LED epitaxial wafer structure and preparation method thereof

Abstract

The application discloses an LED epitaxial wafer structure and a preparation method thereof, and relates to the technical field of semiconductor photoelectric devices. The LED epitaxial wafer structure comprises a substrate and a buffer layer, an N-type limiting layer, an N-type blocking layer, an active layer, a P-type blocking layer, a P-type limiting layer, a P-type window layer and a P-type contact layer which are sequentially stacked on the substrate; the active layer comprises periodically and alternately stacked GaInP quantum dot layers and barrier layers; the GaInP quantum dot layers contain GaInP quantum dots, the density of the GaInP quantum dots is 1*10 9 / cm 2 ~1*10 11 / cm 2 , and the diameter of the GaInP quantum dots is 5nm-40nm. By using the application, the dislocation density can be effectively reduced, the carrier limiting capacity can be improved, the internal quantum efficiency can be improved, and the light efficiency of the LED chip can be finally improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor optoelectronic device technology, and in particular to an LED epitaxial wafer structure and its fabrication method. Background Technology

[0002] Red and yellow LED chips, with their advantages of high reliability, low power consumption, and long lifespan, are widely used in indoor and outdoor displays, automotive brake lights, home appliances, traffic lights, and landscape decoration. Traditional red and yellow LED chip epitaxial wafers typically use an AlGaInP / GaAs material system. The structure of the epitaxial wafer usually includes a GaAs substrate and functional layers epitaxially grown on the GaAs substrate, such as a buffer layer, an N-type confinement layer, a multi-quantum-well active layer, a P-type confinement layer, and a P-type window layer. The multi-quantum-well active layer includes a quantum well layer and a barrier layer. The quantum well layer can be made of AlGaInP or GaInP material, and the barrier layer can also be made of AlGaInP material.

[0003] However, despite the widespread application of the aforementioned LED epitaxial wafer structures, the following technical bottlenecks remain insurmountable in practical applications: Because the active layer of traditional red and yellow LED epitaxial wafers employs a quantum well structure, which is a thin-film structure, lattice mismatch is prevalent between the quantum well layer and the substrate / barrier layer. This results in a high dislocation density in the quantum well layer. These dislocation defects become non-radiative recombination centers for charge carriers, significantly reducing the probability of radiative recombination between electrons and holes, leading to a decrease in the internal quantum efficiency of the LED chip, and consequently, a decrease in luminous efficiency. Furthermore, the traditional quantum well layer has weak confinement capabilities for charge carriers, easily leading to carrier leakage, especially severe at high temperatures, which further reduces the luminous efficiency of the LED chip. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide an LED epitaxial wafer structure and its preparation method, which can effectively reduce dislocation density and improve carrier confinement capability, thereby improving internal quantum efficiency and ultimately improving the luminous efficacy of LED chips.

[0005] To solve the above-mentioned technical problems, the present invention provides an LED epitaxial wafer structure, including a substrate and a buffer layer, an N-type confinement layer, an N-type blocking layer, an active layer, a P-type blocking layer, a P-type confinement layer, a P-type window layer and a P-type contact layer sequentially stacked on the substrate.

[0006] The active layer comprises a periodically alternating stack of GaInP quantum dot layers and a barrier layer;

[0007] The GaInP quantum dot layer contains GaInP quantum dots, and the density of the GaInP quantum dots is 1×10⁻⁶. 9 / cm 2 ~1×1011 / cm 2 The average diameter is 5nm~40nm.

[0008] As an improvement to the above technical solution, the barrier layer includes a GaP barrier layer and an AlGaInP barrier layer stacked sequentially, wherein the GaP barrier layer is stacked on the GaInP quantum dot layer.

[0009] As an improvement to the above technical solution, the thickness of the GaInP quantum dot layer is 2nm~15nm;

[0010] The thickness of the GaP barrier layer is 1 nm to 5 nm.

[0011] The AlGaInP barrier layer has a thickness of 4nm to 20nm, the In content in the AlGaInP barrier layer is 0.2 to 0.7%, and the sum of the Al and Ga contents is 0.3 to 0.8%.

[0012] As an improvement to the above technical solution, the N-type confinement layer is an N-type AlInP electron layer doped with Si, and the Si doping concentration is 1×10⁻⁶. 17 atoms / cm 3 ~1×10 19 atoms / cm 3 The thickness is 100nm~400nm;

[0013] The P-type confinement layer is a Mg-doped P-type AlInP hole layer with a Mg doping concentration of 1×10⁻⁶. 17 atoms / cm 3 ~1×10 19 atoms / cm 3 The thickness is 150nm~350nm.

[0014] As an improvement to the above technical solution, the P-type window layer is a Mg-doped P-type GaP window layer with a Mg doping concentration of 1×10⁻⁶. 18 atoms / cm 3 ~1×10 21 atoms / cm 3 The thickness is 0.5μm~8μm;

[0015] The P-type contact layer is a carbon-doped GaP layer with a carbon doping concentration of 1×10⁻⁶. 20 atoms / cm 3 ~1×10 22 atoms / cm 3 The thickness is 50nm~200nm.

[0016] As an improvement to the above technical solution, the buffer layer is a Si-doped GaAs buffer layer with a Si doping concentration of 1×10⁻⁶. 19 atoms / cm 3 ~1×10 21 atoms / cm 3 The thickness is 100nm~400nm;

[0017] The N-type barrier layer is an N-type AlGaInP barrier layer with a thickness of 20nm~200nm;

[0018] The P-type barrier layer is a P-type AlGaInP barrier layer with a thickness of 20nm~200nm.

[0019] Accordingly, the present invention also provides a method for preparing an LED epitaxial wafer structure, which includes the following steps:

[0020] (1) Provide a substrate for epitaxial growth;

[0021] (2) Deposit a buffer layer on the substrate;

[0022] (3) Deposit an N-type confinement layer on the buffer layer;

[0023] (4) Deposit an N-type barrier layer on the N-type confinement layer;

[0024] (5) Deposit an active layer on the N-type barrier layer;

[0025] (6) Deposit a P-type barrier layer on the active layer;

[0026] (7) Deposit a P-type confinement layer on the P-type barrier layer;

[0027] (8) Deposit a P-type window layer on the P-type confinement layer;

[0028] (9) Deposit a P-type contact layer on the P-type window layer;

[0029] The active layer comprises a periodically alternating stack of GaInP quantum dot layers and a barrier layer;

[0030] The GaInP quantum dot layer contains GaInP quantum dots, and the density of the GaInP quantum dots is 1×10⁻⁶. 9 ~1×10 11 / cm 2 The diameter is 5nm~40nm.

[0031] As an improvement to the above technical solution, the deposition method of the GaInP quantum dot layer includes the following steps:

[0032] a. Under conditions of 500℃~600℃, an In source is pulsedly introduced into the reaction chamber;

[0033] b. Stop the In source and maintain the temperature at 500℃~600℃, then introduce the P source and Ga source into the reaction chamber;

[0034] c. Keep the P source flowing in but stop the Ga source flowing in, maintain the temperature at 500℃~600℃, and interrupt the growth for a preset time;

[0035] Repeat steps a, b, and c several times to obtain a GaInP quantum dot layer.

[0036] As an improvement to the above technical solution, in step a, the time for pulsed introduction of the In source into the reaction chamber is 1s to 40s;

[0037] In step b, the time for introducing the P source and Ga source into the reaction chamber is 10s~25s;

[0038] In step c, the growth is interrupted for 5 to 60 seconds;

[0039] The number of iterations for steps a, b, and c is 2 to 6.

[0040] As an improvement to the above technical solution, in steps a, b and c above, the In source is TMI, the P source is PH3 and the Ga source is TMGa.

[0041] As an improvement to the above technical solution, the method for depositing the barrier layer includes the following steps:

[0042] The growth temperature was controlled at 500℃~600℃, and Ga source and P source were introduced to grow GaP barrier layer.

[0043] The growth temperature was adjusted to 650℃~750℃, and Al source, Ga source, In source and P source were introduced to grow an AlGaInP barrier layer.

[0044] Implementing this invention has the following beneficial effects:

[0045] By replacing the traditional quantum well layer with a GaInP quantum dot layer in the active layer, the three-dimensional confinement effect of the GaInP quantum dot structure can significantly improve the carrier confinement capability, effectively prevent carrier leakage, and better limit Auger recombination, thereby greatly increasing the radiative recombination probability and achieving higher internal quantum efficiency, which can effectively improve the luminescence efficiency of the device.

[0046] Meanwhile, the quantum dot structure of this embodiment effectively relaxes the strain introduced by lattice mismatch, so that the strain introduced by lattice mismatch will not accumulate as in traditional quantum wells, but will be confined around the quantum dot, avoiding the formation of a large number of penetrating dislocations, thereby reducing the density of nonradiative recombination centers, further improving the internal quantum efficiency, and thus further improving the luminous efficiency of the device.

[0047] Furthermore, compared to quantum wells, the quantum dot structure in this embodiment is less sensitive to growth temperature and composition fluctuations, and exhibits better wavelength consistency. Moreover, the carrier transport in the quantum dot structure differs from that in a quantum well; carriers can be transported through resonant tunneling or point-to-point transitions, reducing the device's series resistance and forward operating voltage (Vf). This allows for lower power consumption and improved energy efficiency under the same injection current. Attached Figure Description

[0048] Figure 1 This is a schematic diagram of an LED epitaxial wafer structure according to an embodiment of the present invention;

[0049] Figure 2 yes Figure 1 The schematic diagram of the active layer in the LED epitaxial wafer structure shown in the embodiment is as follows;

[0050] Among them: substrate 1, buffer layer 2, N-type confinement layer 3, N-type barrier layer 4, active layer 5, P-type barrier layer 6, P-type confinement layer 7, P-type window layer 8, P-type contact layer 9, GaInP quantum dot layer 51, and barrier layer 52. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. The present invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the present invention.

[0052] Where specific techniques or conditions are not specified in the embodiments, they shall be performed in accordance with the techniques or conditions described in the literature in this field or in accordance with the product instructions. Raw materials whose manufacturers are not specified are all conventional products that can be obtained commercially.

[0053] like Figure 1 and Figure 2 As shown, this embodiment provides an LED epitaxial wafer structure, including a substrate 1 and a buffer layer 2, an N-type confinement layer 3, an N-type barrier layer 4, an active layer 5, a P-type barrier layer 6, a P-type confinement layer 7, a P-type window layer 8, and a P-type contact layer 9 sequentially stacked on the substrate 1.

[0054] The active layer 5 includes a periodically alternating stacked GaInP quantum dot layer 51 and a barrier layer 52.

[0055] The GaInP quantum dot layer 51 contains GaInP quantum dots, and the density of the GaInP quantum dots is 1×10⁻⁶. 9 / cm 2 ~1×10 11 / cm 2 The average diameter is 5nm~40nm.

[0056] It is worth noting that in this embodiment, a GaInP quantum dot layer 51 is used instead of a traditional quantum well layer in the active layer 5. The GaInP quantum dot layer 51 is a quantum dot structure, and the three-dimensional confinement effect of the quantum dot structure can significantly improve carrier confinement capability, effectively prevent carrier leakage, and better limit Auger recombination, greatly increasing the radiative recombination probability, thereby achieving higher internal quantum efficiency and effectively improving the luminous efficiency of the device. Simultaneously, the quantum dot structure in this embodiment effectively relaxes the strain introduced by lattice mismatch, preventing the strain from accumulating as in traditional quantum wells, instead confining it around the quantum dots. This avoids the formation of a large number of penetrating dislocations, thereby reducing the density of nonradiative recombination centers and further improving internal quantum efficiency, thus further improving the luminous efficiency of the device. Furthermore, compared to quantum wells, the quantum dot structure in this embodiment is less sensitive to growth temperature and compositional fluctuations, and exhibits better wavelength consistency. Moreover, the carrier transport in quantum dot structures differs from that in quantum wells. Carriers can be transported through resonant tunneling or point-to-point transitions, reducing the series resistance and forward operating voltage (Vf) of the device. This allows for lower power consumption and improved energy efficiency under the same injection current.

[0057] Further explanation: the density of GaInP quantum dots in the GaInP quantum dot layer 51 is 1×10⁻⁶. 9 / cm 2 ~1×10 11 / cm 2 The average diameter is 5nm~40nm. The density and size of GaInP quantum dots within this range can effectively confine charge carriers, further reduce charge carrier leakage, and thus further improve luminescence efficiency.

[0058] In one embodiment, the period of the GaInP quantum dot layer 51 and the barrier layer 52 in the active layer 5 is 5 to 20, for example, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 or 20.

[0059] In one embodiment, the barrier layer 52 comprises a GaP barrier layer (not shown) and an AlGaInP barrier layer (not shown) stacked sequentially, with the GaP barrier layer stacked on top of the GaInP quantum dot layer 51. The GaP barrier layer can fix the shape of the quantum dots, preventing In atoms from diffusing outwards from the GaInP quantum dots. The AlGaInP barrier layer has a larger bandgap, which can confine electrons and holes within the GaInP quantum dot layer 51, increasing the carrier recombination probability and further improving optical efficiency.

[0060] In one embodiment, the thickness of the GaInP quantum dot layer 51 is 2nm to 15nm. Within this thickness range, the carrier confinement capability can be further improved and the formation of through-dislocations can be further reduced, thereby further improving the luminous efficiency of the device. Specifically, the thickness of the GaInP quantum dot layer 51 is exemplary to be 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm, or 15nm, but is not limited thereto.

[0061] In one embodiment, the thickness of the GaP barrier layer is 1 nm to 5 nm; specifically, the thickness of the GaP barrier layer within the above range can better prevent In atoms from diffusing outward from the GaInP quantum dot; specifically, the thickness of the GaP barrier layer is, in particular, 1 nm, 2 nm, 3 nm, 4 nm or 5 nm, but is not limited thereto.

[0062] In one embodiment, the thickness of the AlGaInP barrier layer is 4nm to 20nm. A thickness within this range can further enhance carrier confinement. Specifically, the thickness of the AlGaInP barrier layer is exemplary to be 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm, or 20nm, but is not limited thereto.

[0063] In some embodiments, the In content in the AlGaInP barrier layer is 0.2~0.7, and the sum of the Al and Ga contents is 0.3~0.8.

[0064] In one embodiment, the N-type confinement layer 3 is an N-type AlInP electron layer doped with Si, and the Si doping concentration is 1×10⁻⁶. 17 atoms / cm 3 ~1×10 19 atoms / cm 3The thickness is 100nm~400nm. Specifically, the Si doping concentration of the N-type confinement layer 3 is, for example, 1×10⁻⁶. 17 atoms / cm 3 3×10 17 atoms / cm 3 5×10 17 atoms / cm 3 8×10 17 atoms / cm 3 1×10 18 atoms / cm 3 3×10 18 atoms / cm 3 5×10 18 atoms / cm 3 8×10 18 atoms / cm 3 Or 1×10 19 atoms / cm 3 However, it is not limited to this. The thickness of the N-type confinement layer 3 is exemplary to be 100nm, 120nm, 150nm, 180nm, 200nm, 220nm, 250nm, 280nm, 300nm, 320nm, 350nm, 380nm or 400nm, but is not limited to this.

[0065] In one embodiment, the P-type confinement layer 7 is a Mg-doped P-type AlInP hole layer with a Mg doping concentration of 1×10⁻⁶. 17 atoms / cm 3 ~1×10 19 atoms / cm 3 The thickness is 150 nm to 350 nm. Specifically, the Mg doping concentration of the p-type confinement layer 7 is, for example, 1 × 10⁻⁶. 17 atoms / cm 3 3×10 17 atoms / cm 3 5×10 17 atoms / cm 3 8×10 17 atoms / cm 3 1×10 18 atoms / cm 3 3×10 18 atoms / cm 3 5×10 18 atoms / cm 3 8×10 18 atoms / cm 3 Or 1×1019 atoms / cm 3 However, it is not limited to this. The thickness of the P-type confinement layer 7 is exemplary to be 150nm, 180nm, 200nm, 220nm, 250nm, 280nm, 300nm, 320nm or 350nm, but is not limited to this.

[0066] In one embodiment, the P-type window layer 8 is a Mg-doped P-type GaP window layer with a Mg doping concentration of 1×10⁻⁶. 18 atoms / cm 3 ~1×10 21 atoms / cm 3 The thickness is 0.5 μm to 8 μm. Specifically, the Mg doping concentration of the P-type window layer 8 is, for example, 1 × 10⁻⁶. 18 atoms / cm 3 3×10 18 atoms / cm 3 5×10 18 atoms / cm 3 8×10 18 atoms / cm 3 1×10 19 atoms / cm 3 3×10 19 atoms / cm 3 5×10 19 atoms / cm 3 8×10 19 atoms / cm 3 1×10 20 atoms / cm 3 3×10 20 atoms / cm 3 5×10 20 atoms / cm 3 8×10 20 atoms / cm 3 Or 1×10 21 atoms / cm 3 However, it is not limited to this. The thickness of the P-type window layer 8 is exemplary to be 0.5μm, 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm or 8μm, but is not limited to this.

[0067] In one embodiment, the P-type contact layer 9 is a carbon-doped GaP layer with a carbon doping concentration of 1×10⁻⁶. 20 atoms / cm 3 ~1×10 22 atoms / cm 3The thickness ranges from 50 nm to 200 nm. Specifically, the carbon doping concentration of the P-type contact layer 9 is, for example, 1 × 10⁻⁶. 20 atoms / cm 3 3×10 20 atoms / cm 3 5×10 20 atoms / cm 3 8×10 20 atoms / cm 3 1×10 21 atoms / cm 3 3×10 21 atoms / cm 3 5×10 21 atoms / cm 3 8×10 21 atoms / cm 3 Or 1×10 22 atoms / cm 3 However, it is not limited to this. The thickness of the P-type contact layer 9 is exemplary to be 50 nm, 80 nm, 100 nm, 120 nm, 150 nm, 180 nm, or 200 nm, but is not limited to this. In practical applications, the carbon doping concentration and thickness of the P-type contact layer 9 can be flexibly adjusted according to specific needs and process conditions to obtain good performance.

[0068] In one embodiment, the buffer layer 2 is a Si-doped GaAs buffer layer with a Si doping concentration of 1×10⁻⁶. 19 atoms / cm 3 ~1×10 21 atoms / cm 3 The thickness is 100nm~400nm. Specifically, the Si doping concentration of buffer layer 2 is exemplarily 1×10⁻⁶. 19 atoms / cm 3 3×10 19 atoms / cm 3 5×10 19 atoms / cm 3 8×10 19 atoms / cm 3 1×10 20 atoms / cm 3 3×10 20 atoms / cm 3 5×10 20 atoms / cm 3 8×10 20 atoms / cm 3 Or 1×1021 atoms / cm 3 However, it is not limited to this. The thickness of the buffer layer 2 is exemplary to be 100nm, 150nm, 200nm, 250, 300nm, 350nm or 400nm, but is not limited to this.

[0069] In one embodiment, the N-type barrier layer 4 is an AlGaInP barrier layer with a thickness of 20nm to 200nm, exemplarily 20nm, 50nm, 80nm, 100nm, 120nm, 150nm, 180nm or 200nm, but not limited thereto.

[0070] In one embodiment, the P-type barrier layer 6 is an AlGaInP barrier layer with a thickness of 20nm to 200nm, exemplarily 20nm, 50nm, 80nm, 100nm, 120nm, 150nm, 180nm or 200nm, but not limited thereto.

[0071] Specifically, both the N-type barrier layer 4 and the P-type barrier layer 6 are AlGaInP barrier layers, and neither is intentionally doped. The N-type barrier layer 4 and the P-type barrier layer 6 can prevent holes and electrons from leaking into the N-region and P-region, respectively, and force charge carriers to recombine in the luminescent region to further improve luminescence efficiency.

[0072] Accordingly, the present invention also provides a method for preparing an LED epitaxial wafer structure, wherein the epitaxial layer is grown using a metal-organic chemical vapor deposition (MOCVD) device, and includes the following steps:

[0073] (1) A substrate 1 is provided for epitaxial growth;

[0074] In some embodiments, the substrate 1 may be a GaAs substrate, which has a mature fabrication process and good lattice matching with AlGaInP material.

[0075] (2) Deposit a buffer layer 2 on substrate 1;

[0076] In some embodiments, the buffer layer 2 may be a Si-doped GaAs buffer layer. The GaAs buffer layer can effectively improve the lattice defects caused by lattice mismatch and thermal mismatch between the subsequently grown epitaxial layer and the substrate 1, thereby improving the luminescence efficiency.

[0077] In some embodiments, the method for depositing a Si-doped GaAs buffer layer on a GaAs substrate 1 includes the following steps: controlling the reaction chamber temperature at 650°C to 700°C, controlling the reaction chamber pressure at 40 mbar to 80 mbar, using TMGa as the Ga source, AsH3 as the As source, and Si2H6 as the dopant, growing a GaAs buffer layer with a thickness of 100 nm to 400 nm, and a Si doping concentration of 1 × 10⁻⁶. 19 atoms / cm 3 ~1×10 21 atoms / cm 3 .

[0078] (3) Deposit an N-type confinement layer 3 on the buffer layer 2;

[0079] In some embodiments, the N-type confinement layer 3 is an N-type AlInP electronic layer with Si doping.

[0080] In some embodiments, the method for depositing a Si-doped N-type AlInP electronic layer on buffer layer 2 includes the following steps: controlling the reaction chamber temperature at 650°C to 700°C, using TMAl as the Al source, TMIn as the In source, PH3 as the P source, and Si2H6 as the dopant to grow an N-type AlInP electronic layer with a thickness of 100 nm to 400 nm, and a Si doping concentration of 1 × 10⁻⁶. 17 atoms / cm 3 ~1×10 19 atoms / cm 3 .

[0081] (4) Deposit an N-type barrier layer 4 on the N-type confinement layer 3;

[0082] In some embodiments, the N-type barrier layer 4 is an AlGaInP barrier layer. Specifically, the method for depositing the N-type barrier layer 4 on the N-type confinement layer 3 includes the following steps: controlling the reaction chamber temperature at 650°C to 700°C, using TMAl as the Al source, TMGa as the Ga source, TMIn as the In source, and PH3 as the P source to grow an AlGaInP barrier layer with a thickness of 20 nm to 200 nm.

[0083] (5) Deposit an active layer 5 on the N-type barrier layer 4;

[0084] The active layer 5 includes a periodically alternating GaInP quantum dot layer 51 and a barrier layer 52; wherein the GaInP quantum dot layer 51 is prepared by pulsed supply of an In source, and the In source pulse time is 1~40s.

[0085] In some embodiments, the deposition method of the GaInP quantum dot layer 51 includes the following steps:

[0086] a. Under the condition of 500℃~600℃, an In source is pulsedly introduced into the reaction chamber; in this step, there is no P source or Ga source, the In source will decompose on the heated epitaxial layer surface, but cannot form GaInP; In atoms will be adsorbed on the epitaxial layer surface, forming a sub-monolayer, dynamically enriched In atom layer; optionally, the In source is TMIn;

[0087] b. Stop the In source and maintain the temperature at 500℃~600℃. Introduce the P source and Ga source into the reaction chamber. In this step, since the surface is already enriched with a high concentration of In, GaInP with a high In composition will be formed in the initial stage of growth. Driven by the strain energy, the growth mode will immediately change from two-dimensional to three-dimensional, spontaneously nucleating and forming quantum dots. Optionally, the P source is PH3 and the Ga source is TMGa.

[0088] c. Maintain the flow of the P source but stop the flow of the Ga source, and keep the temperature at 500℃~600℃ for a preset time to interrupt the growth. In this step, by interrupting the growth for a preset time, the formed quantum dots are allowed to undergo Oswald ripening, that is, small, unstable dots dissolve, while large, stable dots grow further and become more uniform. It should be noted that the P source needs to be supplied in this step. If the P source is stopped, the P atoms on the GaInP surface and inside will tend to desorb from the solid phase to the gas phase, establish a new equilibrium, and form Ga- or In-rich droplets on the surface, leading to the introduction of a large number of defects.

[0089] Repeat steps a, b, and c several times to obtain GaInP quantum dot layer 51. By repeatedly pulse-introducing TMI, stopping the TMI infusion, introducing TMGa and PH3, and interrupting the growth step, GaInP quantum dot layer 51 is obtained.

[0090] It is worth noting that the growth temperature of the reaction chamber affects the precursor decomposition rate, atomic mobility, and In desorption rate. In this embodiment, when preparing the GaInP quantum dot layer 51, the reaction chamber temperature is controlled at 500℃~600℃ to achieve a balance of the above factors and ensure the structural and compositional stability of the quantum dots. If the growth temperature is too low, although In desorption is less, the atomic mobility is low, which easily forms high-density, small-sized quantum dots, but the crystal quality is slightly worse. If the growth temperature is too high, the atomic mobility is high, which is conducive to the formation of high-quality quantum dots, but In desorption is severe. Specifically, the growth temperature of the GaInP quantum dot layer 51 is exemplarily 500℃, 510℃, 520℃, 530℃, 540℃, 550℃, 560℃, 570℃, 580℃, 590℃, or 600℃, but is not limited to these.

[0091] In some embodiments, in step a, the pulsed introduction of TMIn into the reaction chamber lasts for 1 to 40 seconds, exemplarily 1 to 40 seconds, such as 1 to 40 seconds, but not limited to these. By controlling the TMIn pulse time to 1 to 40 seconds, a foundation is laid to ensure the formation of quantum dots of suitable density and size later. If the TMIn pulse time is too short, fewer In atoms are delivered, only enough to form a limited number of nucleation centers. These nucleation centers will consume subsequently introduced Ga and P to grow, ultimately forming low-density, large-size quantum dots. If the TMIn pulse time is too long, a large number of In atoms are delivered, far exceeding the amount required to form the initial quantum dots. This will lead to the formation of a large number of nucleation centers on the surface of substrate 1, ultimately forming high-density, small-size quantum dots, which can easily lead to quantum dot merging or the formation of rough continuous films, destroying the quantum dot structure.

[0092] In some embodiments, in step b, the time for introducing PH3 and TMGa into the reaction chamber is 10s to 25s.

[0093] In some implementations, in step c, a growth interruption of 5 to 60 seconds is performed; an interruption time in the range of 5 to 60 seconds is beneficial for forming a GaInP quantum dot layer 51 with good uniformity and appropriate density. An excessively long interruption time will significantly reduce the quantum dot density and increase the average size, but the uniformity will be better; an excessively short interruption time will result in a high quantum dot density, but the uniformity may be poor.

[0094] In some implementations, steps a, b, and c are repeated 2 to 6 times, exemplarily 2, 3, 4, 5, or 6 times. This facilitates the formation of GaInP quantum dots with suitable density and size, improving carrier confinement and luminescence efficiency. If the number of cycles is low, the GaInP quantum dot density will be relatively low, the size will be less uniform, and the total volume of the active region will be relatively small, failing to effectively confine carriers and limiting overall luminescence efficiency. With a high number of cycles, the GaInP quantum dot density becomes excessively high, leading to quantum dot merging. The epitaxial layer surface becomes saturated with available nucleation sites, and newly introduced In atoms no longer form new quantum dots. Instead, existing quantum dots grow excessively in both the vertical (height) and horizontal (diameter) directions, causing connections and merging between dots to form irregular large islands. The merged quantum dots lose their quantum confinement advantage, resembling defect-ridden quantum wells, and the QCSE effect reappears, causing luminescence efficiency decay and wavelength drift. Simultaneously, the widened size distribution leads to broadened emission spectral lines, and strain relaxation introduces defects, further reducing carrier radiative recombination efficiency.

[0095] In some embodiments, the deposition method of the barrier layer 52 includes the following steps:

[0096] The growth temperature is controlled at 500℃~600℃, and a GaP barrier layer is grown by introducing Ga and P sources. The GaP barrier layer can quickly freeze the shape of the quantum dots and prevent In atoms from diffusing outward from the quantum dots. Then, the growth temperature is adjusted to 650℃~750℃, and an Al, Ga, In, and P source are introduced to grow an AlGaInP barrier layer. Preferably, TMAl is used as the Al source, TMGa as the Ga source, TMIn as the In source, and PH3 as the P source.

[0097] (6) Deposit a P-type barrier layer 6 on the active layer 5;

[0098] In some embodiments, the P-type barrier layer 6 is an AlGaInP barrier layer. Specifically, the method for depositing the P-type barrier layer 6 on the active layer 5 includes the following steps: controlling the reaction chamber temperature at 650°C to 700°C, controlling the reaction chamber pressure at 50 mbar to 90 mbar, using TMAl as the Al source, TMGa as the Ga source, TMIn as the In source, and PH3 as the P source to grow an AlGaInP barrier layer with a thickness of 20 nm to 200 nm.

[0099] (7) Deposit a P-type confinement layer 7 on the P-type barrier layer 6;

[0100] In some embodiments, the P-type confinement layer 7 is a Mg-doped P-type AlInP hole layer. The method for depositing the P-type AlInP hole layer on the P-type barrier layer 6 includes the following steps: controlling the temperature of the reaction chamber at 600°C to 700°C, controlling the pressure at 50 mbar to 90 mbar, using TMAl as the Al source, TMIn as the In source, PH3 as the P source, and CP2Mg as the dopant to grow the P-type AlInP hole layer.

[0101] (8) Deposit a P-type window layer 8 on the P-type confinement layer 7;

[0102] In some embodiments, the P-type window layer 8 is a Mg-doped P-type GaP window layer. The method for depositing the P-type GaP window layer on the P-type confinement layer 7 includes the following steps: controlling the reaction chamber temperature at 660℃~760℃, controlling the pressure at 40mbar~80mbar, using TMGa as the Ga source, PH3 as the P source, and CP2Mg as the Mg source to grow a P-type GaN window layer with a thickness of 0.5μm~8μm, and the Mg doping concentration can be 1×10⁻⁶. 18 atoms / cm 3 ~1×10 21 atoms / cm 3 .

[0103] (9) Deposit a P-type contact layer 9 on the P-type window layer 8.

[0104] In some embodiments, the P-type contact layer 9 is a carbon-doped GaP layer. The method for depositing the carbon-doped GaP layer on the P-type window layer 8 includes the following steps: controlling the reaction chamber temperature at 550°C to 700°C, controlling the pressure at 50 mbar to 90 mbar, using TMGa as the Ga source, PH3 as the P source, and utilizing the decomposition of the methyl groups of TMGa itself to provide the carbon source, thereby growing a carbon-doped GaP layer with a thickness of 50 nm to 200 nm and a carbon doping concentration of 1 × 10⁻⁶. 20 atoms / cm 3 ~1×10 22 atoms / cm 3 .

[0105] The technical solution of the present invention will be further described below through embodiments and comparative examples.

[0106] Example 1

[0107] An LED epitaxial wafer structure includes a substrate and a buffer layer, an N-type confinement layer, an N-type blocking layer, an active layer, a P-type blocking layer, a P-type confinement layer, a P-type window layer and a P-type contact layer sequentially stacked on the substrate.

[0108] The active layer consists of 12 periodically alternating GaInP quantum dot layers and barrier layers; the barrier layer consists of GaP barrier layers and AlGaInP barrier layers stacked sequentially; wherein, the thickness of the GaInP quantum dot layer is 10 nm, the thickness of the GaP barrier layer is 2 nm, and the thickness of the AlGaInP barrier layer is 12 nm.

[0109] The GaInP quantum dot layer contains GaInP quantum dots, and the density of GaInP quantum dots is 8.5 × 10⁻⁶. 9 / cm 2 The average diameter is 15 nm.

[0110] This embodiment uses MOCVD equipment to grow LED epitaxial wafer structures. The fabrication method of the LED epitaxial wafer structure includes the following steps:

[0111] (1) Provide a substrate for epitaxial growth;

[0112] (2) Deposit a buffer layer on the substrate;

[0113] (3) Deposit an N-type confinement layer on the buffer layer;

[0114] (4) Deposit an N-type barrier layer on the N-type confinement layer;

[0115] (5) Deposit an active layer on the N-type barrier layer;

[0116] (6) Deposit a P-type barrier layer on the active layer;

[0117] (7) Deposit a P-type confinement layer on the P-type barrier layer;

[0118] (8) Deposit a P-type window layer on the P-type confinement layer;

[0119] (9) Deposit a P-type contact layer on the P-type window layer.

[0120] The method for growing GaInP quantum dot layers includes the following steps:

[0121] a. Under the condition of 550℃, TMIn is pulsed into the reaction chamber for 7s.

[0122] b. Stop the flow of TMIn, maintain the temperature at 550℃, and introduce PH3 and TMGa into the reaction chamber for 15 seconds;

[0123] c. Continue to introduce PH3 but stop introducing TMGa, maintain the temperature at 550℃, and interrupt the growth for 30 seconds;

[0124] Repeat steps a, b, and c three times to obtain a GaInP quantum dot layer.

[0125] The method for growing a barrier layer includes the following steps:

[0126] Using TMAl as the Al source, TMGa as the Ga source, TMIn as the In source, and PH3 as the P source, the growth temperature was first controlled at 550℃, and TMGa and PH3 were introduced to grow a GaP barrier layer. Then, the growth temperature was adjusted to 700℃, and TMAl, TMGa, TMIn and PH3 were introduced to grow an AlGaInP barrier layer.

[0127] Comparative Example 1

[0128] This comparative example provides an LED epitaxial wafer structure. The structure and preparation method of the LED epitaxial wafer structure in Comparative Example 1 are basically the same as those in Example 1, except that: the active layer of the LED epitaxial wafer structure in Comparative Example 1 includes 12 periodically alternating GaInP quantum well layers and AlGaInP barrier layers. The thickness of the GaInP quantum well layer is 10 nm, and the thickness of the AlGaInP barrier layer is 12 nm. The GaInP quantum well layer in Comparative Example 1 is prepared using a conventional method.

[0129] Comparative Example 2

[0130] This comparative example provides an LED epitaxial wafer structure. The structure and preparation method of the LED epitaxial wafer structure in Comparative Example 2 are basically the same as those in Example 1. The difference is that the barrier layer of the LED epitaxial wafer structure in Comparative Example 2 is composed only of an AlGaInP barrier layer. The thickness of the AlGaInP barrier layer is 12nm, that is, there is no GaP barrier layer between the GaInP quantum dot layer and the AlGaInP barrier layer.

[0131] Performance testing:

[0132] The LED epitaxial wafer structures obtained in Example 1, Comparative Example 1, and Comparative Example 2 were fabricated into LED chips using the same chip manufacturing process. Their luminous efficiency was tested, and the luminous efficiency improvement rate of Example 1 and Comparative Example 2 was calculated based on Comparative Example 1.

[0133] Light efficiency improvement rate = (Improved light efficiency - Original light efficiency) / Original light efficiency × 100%;

[0134] In the above calculation formula: the original light effect is the same as the light effect of Comparative Example 1.

[0135] Specifically, the test results are shown in Table 1 below:

[0136] Table 1 Performance Test Results

[0137]

[0138] As can be seen from Table 1, by using a GaInP quantum dot layer in the active layer instead of a traditional quantum well layer, the embodiment can effectively reduce dislocation density and improve carrier confinement capability, thereby improving internal quantum efficiency and ultimately improving the luminous efficacy of the LED chip.

[0139] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-described technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. An LED epitaxial wafer structure, characterized in that, It includes a substrate and a buffer layer, an N-type confinement layer, an N-type barrier layer, an active layer, a P-type barrier layer, a P-type confinement layer, a P-type window layer and a P-type contact layer stacked sequentially on the substrate; The active layer comprises a periodically alternating stack of GaInP quantum dot layers and a barrier layer; The GaInP quantum dot layer contains GaInP quantum dots, and the density of the GaInP quantum dots is 1×10⁻⁶. 9 / cm 2 ~1×10 11 / cm 2 The average diameter is 5nm~40nm; The barrier layer comprises a GaP barrier layer and an AlGaInP barrier layer stacked sequentially, wherein the GaP barrier layer is stacked on the GaInP quantum dot layer. The thickness of the GaInP quantum dot layer is 2nm~15nm; The thickness of the GaP barrier layer is 1 nm to 5 nm. The AlGaInP barrier layer has a thickness of 4nm to 20nm, the In content in the AlGaInP barrier layer is 0.2 to 0.7%, and the sum of the Al and Ga contents is 0.3 to 0.8%.

2. The LED epitaxial wafer structure according to claim 1, characterized in that, The N-type confinement layer is an N-type AlInP electron layer doped with Si, and the Si doping concentration is 1×10⁻⁶. 17 atoms / cm 3 ~1×10 19 atoms / cm 3 The thickness is 100nm~400nm; The P-type confinement layer is a Mg-doped P-type AlInP hole layer with a Mg doping concentration of 1×10⁻⁶. 17 atoms / cm 3 ~1×10 19 atoms / cm 3 The thickness is 150nm~350nm.

3. The LED epitaxial wafer structure according to claim 1, characterized in that, The P-type window layer is a Mg-doped P-type GaP window layer with a Mg doping concentration of 1×10⁻⁶. 18 atoms / cm 3 ~1×10 21 atoms / cm 3 The thickness is 0.5μm~8μm; The P-type contact layer is a carbon-doped GaP layer with a carbon doping concentration of 1×10⁻⁶. 20 atoms / cm 3 ~1×10 22 atoms / cm 3 The thickness is 50nm~200nm.

4. The LED epitaxial wafer structure according to claim 1, characterized in that, The buffer layer is a Si-doped GaAs buffer layer with a Si doping concentration of 1×10⁻⁶. 19 atoms / cm 3 ~1×10 21 atoms / cm 3 The thickness is 100nm~400nm; The N-type barrier layer is an N-type AlGaInP barrier layer with a thickness of 20nm~200nm; The P-type barrier layer is a P-type AlGaInP barrier layer with a thickness of 20nm~200nm.

5. A method for fabricating an LED epitaxial wafer structure, characterized in that, The method for preparing the LED epitaxial wafer structure according to any one of claims 1-4 includes the following steps: (1) Provide a substrate for epitaxial growth; (2) Deposit a buffer layer on the substrate; (3) Deposit an N-type confinement layer on the buffer layer; (4) Deposit an N-type barrier layer on the N-type confinement layer; (5) Deposit an active layer on the N-type barrier layer; (6) Deposit a P-type barrier layer on the active layer; (7) Deposit a P-type confinement layer on the P-type barrier layer; (8) Deposit a P-type window layer on the P-type confinement layer; (9) Deposit a P-type contact layer on the P-type window layer; The active layer comprises a periodically alternating stack of GaInP quantum dot layers and a barrier layer; The GaInP quantum dot layer contains GaInP quantum dots, and the density of the GaInP quantum dots is 1×10⁻⁶. 9 ~1×10 11 / cm 2 The diameter is 5nm~40nm.

6. The method for preparing the LED epitaxial wafer structure according to claim 5, characterized in that, The deposition method of the GaInP quantum dot layer includes the following steps: a. Under conditions of 500℃~600℃, an In source is pulsedly introduced into the reaction chamber; b. Stop the In source and maintain the temperature at 500℃~600℃, then introduce the P source and Ga source into the reaction chamber; c. Keep the P source flowing in but stop the Ga source flowing in, maintain the temperature at 500℃~600℃, and interrupt the growth for a preset time; Repeat steps a, b, and c several times to obtain a GaInP quantum dot layer.

7. The method for preparing the LED epitaxial wafer structure according to claim 6, characterized in that, In step a, the In source is pulsed into the reaction chamber for a period of 1 s to 40 s; In step b, the time for introducing the P source and Ga source into the reaction chamber is 10s~25s; In step c, the growth is interrupted for 5 to 60 seconds; The number of iterations for steps a, b, and c is 2 to 6.

8. The method for preparing the LED epitaxial wafer structure according to claim 6, characterized in that, The method for depositing the barrier layer includes the following steps: The growth temperature was controlled at 500℃~600℃, and Ga source and P source were introduced to grow GaP barrier layer. The growth temperature was adjusted to 650℃~750℃, and Al source, Ga source, In source and P source were introduced to grow an AlGaInP barrier layer.

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