Method for low-temperature selective growth of p-type two-dimensional semiconductor thin film and preparation of transistor

Abstract

The application discloses a method for low-temperature selected-area growth of a p-type two-dimensional semiconductor film and preparation of a transistor, and belongs to the technical field of semiconductor devices. The method for low-temperature selected-area growth of a p-type two-dimensional semiconductor film provided by the application comprises the following steps: a 1-4 nm thick Pt metal layer is formed on a substrate surface with a dielectric layer through patterned deposition, and a sample with the Pt metal layer is obtained; sulfur powder and the sample are put into an open container, and sulfuration or selenization is performed through a CVD process; finally, annealing treatment is performed, and a p-type two-dimensional semiconductor film is obtained. The core advantage of the application is that the limitation of a traditional high-temperature preparation process is broken, and the selected-area array growth of p-type two-dimensional material films such as PtS2 and PtSe2 is realized under a low-temperature condition compatible with a back-end-of-line (BEOL) process; on this basis, a transistor array can be directly manufactured, the transfer process of two-dimensional materials is not needed, and the integration of a CMOS circuit can be improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a method for selectively growing p-type two-dimensional semiconductor thin films at low temperatures and the fabrication of transistors. Background Technology

[0002] With the rapid development of IoT and AI technologies, the demand for computing power in integrated circuit information processing and computing chips is increasing daily. To meet this demand, more and more basic device units, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), need to be integrated onto chips. According to Moore's Law, the number of transistors that can be accommodated on an integrated circuit chip roughly doubles every 18 months, and performance also doubles accordingly. However, as the feature size of traditional silicon-based transistors gradually approaches its physical limits, improving device performance faces many challenges, especially the exacerbation of short-channel effects, which severely restricts further miniaturization of transistors. Therefore, exploring new channel materials to continue the advancement of Moore's Law has become an important research direction in the semiconductor field. In recent years, two-dimensional semiconductor materials have received widespread attention due to their unique advantages. Compared with traditional silicon-based materials, two-dimensional semiconductors have atomic-level thickness, no dangling bonds on the surface, tunable band structures, and excellent electrical properties. At extremely small sizes, two-dimensional semiconductors can effectively suppress the short-channel effect caused by gate length miniaturization, while maintaining strong electrostatic control capabilities and achieving high mobility. These characteristics make two-dimensional semiconductors an ideal candidate material for the continued advancement of advanced transistor technology process nodes in the post-Moore era, providing new possibilities for breaking through the physical limits of traditional silicon-based transistors.

[0003] Transition metal chalcogenides such as MoS2 and WS2 have attracted widespread attention due to their tunable band gap, high mobility, and good chemical stability. Currently, most mainstream two-dimensional semiconductor materials (such as MoS2 and WS2) exhibit n-type characteristics, while high-performance p-type two-dimensional semiconductor materials are relatively scarce, and their low-temperature controllable growth and device fabrication still face many challenges.

[0004] In recent years, researchers both domestically and internationally have conducted research on the fabrication technology of p-type two-dimensional semiconductor materials. An improved CVD method has been proposed, which achieves WSe2 growth by controlling a reverse gas flow. WO3 is placed in the high-temperature zone of the tube furnace (close to the substrate), while Se powder is placed in the low-temperature zone (close to the gas flow inlet). During the heating process, a reverse gas flow (from the substrate to the source material) is used to prevent precursor vapor from reaching the substrate prematurely. This method allows for the growth of 800 μm WSe2 single crystals within 10 seconds at 300 °C. Furthermore, high-quality black phosphorus atomic layers have been successfully prepared from bulk black scale crystals using a liquid-phase exfoliation method. However, the preparation of these materials has certain limitations: WSe2 has poor air stability and is easily oxidized in air, readily forming defects such as selenium vacancies. Furthermore, the growth temperature of WSe2 is higher than that of MoS2, and its precursor WO3 has a much higher melting point than MoO3, requiring high-temperature evaporation, which is incompatible with traditional industrial processes. Additionally, selenium's chemical reactivity is lower than that of sulfur, making WSe2 synthesis even more difficult. BP has extremely poor environmental stability, easily oxidized and hydrolyzed in air, requiring additional encapsulation or passivation treatment, severely limiting its practical applications. Moreover, it lacks wafer-level synthesis technology, making it difficult to achieve large-area, high-quality BP thin film growth, failing to meet the demands of large-scale integration. It also exhibits high mechanical brittleness and weak interlayer forces, making it prone to breakage during device fabrication. Therefore, attention has turned to p-type two-dimensional semiconductor materials such as PtSe2 and PtS2, which can be prepared at low temperatures and have better air stability. For PtSe2 growth, Pt thin film deposition was chosen as the precursor, and Se was introduced at low temperature via CVD reaction. Se powder was placed in the upstream region and sublimated at 220℃ to the downstream region where the Pt sheet was placed, at 400℃ for 1 hour, yielding a PtSe2 film of good quality. For PtS2 growth, two methods were used: Pt sheet was inverted on a quartz boat containing S powder, and the gas flow was controlled under an Ar atmosphere, heating at 550℃ for 2 hours to sublimate the S powder and react directly with Pt; alternatively, S powder and Pt were placed in two separate locations, approximately 10 cm apart, and heated at 550℃ for 2 hours, with the S powder sublimated and transported to the Pt surface in gaseous form under Ar atmosphere control. Raman peak characterization revealed the film composition, and electrical performance analysis showed that the film exhibited p-type semiconductor properties.

[0005] Although existing growth methods can produce high-quality p-type two-dimensional semiconductor materials, there are still many key pain points in the low-temperature growth technology of p-type two-dimensional semiconductor materials, which seriously restrict their application in advanced CMOS circuits and new devices. Specifically, the following are the main problems: (1) The growth of existing p-type two-dimensional semiconductor materials mostly depends on high-temperature conditions, which cannot be compatible with the advanced process requirements in traditional industrial production; (2) Even if PtSe2 and PtS2 can be grown at low temperatures, their electrical properties (such as carrier mobility and on / off ratio) are still significantly affected by material thickness, defects and interface state, and the relevant performance control methods are limited, making it difficult to meet the practical requirements of devices; (3) Large-area uniform growth technology still faces bottlenecks, and the crystal quality and thickness control precision of the material are insufficient, which directly affects the stability and consistency of subsequent device performance.

[0006] Based on this, this invention aims to explore the application of P-type two-dimensional semiconductor materials in transistors, and to provide theoretical support and technical pathways for solving key problems in the development of integrated circuits in the post-Moore era. Summary of the Invention

[0007] To address the problems of existing technologies, the present invention aims to provide a method for selectively growing p-type two-dimensional semiconductor thin films at low temperatures and for fabricating transistors. The core innovation of this invention lies in overcoming the limitations of traditional high-temperature fabrication processes. By optimizing key parameters such as precursor thickness, growth temperature, growth time, and subsequent annealing, selective array growth of p-type two-dimensional semiconductor thin films such as PtS2 and PtSe2 is achieved under low-temperature conditions compatible with BEOL. Based on this, transistor arrays can be directly fabricated without additional two-dimensional material transfer processes, and low-temperature three-dimensional monolithic integration of devices can be realized. This invention effectively fills the gaps in current research on low-temperature growth of p-type two-dimensional semiconductors both domestically and internationally. It not only enables the growth of large-area, high-quality, and uniform PtSe2 and PtS2 thin films, solving the core pain points of existing technologies, but also promotes basic research and application development of PtSe2 and PtS2 in the field of two-dimensional semiconductors, enhancing the innovation and practicality of related research. Furthermore, it provides important technical support for the development of high-density integration of new electronic devices (such as GAAFET and CFET) and CMOS circuits in the post-Moore's Law era.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0009] The first aspect of the present invention is to provide a method for selectively growing p-type two-dimensional semiconductor thin films at low temperatures, comprising the following steps:

[0010] A 1-4 nm thick Pt metal layer is patterned and deposited on the surface of a substrate with a dielectric layer to obtain a sample with a Pt metal layer; preferably, the substrate with the dielectric layer is a p-type doped silicon wafer, and the dielectric layer is a silicon oxide layer located on the surface of the p-type doped silicon wafer.

[0011] Sulfur powder and a sample with a Pt metal layer are placed in an open container; then the open container is placed in the same temperature zone as the CVD, with the sulfur powder or selenium powder upstream and the sample with the Pt metal layer downstream, the opening of the open container facing upstream, and then a carrier gas is introduced to perform sulfidation or selenization treatment to form a p-type two-dimensional semiconductor thin film precursor; preferably, the sulfidation or selenization treatment is performed at a temperature of 400°C for 2 hours; the carrier gas is argon.

[0012] The p-type two-dimensional semiconductor thin film precursor is annealed in an S or Se atmosphere to obtain the p-type two-dimensional semiconductor thin film.

[0013] As a preferred technical solution, the material of the p-type two-dimensional semiconductor thin film is PtS2 or PtSe2. These compounds have similar orbital hybridization and band structure, and when the thickness is thin, they are indirect bandgap semiconductors, which can be used as p-type two-dimensional semiconductor materials. However, when the thickness of the PtS2 or PtSe2 thin film is thick, its bandgap will decrease significantly. For example, the bandgap of PtSe2 will decrease to 0, becoming a half-metal; the bandgap of PtS2 will shrink to about 0.25 eV. A bandgap of 0.25 eV is very easily thermally excited at room temperature, which means that even in the "off state" without an applied turn-on voltage, there will be a large number of spontaneously generated electron-hole pairs inside the material, resulting in a high background conductivity (behaving like a half-metal). Therefore, the thickness of the PtS2 or PtSe2 thin film needs to be strictly controlled in this invention. This invention obtains the target thin film by first preparing a 1-4 nm thick Pt metal layer, which can effectively control the thickness of the thin film.

[0014] As a preferred technical solution, the annealing temperature is 400℃ and the time is 2 hours. Due to the low thermal budget of low-temperature CVD processes, the initially grown films often exhibit incomplete reactions and high sulfur vacancy densities. These defects not only disrupt the long-range order of the crystal lattice but also introduce additional interstitial energy states, leading to high background carrier concentration and large off-state leakage current. Annealing in a sulfur-rich environment can effectively promote the filling of these vacancies by gaseous sulfur atoms, restoring the stoichiometry of the material. Furthermore, the thermal energy provided by the annealing process promotes secondary atomic rearrangement and grain boundary fusion, releasing the residual stress caused by sulfidation expansion and significantly improving the crystallinity of the film. This is confirmed by the reappearance of out-of-plane vibrational modes representing high crystallinity in Raman spectroscopy.

[0015] A second aspect of the present invention is to provide a transistor fabrication method based on the method described in the first aspect above, comprising the following steps:

[0016] A p-type two-dimensional semiconductor thin film is prepared using the method described in the first aspect above. Then, source and drain metal electrodes are deposited on the p-type two-dimensional semiconductor thin film to form the source and drain electrodes, thus obtaining a transistor. Further fabrication of the top-gate dielectric and top-gate electrode is possible to form a transistor with a dual-gate structure. This method enables selective growth of p-type two-dimensional semiconductor thin films at low temperatures and allows for the direct fabrication of dual-gate transistor arrays without a transfer process.

[0017] As a preferred technical solution, the source / drain electrode formed by the combination of the source and drain electrodes is made of Ni / Au, Cr / Au, or Ti / Au.

[0018] The present invention has the following beneficial effects:

[0019] In the low-temperature selective growth method for p-type two-dimensional semiconductor thin films provided by this invention, the thickness of the p-type two-dimensional semiconductor thin film must be strictly controlled to be 1nm-4nm, because the properties of this layer are closely related to its thickness. Taking PtS2 material as an example, as the thickness (number of layers) of the PtS2 material layer increases, its band gap gradually narrows due to the weakening of the quantum confinement effect and the enhancement of interlayer interactions. When the thickness reaches the bulk phase (>4nm), the band gap of PtS2 shrinks to about 0.25 eV. A band gap of 0.25 eV is very easily thermally excited at room temperature, which means that even in the "off state" without an applied turn-on voltage, there will be a large number of spontaneously generated electron-hole pairs inside the material, resulting in a very high background conductivity (behaving like a half-metal). If it is used to make transistors, the leakage current will be extremely large, and the device cannot be turned off at all, resulting in a device that cannot achieve the desired performance. However, in the thin-layer state (1nm-4nm), due to the strong quantum confinement effect, the band gap of PtS2 will significantly increase to about 1.6 eV. This wide bandgap effectively suppresses thermal excitation of charge carriers at room temperature, ensuring that the device has low leakage current in the off state.

[0020] The method for low-temperature selective growth of p-type two-dimensional semiconductor thin films provided by this invention is primarily applied to the construction of CMOS circuits based on advanced transistor processes. Specifically, it is adaptable to the fabrication of GAAFETs and CFETs, and simultaneously enables low-temperature three-dimensional monolithic integration of transistor devices, effectively improving device density. This invention precisely deposits a Pt metal layer on a substrate material, and then prepares a p-type two-dimensional semiconductor thin film via CVD processing at a relatively low temperature compatible with BEOL. Based on this, transistor arrays can be directly fabricated without additional two-dimensional material transfer processes. This method enables large-scale array fabrication with low heat loss and seamlessly integrates with existing industrial processes, effectively overcoming the limitations of existing technologies such as high-temperature fabrication incompatibility with BEOL, high material transfer loss, and low integration density. The advantages include:

[0021] Filling the gap in p-type materials and adapting to advanced CMOS architectures: The introduction of low-temperature selective growth process not only effectively breaks through the physical limitations of traditional silicon-based semiconductors, but also fills the gap in the scarcity of high-performance p-type materials in the existing two-dimensional semiconductor field. It provides key material support for the construction of advanced architecture CMOS complementary devices such as GAAFET and CFET, greatly optimizes the overall electrical complementary characteristics of the devices, and helps to upgrade the performance of advanced CMOS circuits.

[0022] Improving material quality, optimizing carrier transport, and reducing transfer losses: By precisely controlling the thermodynamic and kinetic conditions of growth, lattice defects (such as vacancies and grain boundaries) during the growth of p-type two-dimensional materials such as PtS2 and PtSe2 can be effectively reduced, significantly improving the hole mobility and carrier transport efficiency of the materials, laying a solid material foundation for the performance of low-power devices; at the same time, there is no need for two-dimensional material transfer, avoiding problems such as material damage and contamination during the transfer process, further ensuring the performance consistency of transistor arrays.

[0023] Adaptable to large-scale industrial production and compatible with diverse advanced device processes: Employing BEOL-compatible low-temperature CVD processes, selective growth of p-type two-dimensional semiconductor thin films is achieved. This enables the preparation of large-area, highly uniform, and thickness-controllable thin films, while also perfectly compatible with flexible substrates and CMOS back-end processes, meeting the needs of large-scale industrial production. Furthermore, it enables low-temperature three-dimensional monolithic integration of devices, breaking through the limitations of traditional integration modes, further improving the integration level of CMOS circuits, and adapting to the development trend of ultra-large-scale integrated circuits. Attached Figure Description

[0024] Figure 1 AFM images of Pt layers with a thickness of 1.5 nm deposited using different devices in Example 1;

[0025] Figure 2 This is a schematic diagram of the apparatus structure in the CVD process of the present invention;

[0026] Figure 3 Raman characterization images of PtS2 films prepared for different sulfidation times;

[0027] Figure 4 Raman characterization images of PtS2 films prepared by different sulfidation methods;

[0028] Figure 5 This is a flowchart of the transistor fabrication process in Example 2;

[0029] Figure 6 An optical microscope image of the semiconductor device obtained in Example 2;

[0030] Figure 7 for Figure 6 Partial schematic diagram and test parameter description;

[0031] Figure 8 The results are the performance test results of the semiconductor state PtS2 in Example 2;

[0032] Figure 9 The electrical performance diagram of the device prepared in Example 2 is shown below;

[0033] Figure 10 This is a performance comparison chart between the device prepared in Comparative Example 1 and the device prepared in Example 2.

[0034] Figure reference numerals: 1-substrate, 2-dielectric layer, 3-p-type two-dimensional semiconductor thin film, 4-source, 5-drain, 8-sample, 9-sulfur powder, 10-open test tube. Detailed Implementation

[0035] The present invention will be further described below with reference to embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments are not intended to limit the present invention. In addition, unless otherwise specified, the preparation processes in the following embodiments are all conventional methods in the prior art, and therefore will not be described in detail.

[0036] Example 1

[0037] A method for selectively growing p-type two-dimensional semiconductor thin films at low temperatures, wherein SiO2 is selected as the dielectric layer, Pt is selected as the deposition metal, and the material of the p-type two-dimensional semiconductor thin film is PtS2, specifically including the following steps:

[0038] Step 1: The SiO2 / Si substrate was ultrasonically cleaned with acetone and isopropanol for 15 minutes in sequence, and then dried in an oven at 70 °C. In this embodiment, substrate 1 is a p-type heavily doped Si wafer, with SiO2 as the oxide layer, about 300 nm thick, which is low resistivity silicon, and the 300 nm SiO2 is used as dielectric layer 2.

[0039] Step 2: After defining the channel pattern through photolithography exposure and development, a Pt film with a thickness in the range of 1-4 nm is deposited on the top surface of dielectric layer 2 using a deposition equipment. The film is then immersed in acetone at 80 °C for 2 h for resist removal. The quality of the deposited film is evaluated using AFM scanning. In this embodiment, three devices were used to deposit Pt: Sputter PVD75 (rate 0.58 Å / s), Ebeam LAB18 (rate 0.6 Å / s), and Ebeam PVD75 (rate 0.2 Å / s). The AFM comparison images of the Pt layers obtained from these three devices are shown below. Figure 1 , Figure 1 Figures A, B, and C correspond to the Sputter PVD75, EbeamLAB18, and Ebeam PVD75, respectively. From... Figure 1 As shown in Figure C, the Ebeam PVD75 equipment achieves a Pt roughness (Rq) of only 0.15 nm when depositing 1.5 nm Pt. The deposition rate is slow but controllable, resulting in good film quality. The other two equipment exhibit larger fluctuations in deposition rate, leading to poorer roughness. Therefore, the Ebeam PVD75 equipment was used to deposit Pt films of varying thicknesses in subsequent experiments.

[0040] Step 3: A schematic diagram of the apparatus used in the CVD process of this invention is shown below. Figure 2 , Figure 2 The direction of the middle arrow indicates the direction of carrier gas flow. An open test tube 10 is used as the open container. Sample 8 and sulfur powder 9 from step 2 are placed in an open test tube 10, and then placed in the same temperature zone of the CVD reactor. Sulfur powder 9 is located in the upstream region, and the sulfur powder serves as the sulfur source. The distance between sample 8 and the sulfur powder is 10 cm. The argon carrier gas flow rate is 50 sccm. Curing is performed at 400℃ for 1 h and 2 h, respectively. Raman spectroscopy is conducted on the films with different curing times to evaluate their quality.

[0041] Based on existing knowledge, when the main component of the film is PtS, only one characteristic peak can be observed in the Raman test, at 332, indicating incomplete sulfurization. When the main component of the film is PtS2, if excessive sulfurization occurs, two characteristic peaks can be observed, namely E... g The peak is at 303, A 1g 2 The peak is at 344; when the main component of the film is PtS2 and the sulfidation quality is good, three characteristic peaks can be observed in the film, namely E g The peak is at 303, A 1g 1 The peak is at 336, A 1g 2 The peak is at 344.

[0042] Raman test results of the films obtained by sulfurization at 400℃ for 1 h and 2 h respectively are shown below. Figure 3 ,from Figure 3 The Raman spectroscopy results show that sulfidation at 400 °C for 2 h yields a high-quality film, while sulfidation at 400 °C for 1 h results in a film primarily composed of PtS. To meet the requirements of low-temperature processing, this experiment adopted a sulfidation temperature of 400 °C and a sulfidation time of 2 h, resulting in a high-quality two-dimensional semiconductor PtS2 film.

[0043] Furthermore, the experimental results showed that if the step of placing the sample into an open test tube is omitted, and the sample and sulfur powder are placed directly into the CVD process equipment at a 10cm interval, the resulting film does not have a good sulfurization state. Figure 4 The Raman characterization images of the PtS2 film prepared by the open-tube CVD process according to the present invention and the PtS2 film obtained by placing Pt and S in an open tube with a 10cm gap in the prior art, and by directly inverting Pt onto S, show that the PtS2 film obtained by the process of this application can clearly observe three characteristic peaks, and the sulfurization effect is the best.

[0044] Step 4: Place the PtS2 film with better quality obtained by sulfurization for 2 hours back into the CVD process equipment and perform an annealing treatment in an S atmosphere at a temperature of 400 ℃ for 2 hours to obtain a PtS2 film with even better quality.

[0045] Example 2

[0046] The fabrication of a transistor includes the following steps:

[0047] A PtS2 thin film was prepared according to the method in Example 1. The source and drain patterns were defined by photolithography exposure and development. A 10 nm Ni / 30 nm Au layer was deposited by electron beam deposition. After lift-off and resist removal, metal source 4 and drain 5 were formed, completing the fabrication of the transistor device. The process flow diagram for the above fabrication is shown below. Figure 5 Optical microscope images of the entire device are shown below. Figure 6 .

[0048] Performance testing

[0049] The resistivity of the PtS2 thin film in the device prepared by the above process was tested. See [link to test parameter description] for details. Figure 7 , Figure 7 W ch L represents the channel width. ch This represents the channel length. With the same channel width, the IV characteristic curves of devices with different channel lengths are measured, the resistance of each device is calculated, and then the resistances of these devices are plotted as a linear graph. The slope multiplied by the channel width gives the resistivity of the PtS2 thin film.

[0050] Test results are available Figure 8 , Figure 8 Figure A shows the IV characteristic curve of the device, and Figure B shows the sheet resistivity. The slope in Figure B is 91246.78288, multiplied by the W of this batch of devices. ch =5 μm, the calculated resistivity is 4.5623 × 10 5 Ω / □ (sheet resistance, measured in ohms per square unit area, refers to the resistivity per unit area per unit thickness of a material), while the resistivity of the semiconductor PtS2 is 10 Ω / □. 5 -10 6 The material exhibits properties consistent with semiconductor-state PtS2. The testing equipment consisted of a semi-automatic electrical probe station and a semiconductor analyzer. The testing process was conducted in a nitrogen atmosphere to prevent performance degradation due to air exposure. Hall effect measurements were then performed to assess the carrier concentration.

[0051] The electrical performance of the final device fabricated using a low-temperature process was tested, with the drain voltage (V) measured during the test. d The gate voltage (V) is set to -1 V. g A sweep was performed from 100 V to -100 V, and normalized current transfer characteristic curves for different channel lengths were plotted based on the test results. The results are shown in [Figure number missing]. Figure 9 .

[0052] from Figure 9 It can be seen that a semiconductor device with good electrical properties can be obtained by curing at 400 °C for 2 h followed by annealing in an S atmosphere for 2 h, with an on-state current reaching the nA / μm level and an on / off ratio reaching 10. 4 .

[0053] Comparative Example 1

[0054] Compared with Example 2, the only difference of Comparative Example 1 is that the annealing step is omitted, while all other processes are the same as in Example 2.

[0055] The performance comparison graph between the device prepared in Comparative Example 1 and the device prepared in Example 2 is shown in the figure. Figure 10 ,from Figure 10 It can be seen that the devices prepared by the annealing process have more stable performance.

[0056] The technical solution of this invention is specifically optimized to address core issues in p-type two-dimensional semiconductor devices and advanced CMOS circuits, and is particularly suitable for the following fields:

[0057] In the field of low-power advanced electronic devices: p-type two-dimensional semiconductors have the core advantages of high carrier mobility, excellent switching characteristics and low leakage current. Combined with the thin film material prepared by the low-temperature selective growth process of this invention, the energy loss during device operation can be significantly reduced by precisely controlling the carrier transport process, which meets the core requirements of portable electronic devices and IoT terminals for low power consumption and long battery life. At the same time, the low-temperature preparation characteristics are compatible with low thermal stability substrates such as flexible substrates, further expanding its application scenarios in flexible low-power advanced devices.

[0058] In the field of advanced CMOS integrated circuits, traditional two-dimensional semiconductors are mainly n-type, and their high-temperature fabrication processes are incompatible with BEOL (Body-on-Loop) technology, making it difficult to achieve high-performance two-dimensional CMOS integration and three-dimensional monolithic integration. The p-type two-dimensional semiconductor thin film prepared in this invention possesses excellent p-type characteristics and can form a highly efficient complementary structure with n-type two-dimensional semiconductors, successfully constructing advanced architecture CMOS devices such as all-two-dimensional material-based GAAFETs and CFETs. Its high-quality, high-consistency thin film and the ability to directly fabricate transistor arrays effectively ensure the performance uniformity of the device array. Combined with low-temperature three-dimensional monolithic integration capabilities, it further improves the integration density and computing speed of integrated circuits, perfectly meeting the development needs of ultra-large-scale, high-density CMOS circuits.

[0059] In summary, this invention utilizes innovative low-temperature selective growth technology to achieve precise fabrication of p-type two-dimensional semiconductor thin films such as PtS2 and PtSe2, and direct manufacturing of transistor arrays. It eliminates the need for material transfer processes, is compatible with BEOL technology, and enables low-temperature three-dimensional monolithic integration. This allows for large-scale industrial applications and provides a novel solution for the development of high-performance p-type two-dimensional semiconductor transistor devices and the upgrading of advanced CMOS circuits.

[0060] Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

Claims

1. A method for fabricating a transistor, characterized in that, Includes the following steps: A 1-4 nm thick Pt metal layer is patterned and deposited on the surface of a substrate with a dielectric layer to obtain a sample with a Pt metal layer. Sulfur powder and a sample with a Pt metal layer are placed in an open container; then the open container is placed in the same temperature zone as the CVD, with the sulfur powder or selenium powder upstream and the sample with the Pt metal layer downstream, and the opening of the open container facing upstream. Then a carrier gas is introduced to perform sulfidation or selenization treatment to form a p-type two-dimensional semiconductor thin film precursor; the sulfidation or selenization treatment is performed at a temperature of 400°C for 2 hours. The p-type two-dimensional semiconductor thin film precursor was annealed in an S atmosphere to obtain the p-type two-dimensional semiconductor thin film; the annealing temperature was 400℃; the material of the p-type two-dimensional semiconductor thin film was PtS2. Then, source and drain metal electrodes are deposited on a p-type two-dimensional semiconductor thin film to form the source and drain, thus obtaining a transistor.

2. The preparation method according to claim 1, characterized in that, The substrate with the dielectric layer is a p-type doped silicon wafer, and the dielectric layer is a silicon oxide layer located on the surface of the p-type doped silicon wafer.

3. The preparation method according to claim 1, characterized in that: The annealing process takes 2 hours.

4. The preparation method according to any one of claims 1 to 3, characterized in that: The carrier gas is argon.

5. The preparation method according to claim 1, characterized in that, The source / drain electrode formed by the combination of the source and drain electrodes is made of Ni / Au, Cr / Au, or Ti / Au.

6. The preparation method according to claim 1, characterized in that, It also includes the preparation of top gate dielectric and top gate electrode to form a transistor with a dual-gate structure.

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