Improved dynamic random access memory (DRAM) efficiency calculation and last level cache (LLC) utilization

Abstract

Various embodiments include systems and methods for improving dynamic random access memory (DRAM) efficiency and last level cache (LLC) utilization. The computing system may be configured to dynamically adjust DRAM efficiency calculations based on multiple system metrics and conditions (e.g., DDR frequency, density, refresh rate, etc.) to achieve more accurate frequency settings and improved power consumption. A computing system may use a multi-stage approach that includes memory and cache allocation, bandwidth management, and frequency setting. A computing system may trim DRAM efficiency calculations based on various other factors (e.g., cache miss rate, power consumption, etc.), dynamically modify operating parameters (e.g., DDR frequency, etc.) in response to a particular event or computing task, and cooperate with other system components (e.g., last level cache controller (LLCC), etc.) to improve resource allocation.

Description

[0001] Related applications

[0002] This application claims the benefit of priority to U.S. nonprovisional application No. 18 / 475,492, filed September 27, 2023, the entire contents of which are incorporated herein by reference. Background Technology

[0003] Recent advances in power management and memory technologies have significantly improved the performance and efficiency of modern computing devices. These technologies strike a balance between computing power and energy consumption, thereby improving performance while minimizing strain on device resources. Therefore, these technologies can be particularly important in systems and environments where energy efficiency is a significant concern, such as in mobile devices.

[0004] Dynamic Random Access Memory (DRAM) is a popular memory technology used in modern computing systems. DRAM typically interfaces via Double Data Rate (DDR) channels. DDR memory has undergone several generations of iterations, with each generation offering higher bandwidth and lower power consumption than its predecessor. DRAM and DDR memory systems work in conjunction with other power management and memory technologies to increase throughput and reduce energy usage.

[0005] Dynamic Clock and Voltage Scaling (DCVS) is an important power management technique that dynamically adjusts the frequency and voltage of one or more processors based on workload and other variables. By doing so, DCVS can improve the power consumption and heat dissipation characteristics of a computing device without materially negatively impacting its computing performance. For example, DCVS can reduce the clock speed and voltage in response to determining that an application processor (AP) in the device is currently underutilized, thereby improving the device's power consumption characteristics.

[0006] Partial Array Self-Refresh (PASR) is another important power management technique that selectively disables portions of DRAM when they are not in use to reduce power consumption. Therefore, PASR is particularly useful in systems and environments where energy efficiency is a significant concern, such as in mobile devices. Summary of the Invention

[0007] Various aspects include methods for improving memory bandwidth in computing devices. In some aspects, methods may include: determining whether a new DDR bandwidth (BW) requirement has been received for double data rate (DDR) dynamic random access memory (DRAM) in the computing device; determining whether there is a change in the DDR refresh rate or DDR density of the DDR DRAM; determining whether the DDR DRAM can operate at its maximum operating frequency; and determining a DRAM efficiency value based on at least one or more of the following: whether a new DDR BW requirement has been received, whether there is a change in the DDR refresh rate or DDR density, or whether the DDR DRAM can operate at its maximum operating frequency. Some aspects may also include: using the determined DRAM efficiency value to perform dynamic clock and voltage scaling (DCVS) operations that scale the clock frequency, DDR frequency, or supply voltage in the computing device.

[0008] Some aspects may also include: determining the availability of unused Last Level Cache (LLC) lines in response to determining that a new DDR BW request has been received; dynamically assigning unused LLC lines to clients with high DDR BW demand; and transmitting feedback to clients with high DDR BW demand to update the BW request. In some aspects, determining whether there is a change in the DDR refresh rate or DDR density of the DDR DRAM may include determining whether there is a change in the DDR refresh rate or DDR density of the DDR DRAM in response to determining that a new DDR BW request has not yet been received. Some aspects may also include: generating a data repository that maps DRAM efficiency to a function of DDR BW, DDR density, and DRAM refresh rate; determining DRAM efficiency values ​​based on information included in the generated data repository; and determining DDR frequency values ​​based on the determined DRAM efficiency values.

[0009] In some aspects, determining whether DDR memory can operate at the upper limit operating frequency can be performed in response to determining a change in DDR refresh rate or DDR density where DDR memory is not present. Some aspects may also include: in response to determining that a client assigned a Last Level Cache (LLC) line may not be effectively using the assigned LLC line, flushing the underutilized LLC line; assigning the newly flushed LLC line to a client with high DDR BW requirements; and sending feedback to the client with high DDR BW requirements to update the BW requirement. Some aspects may also include: determining whether further adjustments to DRAM efficiency values ​​or assigned LLC lines would better balance the trade-off between performance and power consumption in the computing device. Some aspects may also include: in response to determining that further adjustments to DRAM efficiency values ​​or assigned LLC lines would better balance the trade-off between performance and power consumption in the computing device, determining, based on information stored in a priority table, subsystems of the computing device that can be placed in Low Power Mode (LPM), traversing the determined subsystems to identify low-priority subsystems that may include high DDR BW requirements, and putting the identified low-priority subsystems into LPM.

[0010] Another aspect may include a computing device having a processing system configured with processor-executable instructions to perform various operations corresponding to the methods described above. Another aspect may include a non-transitory processor-readable storage medium having processor-executable instructions stored thereon, these instructions being configured to cause the processing system to perform various operations corresponding to the operations of the methods described above. Another aspect may include a computing device having various components for performing functions corresponding to the operations of the methods described above. Attached Figure Description

[0011] The accompanying drawings, which are incorporated herein and form part of this specification, illustrate exemplary embodiments of the claims and, together with the general description and detailed description given, serve to explain the features of this document.

[0012] Figure 1 This is a component block diagram illustrating example components that can be included in a computing device and configured to implement some implementation scheme in a system-in-package (SIP).

[0013] Figure 2 It is a component block diagram illustrating example components and operations in a system configured to implement some implementation schemes.

[0014] Figures 3A to 3EThis is a flowchart illustrating a method for improving the performance and battery consumption characteristics of a computing system by improving the use of dynamic random access memory (DRAM) and last-level cache (LLC) in a computing system, according to some implementation schemes.

[0015] Figure 4 This is a component block diagram of an example computing device in the form of a laptop computer, suitable for implementing some implementation schemes.

[0016] Figure 5 This is a component block diagram illustrating an example wireless communication device suitable for use with various implementation schemes.

[0017] Figure 6 This is a component diagram of an example server suitable for implementing some implementation schemes. Detailed Implementation

[0018] Various embodiments will be described in detail with reference to the accompanying drawings. Where possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. References to specific examples and embodiments are for illustrative purposes and are not intended to limit the scope of the claims.

[0019] Various implementation schemes include methods for improving memory bandwidth in computing devices by determining DDR dynamic random access memory (DRAM) efficiency values ​​based on at least one or more of the following: whether a new double data rate (DDR) bandwidth requirement has been received, whether there is a change in DDR refresh rate or DDR density, or whether DDR DRAM is operating at the upper limit operating frequency; and using DRAM efficiency values ​​to perform dynamic clock and voltage scaling (DCVS) operations.

[0020] The term "computing device" in this document may refer to any or all of the following: personal computer, laptop computer, tablet computer, user equipment (UE), smartphone, personal or mobile multimedia player, personal data assistant (PDA), handheld computer, wireless email receiver, cellular phone with multimedia internet support, gaming system (e.g., PlayStation). ™ Xbox ™ Nintendo Switch ™ Wearable devices (e.g., headphones, smartwatches, head-mounted displays, fitness trackers, etc.), media players (e.g., DVD players, ROKU...), etc. ™ Apple TV ™ Digital video recorders (DVRs), automotive displays, portable projectors, 3D holographic displays, and other similar devices including displays and programmable processing systems that can be configured to provide functionality for various implementation schemes.

[0021] The term "processing system" is used herein to refer to one or more processors, including multi-core processors, that are organized and configured to perform various computational functions. Various implementation methods can be implemented in one or more of the multiple processors within a processing system as described herein.

[0022] The term "System-on-a-Chip" (SoC) is used herein to refer to a single integrated circuit (IC) chip containing multiple resources or independent processors integrated on a single substrate. A single SoC may contain circuitry for digital, analog, mixed-signal, and radio frequency functions. A single SoC may include a processing system comprising any number of general-purpose or specialized processors (e.g., network processors, digital signal processors, modem processors, video processors, etc.), blocks of memory (e.g., ROM, RAM, flash memory, etc.), and resources (e.g., timers, voltage regulators, oscillators, etc.). For example, an SoC may include an application processor operating as the SoC's main processor, central processing unit (CPU), microprocessor unit (MPU), arithmetic logic unit (ALU), etc. An SoC may also include software for controlling the integrated resources and processors, as well as software for controlling peripheral devices.

[0023] The term "System-in-Package" (SIP) may be used herein to refer to a single module or package that contains multiple resources, computing units, cores, or processors on two or more IC chips, substrates, or SoCs. For example, a SIP may comprise a single substrate on which multiple IC chips or semiconductor dies are stacked in a vertical configuration. Similarly, a SIP may comprise one or more multi-chip modules (MCMs) on which multiple ICs or semiconductor dies are packaged into a single substrate. A SIP may also comprise multiple independent SoCs coupled together and packaged adjacently (e.g., on a single motherboard, in a single UE, or in a single CPU device) via high-speed communication circuitry. The proximity of SoCs facilitates high-speed communication and the sharing of memory and resources.

[0024] Dynamic Clock and Voltage Scaling (DCVS) is a power management technique used in modern computing devices, such as smartphones, tablets, etc., to improve device performance, energy consumption, and / or thermal performance characteristics. A DCVS system dynamically scales clock frequency, DDR frequency, and supply voltage based on workload requirements to balance performance and energy consumption tradeoffs. Under low workload conditions, a DCVS system can reduce clock frequency and voltage to save energy. During high-demand tasks, a DCVS system can increase these parameters to improve performance. Some implementations may include computing systems equipped with a DCVS system configured to further improve the performance and energy consumption characteristics of the computing device by performing scaling operations that take into account variable / dynamic DRAM efficiency values.

[0025] Dynamic Last Cache (LLC) is an adaptable, real-time management feature that can be integrated into the final cache level of a computer's memory hierarchy. Unlike static cache configurations with predetermined sizes and policies, dynamic LLC systems dynamically adjust parameters such as size, associativity, and power states based on current workload demands. This dynamic nature improves the performance, efficiency, and power consumption characteristics of computing devices. For example, dynamic LLC can improve processor data access speed by allocating more cache space or adjusting its policies to minimize cache misses when performing high-performance tasks. During periods of lower demand, dynamic LLC can shrink its size or enter a low-power state to conserve energy.

[0026] Partial Array Self-Refresh (PASR) is an energy-saving technique included in dynamic random access memory (DRAM) systems in modern computing devices such as smartphones, tablets, servers, etc. PASR selectively refreshes only the actively used portions of the memory array, while allowing other unused segments to enter a low-power state. This selective approach contrasts with traditional full-array refresh solutions, which refresh the entire DRAM array regardless of whether all segments are in use (and thus consume more energy). By reducing the number of refresh cycles for currently unaccessed portions of the memory, PASR effectively reduces overall power consumption on the device, thus helping to extend battery life in mobile devices and reduce energy costs in data centers.

[0027] Dynamic Random Access Memory (DRAM) is a volatile memory commonly used in modern computing devices such as smartphones and tablets to temporarily store data and instructions that are currently in use or "in processing." The popularity and use of DRAM have grown significantly in recent years because it allows for fast read / write access to the central processing unit (CPU) at a relatively lower cost and higher density than other types of memory, such as Static Random Access Memory (SRAM). Integrating DRAM into such systems can improve overall performance by allowing for smooth multitasking, fast application loading, and efficient execution of complex tasks. With the continued growth in demand for enhanced functionality and user experience in mobile devices, DRAM remains a widely used component to meet these evolving needs.

[0028] Double Data Rate (DDR) memory is a special-purpose type of DRAM configured to double the data transfer rate by operating on both the rising and falling edges of a clock signal. In modern mobile devices such as smartphones and tablets, DDR memory is typically used as main system memory, allowing for faster and more efficient task processing. With increasing demand for devices capable of running complex applications, streaming high-definition content, and supporting multitasking, DDR memory has become a widely adopted solution, meeting the growing need for enhanced functionality and providing a smoother user experience and more responsive device operation.

[0029] A DDR channel is a path that allows data transfer between the memory controller and the DDR memory module. A DDR system may have one or more channels (e.g., single-channel, dual-channel, or multi-channel configurations). The number of channels may be based on memory bandwidth requirements and / or the memory controller's "memory configuration" or architecture.

[0030] Memory configuration plays a substantial role in determining the overall performance and efficiency of modern computing devices. Multichannel memory configurations (e.g., dual-channel, quad-channel, etc.) typically include multiple data paths or "channels" between the memory modules and the memory controller, which can improve data transfer rates by enabling simultaneous read or write operations across multiple channels. A "single-channel DDR configuration" is a memory configuration with a single data path (DDR channel) between the memory controller and the DDR memory modules. Single-channel DDR configurations do not have as much bandwidth as their multichannel counterparts, but are generally more cost-effective. Single-channel DDR configurations typically allow computing devices to perform tasks well enough for most users while maintaining reasonable battery life and cost structure. Therefore, single-channel DDR configurations are commonly used in modern computing devices to balance performance and resource utilization while meeting other design requirements such as cost, power consumption characteristics, and form factor.

[0031] DRAM efficiency is a crucial characteristic of modern computing devices, used to determine how well a DDR memory system performs under real-world operating conditions (as opposed to considering only its theoretical specifications). Accurately determining DRAM efficiency values ​​allows computing systems to better calibrate memory operating speeds (e.g., as part of DCVS operation). For example, high DRAM efficiency at a given DDR frequency indicates that the system is making full use of its resources at that frequency level and is well-suited for high-performance tasks. Conversely, low DRAM efficiency at higher DDR frequencies suggests that further increases in DDR frequency may not yield a proportional performance increase and could even negatively impact the device's power consumption characteristics.

[0032] DRAM efficiency values ​​can be used to determine the effective DDR frequency, which can then be used by the DCVS system to balance various trade-offs between device performance and power consumption characteristics. The computing system can be configured to determine DRAM efficiency as the ratio of the actual bandwidth achieved by DRAM to the theoretical peak bandwidth that can be achieved. Mathematically, this DRAM efficiency ratio can be expressed as: DRAM efficiency = Achieved actual DRAM bandwidth / Achievable theoretical peak DRAM bandwidth. Due to several factors, for any given target configuration, this DRAM efficiency is almost always less than 100%. For example, if the system-on-a-chip (SoC) requires a DDR frequency of 1555MHz and DRAM is utilized at 100%, the computing system can determine that at 1... With a 16 DDR configuration, the DDR bandwidth will reach 6220 MB per second. However, this figure may be inaccurate because in real-world operating environments, the actual bandwidth often deviates from this theoretical maximum due to various dynamic variables and factors (such as operating temperature, DDR density, etc.).

[0033] Therefore, DRAM efficiency, used to determine the effective DDR frequency, is influenced by many factors and remains less than 100%. Examples of factors that can affect DRAM efficiency include DRAM losses, operational overhead, DDR density, DRAM refresh rate, DDR frequency, and temperature conditions. For example, an increase in DDR density can reduce DRAM efficiency across different frequencies. Temperature conditions can directly affect DRAM refresh rates, which can also significantly impact DRAM efficiency values. DRAM losses can be factors related to issues such as signal attenuation or electrical inefficiency within the memory module, which can significantly affect DRAM efficiency values. Operational overhead can be factors related to tasks performed by the memory that are not related to reading or writing data, such as opening and closing memory pages (which organize data) or performing refresh cycles to maintain the integrity of the stored information, which can also significantly affect DRAM efficiency values.

[0034] Conventional solutions fail to adequately account for the fact that DRAM efficiency is a dynamic value that fluctuates with changes in DDR frequency, density, refresh rate, temperature, DDR density, DRAM wear, and operating overhead. Instead, most conventional solutions simply assume that DRAM efficiency is static. This oversimplification can lead to inaccurate frequency settings and inefficient power utilization, as DRAM efficiency varies across different DDR frequencies, densities, and refresh rates.

[0035] Some conventional solutions determine the DDR frequency by aggregating two key metrics: aggregated bandwidth (AB) and instantaneous bandwidth (IB). These solutions determine the DDR frequency value by using aggregated voting to look up a lookup table that maps bandwidth requirements and static DRAM efficiency values ​​to DDR frequencies. However, unlike the static values ​​used for such lookup tables, DRAM efficiency is a dynamic value (e.g., due to increased operating overhead, etc.), and DRAM efficiency can decrease as the DDR frequency increases. For example, DRAM efficiency in high-density DDR memory devices may be lower at all or varying DDR frequencies compared to low-density memory devices. Furthermore, DRAM and DDR refresh rates can increase with temperature. This can be particularly important in applications with potentially high-temperature scenarios, such as in automotive SoCs. Additionally, higher DRAM refresh rates can (e.g., in configurations with 1Gb DDR density, etc.) lead to reduced DRAM efficiency. For these and other reasons, using static DRAM efficiency values ​​across a range of variables can have adverse effects, especially in terms of power utilization. If the identified DDR frequency is higher than actually needed, it can lead to undesirable power effects, thus reducing the system's energy efficiency.

[0036] Various implementations include computing devices configured to calculate and use DRAM efficiency values ​​to control DCVS operation within the device. The computing devices can be configured to take into account the dynamic nature of DRAM efficiency (and therefore variables such as DDR density and DRAM refresh rate) to achieve improved DCVS operation, DRAM utilization, DDR bandwidth management, etc.

[0037] In some implementations, the computing device may be equipped with components (referred to herein as "FADE components") that implement a framework for proper DRAM-efficient computing and efficient utilization of LLC.

[0038] In some implementations, the FADE component can be configured to implement a four-stage process that includes dynamic LLC allocation, DRAM efficiency calculations based on dynamic parameters, PASR, and other dynamic factors, and workload prioritization. The FADE component enables a multi-stage approach to dynamically allocate cache and adjust DDR frequencies, better utilize system resources, and / or otherwise improve the efficiency of various subsystems within the computing device.

[0039] In some implementations, the FADE component can be configured to determine DRAM efficiency values ​​based on a robust set of parameters. By utilizing a broad range of parameters, the FADE component can more accurately determine or characterize DRAM performance, which in turn allows for smarter system resource allocation and power management to save power, reduce latency, increase data throughput, and so on. Examples of parameters that can be considered by the FADE component include DRAM refresh rate, DDR density, cache miss rate, memory access latency, and power consumption.

[0040] In some implementations, the FADE component can be configured to implement and use a triggering mechanism to dynamically modify the DDR operating frequency and voltage angle. The DDR operating frequency can be the rate at which DDR memory operates (typically measured in megahertz (MHz)). The DDR operating frequency determines the speed at which data can be read from or written to memory, which can in turn affect overall system performance. The voltage angle indicates the specific voltage conditions under which a known semiconductor, such as DDR memory, operates normally. The voltage angle typically encompasses the voltage range for stable and efficient DDR operation. The triggering mechanism can be an automatic or semi-automatic task or process that initiates changes to DDR operating parameters such as frequency and voltage angle. In some implementations, the triggering mechanism can be event-driven and / or can be activated by several types of events or conditions, such as a sudden increase in computational tasks requiring significant memory usage, low battery power, high temperature readings from DRAM, QoS metrics for tasks with changing priorities, etc.

[0041] In some implementations, the FADE component can be configured to dynamically allocate cache to high-demand or "aggressive" clients to improve bandwidth utilization and thermal management (e.g., reduce DDR bandwidth (BW) requirements, lower device temperatures, etc.). By using the cache more efficiently, the FADE component can reduce the amount of data that needs to be transferred between the CPU and DDR memory, thereby reducing overall DDR bandwidth requirements. Furthermore, less frequent access to DDR memory reduces electrical operations, which in turn can lead to a reduction in device thermal output.

[0042] In some implementations, the FADE component may be configured to perform Phase 1 operations, which include: monitoring to detect changes in DDR BW requirements, interrupting the DDR subsystem (DDRSS) in response to detecting changes in DDR BW requirements to determine the availability of unused LLC lines, allocating available unused LLC lines to aggressive clients or clients with higher DDR BW requirements, and transmitting feedback to clients that have been allocated unused LLC lines to update their DDR BW requirements.

[0043] In some implementations, the FADE component may be configured to perform Phase 2 operations, which include: monitoring DRAM refresh rate changes, determining DRAM efficiency, DDR frequency, and other similar values ​​based on information stored in a pre-computed database containing parameters that facilitate the selection of an appropriate frequency (e.g., DDR density, refresh rate, BW, etc.), updating these values ​​to account for characteristics (such as PASR) that contribute to changes in DRAM efficiency, checking the active DRAM status to identify an appropriate DDR frequency, and updating the DDR frequency whenever there is a change in DRAM refresh rate or BW.

[0044] In some implementations, the FADE component may be configured to perform Phase 3 operations, which include: determining whether a higher DDR frequency is beneficial; in response to determining that a higher DDR frequency is beneficial, determining whether the DDR is already at its maximum frequency; invoking the Last Cache Controller (LLCC) to identify the least recently used cache path (path, channel, etc.) for reallocation (or “least frequently used”, “not most recently used”, or “most recently used”, etc.); flushing the dirty cache before allocating unused LLC lines to aggressive clients; and sending feedback to aggressive clients after LLC allocation to update their DDR BW requirements.

[0045] In some implementations, the FADE component can be configured to perform Phase 4 operations, which include maintaining a priority table for the subsystems using the Active Use Case Manager (AUG) component running on the Application Processor Subsystem (APSS). The priority table generated by the AUG component can be a dynamic entity (i.e., non-static), and therefore the priority of a subsystem can change dynamically if multiple use cases are running. The priority table may include information that takes latency requirements into account and categorizes subsystems as real-time clients and non-real-time clients, as well as foreground and background clients. The FADE component can also determine whether further optimization is beneficial and, in response to determining that further optimization is beneficial, restrict the operation of subsystems with low priority and high DDR BW requirements (or place them in low-power mode, etc.).

[0046] Various implementations can improve the performance and functionality of computing devices. As discussed above, DRAM efficiency is not static and is influenced by many factors, including DDR frequency, density, refresh rate, and temperature. Conventional solutions typically rely on fixed DRAM efficiency values, which may fail to account for real-world variations and / or result in inaccurate frequency settings and suboptimal power consumption in computing devices. Unlike conventional solutions, FADE components can be configured to dynamically adjust and optimize DRAM efficiency values ​​based on various system metrics and operating conditions, and use dynamically determined DRAM efficiency values ​​to set DDR frequencies and other parameters in the device (e.g., operating frequency, etc.), using methods such as DCVS. In some implementations, FADE components can be configured to use a four-stage process to improve various aspects of memory and cache allocation, bandwidth management, and operating frequency settings. In some implementations, FADE components can be configured to more accurately characterize DRAM performance and efficiency using any of a number of parameters, including DRAM refresh rate, DDR density, cache miss rate, memory access latency, and power consumption. DRAM performance characterization can be based on empirical curve fitting models and AI / ML methods. In some implementations, the FADE component may be configured to dynamically adjust DDR frequency and other operating parameters in response to the detection of specific conditions or events, such as a surge in compute tasks. In some implementations, the FADE component may be configured to improve system performance and reduce power consumption in the device by dynamically allocating resources based on real-time demand and metrics. In some implementations, the FADE component may be configured to integrate with other components such as the Last Cache Controller (LLCC) and the Active Use Case Manager (AUG) to provide finer-grained control over system resource usage and / or otherwise further improve the performance and battery consumption characteristics of the computing device. For all these reasons, various implementations improve the performance and functionality of the computing device. Additional improvements and enhancements to the performance and functionality of the computing device will be apparent from the disclosure below.

[0047] Various implementation schemes can be implemented on multiple single-processor and multi-processor computer systems, including system-on-a-chip (SOC) or system-in-package (SIP) systems. Figure 1 Example computing systems or SIP 100 architectures are illustrated for use in mobile computing devices that implement continuous voice monitoring artificial intelligence (AI) systems according to various implementation schemes.

[0048] refer to Figure 1 The illustrated example SIP 100 includes two SOCs 102 and 104, a clock 106, a voltage regulator 108, and a wireless transceiver 166. The first SOC 102 and the second SOC 104 can communicate via an interconnect bus 150. Various processors 110, 112, 114, 116, 118, 121, and 122 can be interconnected with each other and to one or more memory elements 120, system components and resources 124, and a thermal management unit 132 via an interconnect bus 126, which may include advanced interconnects such as high-performance network-on-chip (NOC). Similarly, processor 152 can be interconnected to a power management unit 154, a millimeter-wave transceiver 156, memory 158, and various additional processors 160 via an interconnect bus 164. These interconnect buses 126, 150, and 164 may include arrays of reconfigurable logic gates and / or implement bus architectures (e.g., CoreConnect, AMBA, etc.). Communication can be provided by advanced interconnect components such as NOC.

[0049] In various implementation schemes, any or all of the processors 110, 112, 114, 116, 121, and 122 in the system can operate as the main processor, central processing unit (CPU), microprocessor unit (MPU), arithmetic logic unit (ALU), etc. of the SoC. One or more of the coprocessors 118 can operate as the CPU.

[0050] In some implementations, the first SOC 102 may operate as a central processing unit (CPU) of a mobile computing device, which executes instructions by performing arithmetic, logic, control, and input / output (I / O) operations specified by instructions from software applications. In some implementations, the second SOC 104 may operate as a dedicated processing unit. For example, the second SOC 104 may operate as a dedicated 5G processing unit responsible for managing high-capacity, high-speed (e.g., 5Gbps) and / or ultra-high frequency short-wavelength (e.g., 28GHz millimeter-wave spectrum) communications.

[0051] The first SOC 102 may include a digital signal processor (DSP) 110, a modem processor 112, a graphics processor 114, an application processor 116, one or more coprocessors 118 (e.g., vector coprocessors, CPUCP, etc.) connected to one or more of these processors, memory 120, a deep processing unit (DPU) 121, an artificial intelligence processor 122, system components and resources 124, an interconnect bus 126, one or more temperature sensors 130, a thermal management unit 132, and a thermal power envelope (TPE) component 134. The second SOC 104 may include a 5G modem processor 152, a power management unit 154, an interconnect bus 164, multiple millimeter-wave transceivers 156, memory 158, and various additional processors 160, such as application processors, packet processors, etc.

[0052] Each processor 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160 may include one or more cores, and each processor / core may perform operations independently of other processors / cores. For example, the first SOC 102 may include a processor running a first type of operating system (e.g., FreeBSD, LINUX, OS X, etc.) and a processor running a second type of operating system (e.g., MICROSOFT WINDOWS 11). Additionally, any or all of processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160 may be included as part of a processor cluster architecture (e.g., synchronous processor cluster architecture, asynchronous or heterogeneous processor cluster architecture, etc.).

[0053] Processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, and 160, or any or all of them, can operate as the CPU of a mobile computing device. Additionally, processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, and 160, or any or all of them, can be included as one or more nodes in one or more CPU clusters. A CPU cluster can be a group of interconnected nodes (e.g., processing cores, processors, SOCs, SIPs, computing devices, etc.) configured to work in a coordinated manner to perform computational tasks. Each node can run its own operating system and contains its own CPU, memory, and storage devices. Tasks assigned to the CPU cluster can be divided into smaller tasks, which are distributed across the nodes for processing. Nodes can work together to complete a task, with each node handling a portion of the computation. The results of the computations from each node can be combined to produce a final result. CPU clusters are particularly useful for tasks that can be parallelized and executed concurrently. This allows CPU clusters to complete tasks much faster than a single high-performance computer. Furthermore, because CPU clusters consist of multiple nodes, they are generally more reliable and less prone to failure than a single high-performance component.

[0054] The first SOC 102 and the second SOC 104 may include various system components, resources, and custom circuitry for managing sensor data, analog-to-digital conversion, wireless data transmission, and performing other specialized operations such as decoding data packets and processing encoded audio and video signals for presentation in a web browser. For example, the system components and resources 124 of the first SOC 102 may include power amplifiers, voltage regulators, oscillators, phase-locked loops, peripheral bridges, data controllers, memory controllers, system controllers, access ports, timers, and other similar components for supporting processors and software clients running on computing devices. The system components and resources 124 may also include circuitry for interfacing with peripheral devices such as cameras, electronic displays, wireless communication devices, external memory chips, etc.

[0055] The first SOC 102 and / or the second SOC 104 may also include input / output modules (not illustrated) for communicating with external resources such as clock 106, voltage regulator 108, and wireless transceiver 166 (e.g., cellular wireless transceiver, Bluetooth transceiver, etc.). External resources (e.g., clock 106, voltage regulator 108, wireless transceiver 166) may be shared by two or more internal SOC processors / cores.

[0056] In addition to the example SIP 100 discussed above, various implementations can be implemented in a wide variety of computing systems, which may include a single processor, multiple processors, multi-core processors, or any combination thereof.

[0057] Figure 2 Example components, according to an implementation scheme, may be included in a system configured to achieve improved DRAM-efficient computing and more efficient utilization of LLC. References Figure 1 and Figure 2 System 200 (e.g., SIP 100, SOC 102, SOC 104, etc.) may include FADE component 201, which includes double data rate (DDR) bandwidth (BW) component 202, DDR refresh rate component 204, DDR density component 206, operating frequency component 208, DRAM efficiency value component 210, DDR frequency component 212, DCVS component 214, PASR component 216, and LLC component 218.

[0058] DDR BW component 202 can be configured to determine whether a new DDR BW request has been received for the DDR DRAM in computing system 200. DDR refresh rate component 204 can be configured to determine whether there is a change in the DDR refresh rate of the DDR DRAM. DDR density component 206 can be configured to determine whether there is a change in the DDR density of the DDR DRAM. Operating frequency component 208 can be configured to determine whether the DDR DRAM is operating at an upper operating frequency limit. The upper operating frequency limit can be the maximum operating frequency of the memory device, the maximum operating frequency of the computing device in which the memory device is installed, a threshold frequency beyond which applications, other components, or subsystems may experience performance degradation or increased errors, etc.

[0059] The DRAM efficiency value component 210 can be configured to dynamically determine and repeatedly update the DRAM efficiency value based on various factors such as DDR BW requirements, DRAM losses, operating overhead, DDR density, DRAM refresh rate, DDR frequency, temperature conditions, etc. The DDR frequency component 212 can be configured to dynamically determine and update the DDR frequency value based on the DRAM efficiency value.

[0060] DCVS component 214 can be configured to dynamically scale clock frequency, DDR frequency, and supply voltage based on DDR frequency values, DRAM efficiency values, workload requirements, etc., to balance the trade-off between performance and energy consumption. PASR component 216 can be configured to perform various energy-saving operations, such as selectively refreshing only the actively used portions of the memory array while allowing other unused segments to enter a low-power state. LLC component 218 can be configured to assign LLC lines to clients, determine the availability of unused LLC lines (or paths, channels, etc.), dynamically reassign unused LLC lines to clients with high DDR BW requirements (aggressive clients), and flush underutilized LLC lines, etc.

[0061] Figures 3A to 3E This is a process flowchart illustrating a method 300 for improving the performance and battery consumption characteristics of a computing system by improving the use of DRAM and LLC in the computing system, according to some implementation schemes. (Reference) Figures 1 to 3E Method 300 may be executed in a computing device by a processing system, which encompasses one or more processors (e.g., 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, etc.), components, or subsystems discussed herein. Components for performing the operations in method 300 may include the processing system, which includes one or more of processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, and other components described herein. Furthermore, software or firmware may be used to configure one or more processors of the processing system to perform some or all of the operations in method 300. To cover alternative configurations implemented in various embodiments, the hardware implementing any or all of the steps of method 300 is referred to herein as the "processing system".

[0062] Reference Figures 1 to 3A In determination block 302, the processing system may determine whether a new double data rate bandwidth (DDR BW) request has been received. In some embodiments, the processing system may determine whether a new DDR BW request has been received by monitoring system calls or application-level instructions that affect memory access patterns. The processing system may also examine its data flow and / or use observational metrics such as cache miss rates to estimate bandwidth requirements for various data storage and retrieval operations. For example, a higher-than-expected cache miss rate may indicate that adjusting the DDR BW may be beneficial. In some embodiments, the processing system may be configured to receive explicit commands indicating a new DDR BW request from other hardware components or software layers.

[0063] In some implementations, the processing system may be configured to receive and use event triggers (e.g., from a built-in monitoring system) to determine whether DDR BW usage has reached a predetermined threshold. In some implementations, the processing system may be configured to receive DDR BW request information directly from the computing device's resource manager. In some implementations, the processing system may be configured to periodically poll specific registers or memory locations to check for new requests. In some implementations, the processing system may be configured to use the length and latency of memory-related queues to determine whether a new DDR BW request has been received. In some implementations, the processing system may be configured to use adaptive feedback mechanisms to evaluate performance metrics and dynamically adjust system parameters, including changes in DDR BW requests.

[0064] In response to determining that no new DDR BW request has been received (i.e., determination box 302 = "No"), the processing system may determine in determination box 304 whether there is any change in the DDR refresh rate or DDR density. For example, the processing system may query specific hardware registers that store information related to the DDR refresh rate and density, monitor system events or alarms generated by the memory controller or other components of the hardware subsystem to detect changes in memory characteristics such as refresh rate and density, receive notifications from a dedicated resource manager indicating changes in DDR settings, read information stored in the operating system log or hardware log, issue commands to request real-time status updates from the memory controller or DDR module, and so on.

[0065] In response to determining that a new DDR BW request has been received (i.e., determining box 302 = "Yes"), the processing system may perform the Phase 1 operation in box 310. See below for reference. Figure 3B The Phase 1 operation in box 310 is discussed in detail.

[0066] In response to determining that there is no change in the DDR refresh rate or DDR density (i.e., determination box 304 = "No"), the processing system may determine in determination box 306 whether the DDR memory is operating at its maximum operating frequency (or its maximum operating frequency, frequency upper limit, etc.). For example, the processing system may read specific hardware registers containing information about the current operating frequency of the DDR memory, read event logs or notifications generated by the memory controller or other system components, observe system-level metrics and performance indicators, and / or perform other similar operations to determine whether the DDR memory is operating at its maximum operating frequency. Typically, memory access latency and throughput are negatively correlated with the memory's operating frequency. Therefore, in some embodiments, the processing system may be configured to determine whether the DDR memory is operating at its frequency upper limit in response to determining that latency and throughput metrics are at levels consistent with maximum performance.

[0067] In response to determining that a change in DDR refresh rate or DDR density exists (i.e., determination box 304 = "Yes"), the processing system may perform the stage 2 operation in box 330. See below for reference. Figure 3C The Phase 2 operation in box 330 will be discussed in detail.

[0068] In response to determining that the DDR memory is not operating at its maximum operating frequency (i.e., determining box 306 = "No"), the processing system may perform monitoring to determine whether a new DDR BW request has been received in box 302.

[0069] In response to determining that the DDR memory is operating at its maximum operating frequency (i.e., determining box 306 = "Yes"), the processing system may perform stage 3 operation in box 350. See below for reference. Figure 3D The Phase 3 operation in box 350 will be discussed in detail.

[0070] In determination box 308, the processing system may determine whether further adjustments to the DRAM efficiency value are beneficial. In some embodiments, the processing system may consider various trade-offs between performance and power consumption associated with achieving the current objective based on current operating conditions. In some embodiments, the processing system may monitor system performance metrics (e.g., memory latency, throughput, cache miss rate, etc.) and determine whether further adjustments to the DRAM efficiency value are beneficial based on whether the performance metrics deviate from expected or optimal values.

[0071] In response to determining that further adjustments to the DRAM efficiency value are not beneficial (i.e., determining box 308 = "No"), the processing system may monitor to determine whether a new DDR BW request has been received in box 302.

[0072] In response to the determination that further adjustments to the DRAM efficiency value are beneficial (i.e., determining that box 308 = "Yes"), the processing system may perform the stage 4 operation in box 370 and monitor to determine whether a new DDR BW request has been received in box 302. See below for reference. Figure 3E The Phase 4 operation in box 370 is discussed in detail.

[0073] Figure 3B The example shown illustrates operations that can be performed in stage 1. (See also...) Figures 1 to 3B In box 312, the processing system can interrupt the DDR subsystem (DDRSS) to determine whether any line in the LLC is available.

[0074] In determination block 314, the processing system may determine whether unused LLC lines are available. In some embodiments, the processing system may issue an interrupt signal that temporarily halts or modifies the standard operation of the DDRSS to perform specific checks on the LLC. The interrupt may instruct the memory controller to query or investigate the LLC to determine whether the lines are currently available. In some embodiments, the processing system may use a special control register or system command that triggers a status check on the LLC. After such a command is issued, the processing system may read back the result from a designated register or memory location in the DDRSS or LLC where availability information is written. In some embodiments, the processing system may invoke APIs or system calls associated with operating system-level functions or dedicated resource management software in the computing system to determine LLC line availability.

[0075] In response to determining that there are no available unused LLC lines (i.e., determination box 314 = "No"), the processing system may determine in determination box 304 whether there are any changes in DDR refresh rate or DDR density.

[0076] In response to determining that there are available unused LLC lines (i.e., determining box 314 = "Yes"), in box 316, the processing system may dynamically assign the unused LLC lines to DDR BW aggressive clients.

[0077] In block 318, the processing system may send feedback to the client with the latest LLC allocation to update its BW requirements. The processing system may then perform the operations in determination block 304 of method 300 as described.

[0078] Figure 3C The example shown illustrates operations that can be performed in stage 2. (See reference) Figures 1 to 3C In box 332, the processing system can generate and store a DRAM efficiency calculation database, where efficiency is mapped as a function of DDR BW, DDR density, and DRAM refresh rate.

[0079] In block 334, the processing system can determine DRAM efficiency values ​​based on information stored in the generated database.

[0080] In block 336, the processing system may determine the DDR frequency value based on the DRAM efficiency value. The processing system may then perform the operations in determination block 306 of method 300 as described.

[0081] Figure 3D The example shown illustrates operations that can be performed in stage 3. (See reference) Figures 1 to 3D In determination box 352, the processing system can determine whether any client in the client is not effectively using the assigned LLC path.

[0082] In response to determining that all clients are effectively using their assigned LLC paths (i.e., determination box 352 = "No"), the processing system may determine in determination box 308 whether further adjustments to the DRAM efficiency value would be beneficial.

[0083] In response to determining that the client is not effectively using its assigned LLC path (i.e., determining box 352 = "Yes"), in box 354, the processing system may flush the underutilized LLC line.

[0084] In box 356, the processing system can assign the newly flashed LLC path to aggressive clients with high DDR BW requirements.

[0085] In block 358, the processing system may send feedback to the client with the latest LLC allocation to update its BW requirements. The processing system may then perform the operations in determination block 308 of method 300 as described.

[0086] Figure 3E The example shown illustrates operations that can be performed in stage 4. (See references.) Figures 1 to 3E In box 372, the processing system may use the Active Use Case Manager (AUG) component running on the Application Processor Subsystem (APSS) to update and / or maintain a dynamic priority table for the subsystem, which includes information that takes into account latency requirements and classifies the subsystem into real-time clients and non-real-time clients, as well as foreground clients and background clients.

[0087] The priority table can be dynamic, allowing the priority of subsystems in the priority table to change dynamically if multiple use cases are running. In box 374, the processing system can determine which subsystems can be placed in low-power mode (LPM) based on the generated priority table of subsystems.

[0088] In box 376, the processing system can identify low-priority subsystems that include high DDR BW requirements.

[0089] In block 378, the processing system can cause the identified subsystem to enter its low-power mode to reduce DDR BW requirements. The processing system can repeat the operation of method 300 continuously, periodically, or intermittently by re-executing the operation in determination block 302 as described.

[0090] Therefore, as described in detail above, in various implementations, the FADE component can be configured to dynamically allocate LLC to high BW clients, determine DDR bandwidth based on refresh rate and effective DRAM size, dynamically reallocate underutilized lines to high BW clients if DDR is at maximum frequency, and / or assign DDR BW to clients based on application priority (e.g., dynamic priority table, etc.).

[0091] Various implementation plans (including but not limited to the above references) Figures 1 to 3E The described implementation scheme can be used in a wide variety of wireless devices and computing systems (including laptop computers 400, examples of which are shown in...). Figure 4 Implemented in the example (see below). Reference Figures 1 to 4 The laptop computer 400 may include a processor 402 coupled to volatile memory 404 and a disk drive 406 containing mass non-volatile memory (such as flash memory). The laptop computer 400 may include a touchpad touch surface 408 serving as a pointing device for the computer and thus capable of receiving drag, scroll, and tap gestures. Additionally, the laptop computer 400 may have one or more antennas 410 for transmitting and receiving electromagnetic radiation, connectable to a wireless data link, and / or a cellular transceiver 412 coupled to the processor 402. The computer 400 may also include a BT transceiver 414, a compact disc (CD) drive 416, a keyboard 418, and a display 420, all coupled to the processor 402. Other configurations of the computing device may include a computer mouse or trackball, as is well known (e.g., via a Universal Serial Bus (USB) input), coupled to the processor, which may also be used in various implementations.

[0092] Figure 5 This is a component block diagram of a computing device 500 suitable for use with various implementation schemes. (Reference) Figures 1 to 5 Various implementation schemes can be implemented on a variety of computing devices (examples of which are available in 500). Figure 5 This is exemplified in the form of a smartphone. The computing device 500 may include a first SOC 102 coupled to the second SOC 104. The first SOC 102 and the second SOC 104 may be coupled to an internal memory 516, a display 512, and a speaker 514. The first SOC 102 and the second SOC 104 may also be coupled to at least one subscriber identity module (SIM) 540 and / or a SIM interface, which may store information supporting a first 5G NR subscription and a second 5G NR subscription, supporting services on a 5G non-standalone (NSA) network.

[0093] The computing device 500 may include an antenna 504 for transmitting and receiving electromagnetic radiation, which may be connected to a wireless transceiver 166 coupled to one or more processors in the first SOC 102 and / or the second SOC 104. The computing device 500 may also include a menu selection button or rocker switch 520 for receiving user input.

[0094] The computing device 500 also includes a sound codec (CODEC) circuit 510 that digitizes sound received from a microphone into data packets suitable for wireless transmission and decodes the received sound data packets to generate an analog signal for use with a speaker to produce sound. Furthermore, one or more of the processor in the first circuit 102 and the second circuit 104, the wireless transceiver 166, and the CODEC 510 may include a digital signal processor (DSP) circuit (not shown separately).

[0095] Some implementation schemes can be implemented on any type of computing device among a variety of commercially available computing devices (such as...) Figure 6 Implemented on the server computing device 600 illustrated herein. Such a server device 600 may include a processor 601 coupled to volatile memory 602 and mass non-volatile memory (such as a disk drive 603). The server device 600 may also include a floppy disk drive, USB, etc. coupled to the processor 601. The server device 600 may also include a network access port 606 coupled to the processor 601 to establish a data connection with network connection circuitry 604 and a communication network 607 (e.g., an Internet Protocol (IP) network) coupled to other communication system network elements.

[0096] The processor or processing unit discussed in this application can be any programmable microprocessor, microcomputer, or one or more multiprocessor chips that can be configured via software instructions (applications) to perform a variety of functions, including those described in the various embodiments. In some computing devices, multiple processors may be provided, such as one processor within a first circuit dedicated to wireless communication functions and another processor within a second circuit dedicated to running other applications. Software applications may be stored in memory and then accessed and loaded into the processor. The processor may include internal memory sufficient to store application software instructions.

[0097] Specific implementation embodiments are described in the following paragraphs. While some of the specific implementation embodiments described below are in the form of exemplary methods, further exemplary implementations may include: the exemplary methods discussed in the following paragraphs may be implemented by a computing device including a processor configured (e.g., configured using processor-executable instructions) to perform the operations of the methods of the following embodiments; the exemplary methods discussed in the following paragraphs implemented by a computing device including components for performing the functions of the methods of the following embodiments; and the exemplary methods discussed in the following paragraphs may be implemented as a non-transitory processor-readable storage medium storing processor-executable instructions configured to cause the processor of the computing device to perform the operations of the methods of the following embodiments.

[0098] Example 1: A method for improving memory bandwidth in a computing device, the method comprising: determining whether a new DDR bandwidth (BW) request has been received for a Double Data Rate (DDR) Dynamic Random Access Memory (DRAM) in the computing device; determining whether there is a change in the DDR refresh rate or DDR density of the DDR DRAM; determining whether the DDR DRAM is operating at an upper limit operating frequency; and determining a DRAM efficiency value based on at least one or more of the following: whether the new DDR BW request has been received, whether there is a change in the DDR refresh rate or the DDR density, or whether the DDR DRAM is operating at the upper limit operating frequency.

[0099] Example 2: According to the method described in Example 1, the method further includes: performing a dynamic clock and voltage scaling (DCVS) operation using a determined DRAM efficiency value, the dynamic clock and voltage scaling (DCVS) operation scaling the clock frequency, DDR frequency, or supply voltage in the computing device.

[0100] Example 3: The method according to any one of Examples 1 or 2, the method further includes: determining the availability of unused last-level cache (LLC) lines in response to determining that a new DDR BW request has been received; dynamically assigning the unused LLC lines to a high DDR BW demand client; and transmitting feedback to the high DDR BW demand client to update the BW request.

[0101] Example 4: The method according to any one of Examples 1 to 3, wherein determining whether there is a change in the DDR refresh rate or the DDR density of the DDR DRAM includes determining whether there is a change in the DDR refresh rate or the DDR density of the DDR DRAM in response to determining that no new DDR BW request has been received.

[0102] Example 5: The method according to any one of Examples 1 to 4, the method further includes: generating a data repository that maps DRAM efficiency to a function of DDR BW, DDR density and DRAM refresh rate; determining the DRAM efficiency value based on information included in the generated data repository; and determining the DDR frequency value based on the determined DRAM efficiency value.

[0103] Example 6: The method according to any one of Examples 1 to 5, wherein determining whether the DDR memory is operating at the upper limit operating frequency is performed in response to a change in the DDR refresh rate or the DDR density in which the absence of the DDR memory is determined.

[0104] Example 7: The method according to any one of Examples 1 to 6, the method further includes: in response to determining that a client assigned a Last Cache (LLC) line is not effectively using the assigned LLC line to flush the underutilized LLC line; assigning the newly flushed LLC line to a client with high DDR BW demand; and sending feedback to the client with high DDR BW demand to update the BW requirement.

[0105] Example 8: According to the method of Example 7, the method further includes: determining whether further adjustments to the DRAM efficiency value or the assigned LLC circuitry will better balance the trade-off between performance and power consumption in the computing device.

[0106] Example 9: According to the method of Example 8, the method further includes: in response to determining that further adjustments to the DRAM efficiency value or the assigned LLC line will better balance the trade-off between performance and power consumption in the computing device, determining the subsystems of the computing device that can be placed in low power mode (LPM) based on information stored in a priority table, traversing the determined subsystems to identify low-priority subsystems including high DDR BW requirements, and bringing the identified low-priority subsystems into the LPM.

[0107] As used in this application, the terms "component," "module," "system," etc., are intended to include computer-related entities such as, but not limited to, hardware, firmware, combinations of hardware and software, software, or software being executed, configured to perform specific operations or functions. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. By way of illustration, both an application running on a computing device and the computing device itself can be referred to as a component. One or more components may reside within a process and / or a thread of execution, and components may reside on a processor or core and / or be distributed across two or more processors or cores. Furthermore, these components may execute on various non-transitory computer-readable media on which various instructions and / or data structures are stored. Components may communicate via local and / or remote processes, function or procedure calls, electronic signals, data packets, memory read / write, and other known network, computer, processor, and / or process-related communication methods.

[0108] A variety of different memory types and memory technologies are available or conceivable in the future, and any or all of these different memory types and memory technologies can be included and used in systems and computing devices implementing various implementation schemes. Such memory technologies / types may include non-volatile random access memory (NVRAM), such as magnetoresistive RAM (M-RAM), resistive random access memory (ReRAM or RRAM), phase-change random access memory (PC-RAM, PRAM, or PCM), ferroelectric RAM (F-RAM), spin-transfer torque magnetoresistive random access memory (STT-MRAM), and 3D-XPOINT memory. Such memory technologies / types may also include non-volatile or read-only memory (ROM) technologies, such as programmable read-only memory (PROM), field-programmable read-only memory (FPROM), and one-time programmable non-volatile memory (OTP NVM). Such memory technologies / types may also include volatile random access memory (RAM) technologies, such as dynamic random access memory (DRAM), double data rate (DDR) synchronous dynamic random access memory (DDR SDRAM), static random access memory (SRAM), and pseudo static random access memory (PSRAM). Systems and computing devices implementing various embodiments may also include or use electronic (solid-state) non-volatile computer storage media, such as flash memory. Each of the memory technologies mentioned above includes, for example, elements suitable for storing instructions, programs, control signals, and / or data for use in computing devices, system-on-a-chip (SOC), or other electronic components. Any references to terms and / or technical details relating to individual memory types, interfaces, standards, or memory technologies are for illustrative purposes only and are not intended to limit the scope of the claims to a particular memory system or technology, unless expressly stated in the language of the claims.

[0109] The various embodiments illustrated and described are provided merely as examples illustrating the various features of the claims. However, the features shown and described with respect to any given embodiment are not necessarily limited to the associated embodiment and may be used or combined with other embodiments shown and described. Furthermore, the claims are not intended to be limited to any one of the exemplary embodiments. For example, one or more operations in the operation of the method may substitute for or combine with one or more operations of the method.

[0110] The foregoing method descriptions and process flowcharts are provided as illustrative examples only and are not intended to require or imply that the operations of the various embodiments must be performed in the given order. As those skilled in the art will appreciate, the operations in the foregoing embodiments can be performed in any order. Words such as “afterward,” “then,” “next,” etc., are not intended to restrict the order of operations; these words are only used to guide the reader through the description of the method. Furthermore, any reference to singular claim elements (e.g., references using the articles “a,” “an,” or “the”) should not be construed as limiting that element to the singular.

[0111] The various exemplary logic blocks, modules, circuits, and algorithmic operations described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and operations have been generally described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. While those skilled in the art may implement the described functionality in different ways for each specific application, such implementation decisions should not be construed as departing from the scope of the claims.

[0112] Hardware for implementing the various exemplary logic units, logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein may be implemented or executed using a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (TCUASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic unit, discrete hardware component, or any combination thereof designed to perform the functions described herein. While the general-purpose processor may be a microprocessor, in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. Alternatively, some operations or methods may be performed by circuitry specific to a given function.

[0113] In one or more embodiments, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, such functionality may be stored as one or more instructions or code on a non-transitory computer-readable medium or a non-transitory processor-readable medium. The operation of the methods or algorithms disclosed herein may be embodied in a processor-executable software module that may reside on a non-transitory computer-readable or processor-readable storage medium. A non-transitory computer-readable or processor-readable storage medium may be any storage medium accessible by a computer or processor. By way of example and not limitation, such non-transitory computer-readable or processor-readable media may include RAM, ROM, EEPROM, flash memory, CD-ROM or other optical disc storage, disk storage or other magnetic storage devices, or any other medium that can be used to store object program code in the form of instructions or data structures and is accessible by a computer. As used herein, disks and optical discs include compact optical discs (CDs), laser discs, optical discs, digital versatile optical discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of the above are also included within the scope of non-transitory computer-readable and processor-readable media. Additionally, the operation of a method or algorithm may reside as a single line of code and / or instruction, or any combination or set of code and / or instructions, on a non-transitory processor-readable medium and / or computer-readable medium that may be incorporated into a computer program product.

[0114] The above description of the disclosed embodiments is provided to enable any person skilled in the art to implement or use the claims. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments without departing from the scope of the claims. Therefore, this disclosure is not intended to be limited to the embodiments shown herein, but should be granted the broadest scope consistent with the following claims and the principles and novel features disclosed herein.

Claims

1. A computing device, the computing device comprising: Double Data Rate (DDR) Dynamic Random Access Memory (DRAM); and A processor, coupled to the DDR DRAM and configured to: Determine whether a new DDR bandwidth (BW) requirement has been received for the DDR DRAM; Determine whether there is a change in the DDR refresh rate or DDR density of the DDR DRAM; Determine whether the DDR DRAM is operating at the upper limit operating frequency; and The DRAM efficiency value is determined based on at least one or more of the following: whether the new DDR BW requirement has been received, whether there is a change in the DDR refresh rate or the DDR density, or whether the DDR DRAM is operating at the upper limit operating frequency.

2. The computing device of claim 1, wherein the processor is further configured to perform a dynamic clock and voltage scaling (DCVS) operation using a determined DRAM efficiency value, the dynamic clock and voltage scaling (DCVS) operation scaling the clock frequency, DDR frequency, or supply voltage in the computing device.

3. The computing device of claim 1, wherein the processor is further configured to: In response to the determination that a new DDR BW request has been received, the availability of unused last-level cache (LLC) lines is determined; Dynamically assign the unused LLC lines to clients with high DDR BW requirements; and Feedback is sent to the client with high DDR BW requirements to update the BW requirements.

4. The computing device of claim 1, wherein the processor is configured to determine whether there is a change in the DDR refresh rate or the DDR density of the DDR DRAM by determining, in response to determining that no new DDR BW request has been received, whether there is a change in the DDR refresh rate or the DDR density of the DDR DRAM.

5. The computing device of claim 1, wherein the processor is further configured to: Generate a data repository that maps DRAM efficiency to functions of DDR BW, DDR density, and DRAM refresh rate. The DRAM efficiency value is determined based on information included in the generated data repository; and The DDR frequency value is determined based on the established DRAM efficiency value.

6. The computing device of claim 1, wherein the processor is configured to determine whether the DDR memory is operating at the upper limit operating frequency in response to a change in the DDR refresh rate or the DDR density in determining that the DDR memory is absent.

7. The computing device of claim 1, wherein the processor is further configured to: In response to the determination that a client assigned a Last Cache (LLC) line is not effectively using the assigned LLC line to flush underutilized LLC lines; The newly flashed LLC lines are assigned to clients with high DDR BW requirements; as well as Feedback is sent to the client with high DDR BW requirements to update the BW requirements.

8. The computing device of claim 7, wherein the processor is further configured to determine whether further adjustments to the DRAM efficiency value or the assigned LLC circuitry will better balance the trade-off between performance and power consumption in the computing device.

9. The computing device of claim 8, wherein the processor is further configured to perform operations including the following in response to determining that further adjustments to the DRAM efficiency value or the assigned LLC circuitry will better balance the trade-off between performance and power consumption in the computing device: The subsystems of the computing device that can be placed in low-power mode (LPM) are determined based on information stored in a priority table; Traverse the identified subsystems to identify low-priority subsystems that include high DDR BW requirements; as well as The identified low-priority subsystem is then brought into the LPM.

10. A method for improving memory bandwidth in a computing device, the method comprising: Determine whether a new DDR bandwidth (BW) request has been received for the Double Data Rate (DDR) Dynamic Random Access Memory (DRAM) in the computing device; Determine whether there is a change in the DDR refresh rate or DDR density of the DDR DRAM; Determine whether the DDR DRAM is operating at the upper limit operating frequency; and The DRAM efficiency value is determined based on at least one or more of the following: whether the new DDR BW requirement has been received, whether there is a change in the DDR refresh rate or the DDR density, or whether the DDR DRAM is operating at the upper limit operating frequency.

11. The method according to claim 10, further comprising: The determined DRAM efficiency value is used to perform a dynamic clock and voltage scaling (DCVS) operation, which scales the clock frequency, DDR frequency, or supply voltage in the computing device.

12. The method according to claim 10, further comprising: In response to the determination that a new DDR BW request has been received, the availability of unused last-level cache (LLC) lines is determined; The unused LLC lines are dynamically assigned to clients with high DDR BW requirements; as well as Feedback is sent to the client with high DDR BW requirements to update the BW requirements.

13. The method of claim 10, wherein determining whether there is a change in the DDR refresh rate or the DDR density of the DDR DRAM includes determining whether there is a change in the DDR refresh rate or the DDR density of the DDR DRAM in response to determining that no new DDR BW request has been received.

14. The method according to claim 10, further comprising: Generate a data repository that maps DRAM efficiency to functions of DDR BW, DDR density, and DRAM refresh rate. The DRAM efficiency value is determined based on information included in the generated data repository; as well as The DDR frequency value is determined based on the established DRAM efficiency value.

15. The method of claim 10, wherein determining whether the DDR memory is operating at the upper limit operating frequency is performed in response to a change in the DDR refresh rate or the DDR density in which the absence of the DDR memory is determined.

16. The method according to claim 10, further comprising: In response to the determination that a client assigned a Last Cache (LLC) line is not effectively using the assigned LLC line to flush underutilized LLC lines; The newly flashed LLC lines are assigned to clients with high DDR BW requirements; as well as Feedback is sent to the client with high DDR BW requirements to update the BW requirements.

17. The method according to claim 16, further comprising: Determine whether further adjustments to the DRAM efficiency value or the assigned LLC circuitry will better balance the trade-off between performance and power consumption in the computing device.

18. The method according to claim 17, further comprising: In response to the determination that further adjustments to the DRAM efficiency value or the assigned LLC circuitry will better balance the trade-off between performance and power consumption in the computing device: The subsystems of the computing device that can be placed in low-power mode (LPM) are determined based on information stored in a priority table; Traverse the identified subsystems to identify low-priority subsystems that include high DDR BW requirements; as well as The identified low-priority subsystem is then brought into the LPM.

19. A non-transitory computer-readable storage medium having stored thereon processor-executable software instructions configured to cause a processor in a computing device to perform operations for improving memory bandwidth in the computing device, the operations including: Determine whether a new DDR bandwidth (BW) request has been received for the Double Data Rate (DDR) Dynamic Random Access Memory (DRAM) in the computing device; Determine whether there is a change in the DDR refresh rate or DDR density of the DDR DRAM; Determine whether the DDR DRAM is operating at the upper limit operating frequency; and The DRAM efficiency value is determined based on at least one or more of the following: whether the new DDR BW requirement has been received, whether there is a change in the DDR refresh rate or the DDR density, or whether the DDR DRAM is operating at the upper limit operating frequency.

20. The non-transitory computer-readable storage medium of claim 19, wherein the stored processor-executable software instructions are configured to cause the processor to perform an operation, said operation further comprising: The determined DRAM efficiency value is used to perform a dynamic clock and voltage scaling (DCVS) operation, which scales the clock frequency, DDR frequency, or supply voltage in the computing device.

21. The non-transitory computer-readable storage medium of claim 19, wherein the stored processor-executable software instructions are configured to cause the processor to perform an operation, said operation further comprising: In response to the determination that a new DDR BW request has been received, the availability of unused last-level cache (LLC) lines is determined; The unused LLC lines are dynamically assigned to clients with high DDR BW requirements; as well as Feedback is sent to the client with high DDR BW requirements to update the BW requirements.

22. The non-transitory computer-readable storage medium of claim 19, wherein the stored processor-executable software instructions are configured to cause the processor to perform operations such that determining whether there is a change in the DDR refresh rate or the DDR density of the DDR DRAM includes determining whether there is a change in the DDR refresh rate or the DDR density of the DDR DRAM in response to determining that no new DDR BW request has been received.

23. The non-transitory computer-readable storage medium of claim 19, wherein the stored processor-executable software instructions are configured to cause the processor to perform an operation, said operation further comprising: Generate a data repository that maps DRAM efficiency to functions of DDR BW, DDR density, and DRAM refresh rate. The DRAM efficiency value is determined based on information included in the generated data repository; as well as The DDR frequency value is determined based on the established DRAM efficiency value.

24. The non-transitory computer-readable storage medium of claim 19, wherein the stored processor-executable software instructions are configured to cause the processor to perform operations such that determining whether the DDR memory is operating at the upper limit operating frequency is performed in response to a change in the DDR refresh rate or the DDR density in which the absence of the DDR memory is determined.

25. The non-transitory computer-readable storage medium of claim 19, wherein the stored processor-executable software instructions are configured to cause the processor to perform an operation, said operation further comprising: In response to the determination that a client assigned a Last Cache (LLC) line is not effectively using the assigned LLC line to flush underutilized LLC lines; The newly flashed LLC lines are assigned to clients with high DDR BW requirements; as well as Feedback is sent to the client with high DDR BW requirements to update the BW requirements.

26. The non-transitory computer-readable storage medium of claim 25, wherein the stored processor-executable software instructions are configured to cause the processor to perform an operation, said operation further comprising: Determine whether further adjustments to the DRAM efficiency value or the assigned LLC circuitry will better balance the trade-off between performance and power consumption in the computing device.

27. The non-transitory computer-readable storage medium of claim 26, wherein the stored processor-executable software instructions are configured to cause the processor to perform an operation, said operation further comprising: In response to the determination that further adjustments to the DRAM efficiency value or the assigned LLC circuitry will better balance the trade-off between performance and power consumption in the computing device: The subsystems of the computing device that can be placed in low-power mode (LPM) are determined based on information stored in a priority table; Traverse the identified subsystems to identify low-priority subsystems that include high DDR BW requirements; as well as The identified low-priority subsystem is then brought into the LPM.

28. A computing device, the computing device comprising: A component used to determine whether a new DDR bandwidth (BW) request has been received for the double data rate (DDR) dynamic random access memory (DRAM) in the computing device; A component used to determine whether there is a change in the DDR refresh rate or DDR density of the DDR DRAM; A component used to determine whether the DDR DRAM is operating at the upper limit operating frequency; and Components for determining DRAM efficiency values ​​based on at least one or more of the following: whether the new DDR BW requirement has been received, whether there is a change in the DDR refresh rate or the DDR density, or whether the DDR DRAM is operating at the upper limit operating frequency.

29. The computing device of claim 28, further comprising: A component used to determine the availability of unused last-level cache (LLC) lines in response to the receipt of a new DDR BW request; A component for dynamically assigning the unused LLC lines to clients with high DDR BW requirements; and Components used to send feedback to the high DDR BW demand client to update the BW requirements.

30. The computing device of claim 28, further comprising: A component for responding to the determination that a client assigned a Last Cache (LLC) line is not effectively using the assigned LLC line to flush underutilized LLC lines. Components used to assign the newly flashed LLC lines to clients with high DDR BW requirements; Components used to transmit feedback to the high DDR BW demand client to update the BW requirements; A component used to determine whether further adjustments to the DRAM efficiency value or the assigned LLC circuitry will better balance the trade-off between performance and power consumption in the computing device; Components used to determine, based on information stored in a priority table, which subsystems of the computing device can be placed in low-power mode (LPM) in response to the determination that further adjustments to the DRAM efficiency value or the assigned LLC circuitry will better balance the trade-off between performance and power consumption in the computing device. Used to traverse the identified subsystems to identify components that include low-priority subsystems with high DDR BW requirements; and Components used to bring the identified low-priority subsystem into the LPM.

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