Abstract component-based patch machine service logic control method and system, medium

Abstract

The application discloses a patch machine business logic control method and system based on abstract components, medium, and relates to the technical field of industrial automation control.The system comprises a command cache queue module configured to receive and cache commands from the upper layer; a command parameter verification module configured to verify the legality of the command parameters cached by the command cache queue module in real time; a user command monitoring module configured to distribute the verified commands to different units according to the command type; and a device control flow monitoring module configured to monitor the command execution state of the hardware layer and report a timeout event to the user command monitoring module and coordinate the system to enter a safe state if no command is received within a specified time.The scheme builds a unified business logic control hub and an abstract component control model, completely separates the component collaborative control logic from the specific hardware implementation, and realizes the centralization, closed loop and uniqueness of command execution.

Description

Technical Field

[0001] This invention relates to the field of industrial automation control technology, specifically to a method, system, and medium for controlling the business logic of a chip mounter based on abstract components. Background Technology

[0002] The traditional chip mounter main control software architecture has several systemic defects, specifically in the following aspects: Decentralized component control: In traditional architectures, control of the same physical component is distributed among multiple functional modules, lacking a unified and unique control entry point. For example, the placement head component may be directly invoked by the production module, manual operation module, and calibration module simultaneously. When these modules run in parallel, instruction conflicts can easily occur, leading to production accidents.

[0003] Open-loop control mechanism: After control commands are issued, there is a lack of effective status feedback and verification mechanisms, making it impossible to form a closed loop for command execution. The upper-level software is only responsible for triggering actions but cannot confirm whether the actions are actually executed or whether the execution results meet expectations, thus causing uncertainty in system behavior and affecting production accuracy and process stability.

[0004] Significant synchronization overhead: To avoid control conflicts between multiple modules on the same component, traditional architectures rely on complex external synchronization mechanisms for resource coordination. These synchronization measures not only increase the complexity of the code logic but also introduce significant system performance overhead, reducing the operating efficiency of the device.

[0005] State unknowable: Due to the decentralized control logic, the system struggles to obtain the real-time and accurate operating state of a physical component (e.g., whether it is performing an action or has been locked by other modules). Upper-level process control often lacks support from real hardware feedback, resulting in poor process control accuracy and low operational stability.

[0006] Maintenance difficulties and poor scalability: Component control logic is scattered across various system modules. Modifying or debugging a single component often requires adjusting the code of multiple functional modules in tandem, significantly increasing maintenance difficulty and the probability of errors. Furthermore, when adding new hardware or upgrading existing equipment, extensive refactoring of upper-layer business code is often necessary, resulting in high adaptation costs.

[0007] The root cause of the above problems lies in the lack of convergence of control over components and the lack of closed-loop instruction flow in traditional architectures. Summary of the Invention

[0008] To address the aforementioned technical shortcomings, the present invention aims to provide a business logic control method, system, and medium for a chip mounter based on abstract components. By centrally managing the control logic of each component through a unified and abstract business logic layer, the invention overcomes the problems of unconverged component control and unclosed instruction flow, thereby eliminating the hidden dangers of multi-source control conflicts from the design level.

[0009] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: The first aspect provides a chip mounter business logic control system based on abstract components, comprising: The command caching queue module is configured to receive and cache commands sent from the upper layer. The command parameter verification module is configured to verify the validity of command parameters cached by the command cache queue module in real time. If the parameter is invalid, the command is intercepted and an error is returned to the upper layer. The user command monitoring module is configured to distribute verified commands to different units based on command type, including component control units, process control units, and combined process control units. The component control units are used to centrally control each abstract component, with each abstract component instance corresponding to a physical component. The process control units are used to combine multiple abstract component instances into standardized processes. When a standardized process starts, it automatically initiates resource locking requests to all involved abstract components, and automatically releases all locked resources when the process ends normally or terminates abnormally. The combined process control units are used to combine multiple standardized processes into an ordered sequence. Equipment control process monitoring module: It is configured to monitor the command execution status of the hardware layer. If no command execution status is received within a specified time, it reports a timeout event to the user command monitoring module and coordinates the system to enter a safe state.

[0010] Preferably, the interaction between the command cache queue module and the upper layer is implemented through inter-process communication based on shared memory using the Boost library.

[0011] Preferably, after receiving a command, the command cache queue module temporarily stores the command in a thread-safe priority blocking queue, and the queue adopts a dual sorting method of priority > timestamp.

[0012] Preferably, the user command monitoring module is configured to distribute commands to different units according to command type, track command execution progress, and automatically generate information to feed back to the upper layer if execution times out or fails.

[0013] Preferably, the user command monitoring module is configured to distribute commands to different units according to command type, track command execution progress, and automatically generate information feedback to the upper layer if execution times out or fails. Specifically, after distributing commands to different units, a unique command ID is assigned to each command. The command execution status is continuously monitored through an internally integrated independent monitoring timer. If no feedback is received from the device control process monitoring module within a preset timeout threshold, a timeout event is actively triggered and the combined process control unit is notified to forcibly interrupt the current task. At the same time, the component status, execution results, and error details are summarized to generate a unified result and send it back to the upper layer.

[0014] Preferably, the system further includes a component initialization module, configured to initialize all abstract component instances when the system starts, including loading component parameters, verifying hardware connection status, and setting initial states.

[0015] Preferably, the system further includes an executability check module, configured to determine whether the command of the corresponding module is executable based on the current global state of the system and the real-time state of the abstract component.

[0016] The second aspect provides a method for controlling the business logic of a pick-and-place machine based on abstract components, including the following process: The command cache queue module receives commands from the upper layer; The command parameter verification module verifies the validity of the command parameters cached by the command cache queue module in real time. If the parameter is invalid, the command is intercepted and an error is returned to the upper layer. The executability check module determines whether the command of the corresponding module is executable based on the current global state of the system and the real-time state of the abstract component. If the target component is locked by other processes or is in a busy state, it is determined that it is not executable and the upper layer is notified. If possible, proceed to the next step; The user command monitoring module distributes verified commands to different units based on command type, including component control units, process control units, and combined process control units. The component control units centrally control each abstract component, with each abstract component instance corresponding to a physical component. The process control units combine multiple abstract component instances into standardized processes. When a standardized process starts, it automatically initiates resource locking requests to all involved abstract components. All locked resources are automatically released when the process ends normally or terminates abnormally. The combined process control units combine multiple standardized processes into an ordered sequence. Simultaneously, the device control process monitoring module monitors the command execution status at the hardware layer. If no command execution status is received within a specified time, it reports a timeout event to the user command monitoring module and coordinates for the system to enter a safe state.

[0017] Preferably, the method further includes: creating a unique corresponding abstract component instance for each physical component when the system starts up, initializing all abstract component instances by the component initialization module, the initialization including loading component parameters, verifying hardware connection status and setting initial state, and switching the system global state to idle after all components have been initialized.

[0018] A third aspect provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described method.

[0019] The beneficial effects of this invention are as follows: By constructing a unified business logic control center and an abstract component control model, the component collaborative control logic is completely separated from the specific hardware implementation, achieving centralized, closed-loop, and unique command execution. At the methodological level, standardized processes handle user commands to ensure the reliability of each instruction from issuance to execution and feedback throughout the entire chain. At the system architecture level, modular design achieves atomicity of component control and coordination of processes. This invention solves the conflict problem caused by multiple modules controlling the same component in traditional architectures from the software architecture design level, eliminates additional synchronization overhead, and achieves complete state closed-loop control. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram illustrating the implementation steps of the pick-and-place machine business logic control method based on abstract components according to the present invention. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] Please see Figure 1 As shown, a pick-and-place machine business logic control system based on abstract components includes: The command cache queue module is configured to receive and cache commands issued from the upper layer. The interaction between the command cache queue module and the upper layer is implemented through inter-process communication based on shared memory of the Boost library. After receiving a command, the command is temporarily stored in a thread-safe priority blocking queue, which adopts a dual sorting method of priority > timestamp. The command parameter verification module is configured to verify the validity of command parameters cached by the command cache queue module in real time. If the parameter is invalid, the command is directly intercepted and an error is returned to the upper layer. As the first line of defense for the system, this module performs mandatory multi-dimensional verification on the parameters immediately after the command is dequeued, including numerical boundaries (such as whether the coordinates exceed mechanical limits, whether the speed is within the allowable range of the device), format validity (such as data type, enumeration value, structural integrity), and logical consistency (such as the requirement that the fetch command must be associated with a valid nozzle type and vacuum threshold). Once an anomaly is detected, a standardized error code is generated and the subsequent process is interrupted to prevent illegal parameters from being passed to the underlying hardware driver and causing unpredictable behavior. At the same time, the error information is asynchronously returned to the upper user layer, realizing fault pre-interception and rapid feedback, which greatly improves the robustness and diagnosability of the system.

[0024] The user command monitoring module is configured to distribute verified commands to different units based on command type, including component control units, process control units, and combined process control units. The component control units are used to centrally control each abstract component, with each abstract component instance corresponding to a physical component. The process control units combine multiple abstract component instances into standardized processes. When a standardized process starts, it automatically initiates resource locking requests to all involved abstract components. All locked resources are automatically released when the process ends normally or terminates abnormally. The combined process control units combine multiple standardized processes into an ordered sequence. After distributing commands to different units according to command type, the user command monitoring module tracks command execution progress. If execution times out or fails, it automatically generates information feedback to the upper layer. Specifically, after distribution to different units, each command is assigned a unique command ID. An internally integrated independent monitoring timer continuously monitors the command execution status. If no feedback is received from the device control process monitoring module within a preset timeout threshold, a timeout event is proactively triggered, and the combined process control unit is notified to forcibly interrupt the current task. Simultaneously, the component status, execution results, and error details are summarized, and a unified result is generated and sent back to the upper layer. The user command monitoring module assumes the dual responsibility of command distribution hub and full lifecycle status tracking. It routes commands to the corresponding execution units based on their type (component control or process execution) and assigns a unique command ID to each command. Internally, it integrates an independent monitoring timer that continuously listens to command execution status. If no feedback is received from the lower layer within a preset timeout threshold, it proactively triggers a timeout event and notifies the combined process module to forcibly interrupt the current task. Simultaneously, it summarizes component status, execution results, and error details, generating a unified result to be sent back to the user interaction layer. This design achieves end-to-end closed-loop monitoring from command issuance to result feedback, significantly enhancing system efficiency.

[0025] The component control unit enables the unique, atomic, and centralized management of physical components. Each physical component in the system (such as the Z-axis, XY platform, and vacuum generator) corresponds to only one abstract component instance, exclusively controlled by this unit, completely eliminating resource contention and instruction conflicts caused by multiple modules concurrently calling the same hardware device. It encapsulates underlying hardware operations through a unified abstract interface and, in conjunction with an internal state machine, strictly manages the component's own state, ensuring that all action sequences possess atomicity and deterministic execution capabilities. It is the core carrier for achieving control convergence. The process control unit is responsible for encapsulating multiple atomic operations into reusable standardized process units (such as substrate transfer, component pickup, and placement positioning). Its core innovation lies in introducing a "short-term exclusive lock" mechanism. When a process starts, it automatically initiates resource lock requests to all involved abstract components. During the lock period, any instructions from other processes attempting to access these components will be directly rejected and a resource occupied error code will be returned. When the process ends normally or terminates abnormally, the system automatically releases all lock resources, restoring the components to a usable state. This mechanism ensures the integrity and isolation of complex action sequences, preventing external interference with process execution and improving the stability of equipment operation. The combined process control unit is designed for higher-level business scenarios. Based on state machine management, it organizes multiple sub-processes (such as warm-up, trial production, and production processes) into an ordered, configurable, and complex task chain, with each state node corresponding to a specific process instance. During execution, it recursively locks the involved sub-processes and their underlying components, forming a multi-layered resource protection barrier. It also supports logic such as conditional jumps, exception rollbacks, and timeout exits. It does not directly manipulate hardware but reuses the capabilities of lower-level component control and process control modules, focusing only on the orchestration of scheduling logic between processes, thereby enabling flexible expansion of business logic.

[0026] The device control process monitoring module is configured to monitor the command execution status of the hardware layer. If no command execution status is received within a specified time, it reports a timeout event to the user command monitoring module and coordinates the system to enter a safe state. This module is responsible for the last link in the closed-loop feedback chain and provides a safety fallback. On the one hand, it listens for the structured execution results returned by the hardware layer (including status codes, actual positions, and sensor values). On the other hand, it sets a dynamic timeout threshold for each hardware instruction. If the hardware layer fails to provide timely feedback, it proactively reports a timeout event and coordinates the system to enter a safe state.

[0027] Furthermore, the system also includes: The component initialization module is configured to initialize all abstract component instances when the system starts, including loading component parameters, verifying hardware connection status, and setting initial states. The executability check module is configured to determine whether the commands of the corresponding module are executable based on the current global state of the system and the real-time state of the abstract components.

[0028] The control method of the system of the present invention, such as Figure 1 As shown, the process includes the following: S1. Component initialization: When the system starts, it creates a unique abstract component instance for all physical components such as the mounting head, XY axis, conveyor module, and vacuum system. After completing parameter loading and hardware connection verification, it sets the component initialization state. Once all components have been initialized, the system global state switches to idle. S2, the command cache queue module receives commands from the upper layer (such as the user layer); the commands are encapsulated by the upper layer into a standard structure containing instruction type (such as component control, process execution), operation parameters (such as target position, speed), and priority, and are passed to the priority cache queue of the business logic layer in an asynchronous non-blocking manner to ensure decoupling between user operation and device execution; S3. The command parameter verification module verifies the legality of the command parameters cached by the command cache queue module in real time, checks the parameter value range, format specifications and logical consistency. If the parameter is invalid, the command is directly intercepted and an error is returned to the upper layer, interrupting the subsequent process. S4. The executability check module determines whether the command of the corresponding module is executable based on the current global state of the system (such as whether the device is in emergency stop or error mode) and the real-time state of the abstract component (such as whether the component is locked or idle). If the target component is locked by other processes or is in a busy state, it is determined that it is not executable and the upper layer is notified; if it is, the next step is executed. S5. Command Distribution: The user command monitoring module distributes verified commands to different units based on command type, including component control units, process control units, and combined process control units. The component control units centrally control each abstract component, with each abstract component instance corresponding to a physical component. The process control units combine multiple abstract component instances into standardized processes. When a standardized process starts, it automatically initiates resource locking requests to all involved abstract components. All locked resources are automatically released after the process ends normally or terminates abnormally. The combined process control units combine multiple standardized processes into an ordered sequence. Simultaneously, the device control process monitoring module monitors the command execution status at the hardware layer. If no command execution status is received within a specified time, a timeout event is reported to the user command monitoring module, and the system is coordinated to enter a safe state. Component control units execute atomic actions of single components, while process control units coordinate multiple components to complete complex collaborative operations. During process execution, involved components are automatically locked to ensure the action sequence is not disturbed by external interference until the process ends or is forcibly interrupted.

[0029] S6. After the hardware device completes its execution, the device control process monitoring module receives a structured result from the hardware layer, which includes the execution status, error codes, and key data, to ensure that the upper layer accurately obtains the hardware execution status.

[0030] S7. Software and hardware status consistency synchronization: After receiving hardware feedback, the device control process monitoring module immediately updates the status of the corresponding abstract component and synchronizes it to the system real-time data area to ensure that the software status is strictly consistent with the actual hardware status.

[0031] S8. Result Feedback: The equipment control process monitoring module will send the final execution result (including success confirmation, error details or timeout notification) back to the upper layer to complete the command loop. The upper layer can update the UI display or trigger subsequent processes based on the result.

[0032] The various modules of the system of this invention work together through standard interfaces to jointly support the implementation of the aforementioned control method and ensure that the system has high reliability, high maintainability and strong scalability.

[0033] Compared with existing technologies, the pick-and-place machine business logic layer control system based on abstract components proposed in this invention can fundamentally improve the inherent defects of traditional main control software architecture. Its outstanding beneficial effects are specifically reflected in the following aspects: (1) Fundamentally solve the problem of multi-module control conflict: By establishing the single control principle that each physical component corresponds to only one abstract component instance at the system level, and combining it with the component resource locking mechanism that is automatically triggered when the process is executed, the instruction conflict and resource contention caused by multiple functional modules operating the same hardware device in parallel are completely eliminated from the architecture design. This not only avoids the risk of hardware malfunction, but also eliminates the complex synchronization mechanism introduced in the traditional solution to avoid conflict, significantly reducing the extra overhead of the system during operation and improving the overall throughput efficiency and determinism.

[0034] (2) Achieving full-link closed-loop control to significantly improve system reliability: This invention constructs an end-to-end closed-loop control flow covering the entire process. Each link has clear status feedback and data synchronization points, ensuring that every operation can be tracked, verified and traced. Furthermore, the system behavior is based on real-time hardware status to make decisions, thereby ensuring the determinism and high reliability of instruction execution at the engineering level.

[0035] (3) Significantly enhances the maintainability and scalability of the system: This invention completely integrates the control logic within the system software layer. All component control, process orchestration, error handling, and other functions are undertaken by independent modules, which work together through clearly defined interfaces. On this basis, new physical components only need to inherit the unified standard interface and implement its core methods to be connected to the system without modifying the existing core code, which greatly shortens the product iteration cycle and reduces long-term maintenance costs and version management complexity.

[0036] (4) Optimize system real-time response capability and operational security: By introducing a priority-based command cache queue and a multi-level timeout monitoring mechanism, this invention ensures that security commands can receive a response within milliseconds while ensuring the orderly execution of routine tasks. When abnormal situations such as communication interruption or hardware unresponsiveness occur, the device control process monitoring module can proactively identify timeout events and immediately trigger safety recovery strategies such as emergency braking, resource release, and state switching to prevent the system from falling into a deadlock or out-of-control state.

[0037] In summary, the technical solution of this invention, by constructing a unified business logic control center and an abstract component control model, completely decouples the component collaborative control logic from specific hardware implementations, achieving centralized, closed-loop, and unique command execution. At the methodological level, standardized processes handle user commands, ensuring end-to-end reliability of each instruction from issuance to execution and feedback. At the system architecture level, modular design achieves atomicity of component control and coordination of processes. This invention solves the conflict problem caused by multiple modules controlling the same component in traditional architectures from a software architecture design perspective, eliminating additional synchronization overhead and achieving complete state closed-loop control.

[0038] The above description is merely an example and illustration of the concept of the present invention. Those skilled in the art can make various modifications or additions to the specific embodiments described or use similar methods to replace them, as long as they do not deviate from the concept of the invention or exceed the scope defined in this specification, they should all fall within the protection scope of the present invention.

Claims

1. A pick-and-place machine business logic control system based on abstract components, characterized in that, include: The command caching queue module is configured to receive and cache commands sent from the upper layer. The command parameter verification module is configured to verify the validity of command parameters cached by the command cache queue module in real time. If the parameter is invalid, the command is intercepted and an error is returned to the upper layer. The user command monitoring module is configured to distribute verified commands to different units based on command type, including component control units, process control units, and combined process control units. The component control units are used to centrally control each abstract component, with each abstract component instance corresponding to a physical component. The process control units are used to combine multiple abstract component instances into standardized processes. When a standardized process starts, it automatically initiates resource locking requests to all involved abstract components, and automatically releases all locked resources when the process ends normally or terminates abnormally. The combined process control units are used to combine multiple standardized processes into an ordered sequence, organizing multiple sub-processes into a task chain based on state machine management. Each state node corresponds to a specific process instance, and during execution, it recursively locks the involved sub-processes and their underlying components. Equipment control process monitoring module: It is configured to monitor the command execution status of the hardware layer. If no command execution status is received within a specified time, it reports a timeout event to the user command monitoring module and coordinates the system to enter a safe state.

2. The system according to claim 1, characterized in that, The interaction between the command cache queue module and the upper layer is implemented using a shared memory inter-process communication method based on the Boost library.

3. The system according to claim 1, characterized in that, After receiving a command, the command cache queue module temporarily stores the command in a thread-safe priority blocking queue, which adopts a dual sorting method of priority > timestamp.

4. The system according to claim 1, characterized in that, The user command monitoring module is configured to distribute commands to different units according to their types, track the execution progress of commands, and automatically generate information to feed back to the upper layer if execution times out or fails.

5. The system according to claim 4, characterized in that, The user command monitoring module is configured to distribute commands to different units according to their types, track the execution progress of commands, and automatically generate information to feed back to the upper layer if execution times out or fails. Specifically, after distributing commands to different units, a unique command ID is assigned to each command. The module continuously monitors the command execution status through an internally integrated independent monitoring timer. If no feedback is received from the device control process monitoring module within a preset timeout threshold, a timeout event is actively triggered and the combined process control unit is notified to forcibly interrupt the current task. At the same time, the module summarizes the component status, execution results, and error details, and generates a unified result to be sent back to the upper layer.

6. The system according to any one of claims 1-5, characterized in that, The system also includes a component initialization module, which is configured to initialize all abstract component instances when the system starts, including loading component parameters, verifying hardware connection status, and setting initial states.

7. The system according to claim 6, characterized in that, The system also includes an executability check module, which is configured to determine whether the commands of the corresponding module are executable based on the current global state of the system and the real-time state of the abstract components.

8. A method for controlling the business logic of a pick-and-place machine based on abstract components, characterized in that, The process includes the following: The command cache queue module receives commands from the upper layer; The command parameter verification module verifies the validity of the command parameters cached by the command cache queue module in real time. If the parameter is invalid, the command is intercepted and an error is returned to the upper layer. The executability check module determines whether the command of the corresponding module is executable based on the current global state of the system and the real-time state of the abstract component. If the target component is locked by other processes or is in a busy state, it is determined that it is not executable and the upper layer is notified. If possible, proceed to the next step; The user command monitoring module distributes verified commands to different units based on command type, including component control units, process control units, and combined process control units. The component control units centrally control each abstract component, with each abstract component instance corresponding to a physical component. The process control units combine multiple abstract component instances into standardized processes. When a standardized process starts, it automatically initiates resource locking requests to all involved abstract components. All locked resources are automatically released when the process ends normally or terminates abnormally. The combined process control units combine multiple standardized processes into an ordered sequence, organizing multiple sub-processes into a task chain based on state machine management. Each state node corresponds to a specific process instance. During execution, the involved sub-processes and their underlying components are recursively locked. Simultaneously, the device control process monitoring module monitors the command execution status at the hardware layer. If no command execution status is received within a specified time, a timeout event is reported to the user command monitoring module, and the system is coordinated to enter a safe state.

9. The method according to claim 8, characterized in that, The method further includes: when the system starts, a unique corresponding abstract component instance is created for each physical component, and the component initialization module initializes all abstract component instances. The initialization includes loading component parameters, verifying hardware connection status and setting initial state. After all components are initialized, the system global state is switched to idle.

10. A computer-readable storage medium having a computer program stored thereon, the program being executed by a processor to implement the method according to claim 8 or 9.

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