A memory management method and system applied to a low-power microcontroller

Abstract

The application relates to the technical field of microcontrollers, in particular to a memory management method and system applied to a low-power microcontroller. The system comprises a ring-shaped storage array which comprises a plurality of register nodes connected at the head and the tail through a shift logic circuit, is used for storing a logical address and storage data, and is provided with a fixed read-write window; an instruction monitoring unit is used for identifying a write instruction or a read instruction comprising a target logical address; and a shift execution unit is used for driving the shift logic circuit to perform data shift storage when the write instruction or the read instruction is received, until the target logical address is aligned to the fixed read-write window. The application converts the address searching into data rotation to the fixed read-write window by constructing the physical closed-loop ring-shaped storage array, and eliminates a large-scale selector network and decoding circuit.

Description

Technical Field

[0001] This application relates to the field of low-power microcontroller technology, and in particular to a memory management method and system for low-power microcontrollers. Background Technology

[0002] In microcontroller applications for sensor signal processing, hardware typically needs to buffer continuously generated data streams in real time for subsequent filtering, spectral analysis, or nonlinear calibration. Due to process and cost limitations, low-power microcontrollers often use relatively outdated processes (e.g., 180nm) and cannot utilize high-performance random access memory from advanced integrated circuit processes (e.g., 3nm). They generally use synchronous register arrays built with hardware description languages ​​to describe memory behavior. Implementing hardware with relatively outdated processes results in reduced performance; for example, addressing and reading / writing data takes a lot of time.

[0003] Existing sensor data caching solutions mainly fall into two categories: The first is traditional address decoding caching technology, which achieves random addressing through a multi-level selector network and address decoder. As the cache depth increases or the number of access ports increases, its combinational logic area expands exponentially, and address decoding and data gating consume a large amount of logic gate resources and wiring space. The second category is software circular caching technology, which implements a circular buffer by setting read / write pointers in memory and using software logic for modulo operations and boundary checks.

[0004] However, the aforementioned existing technologies have obvious drawbacks. In continuous sampling tasks, traditional address decoding caching schemes can lead to a lengthened critical path and a lower clock margin due to large-scale network selection, and frequent address switching can generate significant power consumption. On the other hand, software circular caching schemes often require cumbersome data transfer and splicing operations when processing sliding window data due to the discontinuous nature of physical memory. This not only consumes a large number of processor instruction cycles but also reduces the real-time performance of the system, making it difficult to meet the stringent requirements of ultra-low power sensor processing scenarios. Summary of the Invention

[0005] The purpose of this application is to provide a memory management method for low-power microcontrollers, comprising: constructing a ring-shaped memory array, the ring-shaped memory array including N register nodes, each register node being used to store a logical address and the corresponding stored data; physically connecting adjacent register nodes with shift logic circuits to form a closed-loop structure, and the stored data can be shifted and stored through the shift logic circuits; each register node having a fixed physical address, and designating one of the physical addresses as a fixed read / write window; monitoring write or read instructions, each of the write or read instructions including at least a target logical address; when the write or read instruction is received, the logical address and the corresponding stored data in the register nodes of the ring-shaped memory array are shifted and stored according to a preset ring shift direction until the target logical address and the corresponding stored data are moved to the register node to which the fixed read / write window belongs; and performing a write or read operation through the register node to which the fixed read / write window belongs.

[0006] A further approach is that the shift storage process employs a differential driving mechanism, specifically including: calculating the address difference between the target logical address and the current logical address currently stored in the fixed read / write window; determining the shift step sequence based on the address difference; and driving the shift logic circuit to perform data rotation and alignment according to the shift step sequence.

[0007] A further solution is that determining the shift step sequence based on the address difference specifically includes: splitting the address difference into a continuous shift step sequence, wherein the shift step sequence includes a first shift step, a second shift step, ..., a Kth shift step, and the sum of the values ​​of the first shift step, the second shift step, ..., the Kth shift step equals the address difference.

[0008] A further approach is that the values ​​of all shift steps in the shift step sequence must satisfy the condition that the total number N of register nodes in the circular storage array is divisible by the value of the shift step.

[0009] A further embodiment includes a direction adaptive optimization step in the shift storage process: calculating the distance between the clockwise shift path and the counterclockwise shift path based on the positive or negative attribute of the address difference and the total number of register nodes; and selecting the direction corresponding to the path with the shorter distance as the preset circular shift direction.

[0010] A further approach is that the shift storage process is controlled in a closed loop using timing signals, which include: an alignment ready signal, used to indicate that the target logical address has been moved to the fixed read / write window and to trigger the write or read operation; and a step size warning signal, used to issue a warning when the target logical address is only one shift size away from the fixed read / write window, so as to switch the timing state.

[0011] A further embodiment includes an output ready signal in the shift storage process. The output ready signal is used to feed back a busy status to the microcontroller bus during the execution of the shift storage operation and to release bus access permissions after the alignment is completed, so as to achieve a data handshake without delay.

[0012] A further approach is that the ring-shaped storage array is also associated with a state synchronization mechanism, which is used to record the shift history in real time and synchronously update the mapping relationship between the logical address and the stored data in all register nodes when the shift storage is performed.

[0013] A further solution is that, when applied to nonlinear calibration scenarios of rotary encoders, the ring storage array stores multiple preset reference calibration points. Based on the mechanical rotation direction of the rotary encoder, the ring storage array is driven to synchronously rotate clockwise or counterclockwise, so that the calibration parameters corresponding to the current mechanical position are always physically aligned with the fixed read / write window.

[0014] The second objective of this application is to provide a memory management system for low-power microcontrollers, including a ring-shaped storage array comprising multiple register nodes connected end-to-end by shift logic circuits for storing logical addresses and data, and a fixed read / write window through which write or read operations are performed; an instruction monitoring unit for identifying write or read instructions including a target logical address; and a shift execution unit for driving the shift logic circuits to perform data shifting and storage upon receiving the write or read instruction, until the target logical address is moved to the fixed read / write window. Attached Figure Description

[0015] Figure 1 This is a block diagram of the memory management system of this application.

[0016] Figure 2 This is a schematic diagram of the memory management method of this application to be rotated.

[0017] Figure 3 This is a rotating diagram illustrating the memory management method of this application.

[0018] Figure 4 This is a schematic diagram illustrating the data writing method of the memory management approach in this application. Detailed Implementation

[0019] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0020] Low-power microcontrollers for sensor signal processing are typically used to handle continuous data streams from sensors such as analog-to-digital converters, pulse density modulation microphones, or rotary encoders. Limited by outdated manufacturing processes (e.g., 180nm) or cost constraints, their internal memory units often cannot integrate high-density static random access memory (SRAM) IP cores (e.g., 3nm). Instead, they must use synchronous register arrays written in hardware description languages ​​to describe the functionality of the random access memory. In traditional solutions, to support random access to the register array, a large address decoder and MUX (Multiplexer) network must be constructed. For example, for an array with a depth of 1024 (1KB) and a data width of 8 bits, a single byte random read is equivalent to a... A 1024-to-1 MUX exhibits a dramatic increase in combinational logic area, wiring complexity, and dynamic power consumption as the depth reaches hundreds to thousands of bytes or the number of ports increases, potentially exceeding the size of the memory cell itself. This also significantly lengthens the critical path and reduces clock margin. This is extremely uneconomical for sensor applications that continuously perform data sampling, filtering, energy calculation, or spectral analysis, as a large number of clock cycles and energy are consumed in address management and data stitching. This application fundamentally changes the access method of the memory array, transforming "moving read / write ports to find data" into "rotating data to align it with a fixed read / write window." This completely eliminates the large-scale MUX / decoding network required for random addressing at the hardware level, achieving comprehensive optimization of area, power consumption, and real-time performance.

[0021] like Figure 1 As shown in the figure, this application discloses a memory management system for a low-power microcontroller, including a ring memory array. The ring memory array includes multiple register nodes connected end-to-end by shift logic circuits for storing logical addresses and data, and is provided with a fixed read / write window through which write or read operations are performed; an instruction monitoring unit for identifying write or read instructions including target logical addresses; and a shift execution unit for driving the shift logic circuits to shift and store data when a write or read instruction is received, until the target logical address is moved to the fixed read / write window.

[0022] like Figure 1-4As shown, this application provides a memory management method for low-power microcontrollers, comprising: constructing a ring-shaped memory array, the ring-shaped memory array including N register nodes, each register node being used to store a logical address and the corresponding stored data; setting shift logic circuits to physically connect adjacent register nodes to form a closed-loop structure, and the shift storage of stored data can be realized through the shift logic circuits; each register node having a fixed physical address, and designating one of the physical addresses as a fixed read / write window; monitoring write instructions or read instructions, each write instruction or read instruction including at least a target logical address; when a write instruction or read instruction is received, the logical address and the corresponding stored data in the register nodes of the ring-shaped memory array are shifted and stored according to a preset ring shift direction until the target logical address and the corresponding stored data are moved to the register node to which the fixed read / write window belongs; and performing a write or read operation through the register node to which the fixed read / write window belongs.

[0023] Understandably, a ring-shaped memory array comprises N register nodes, where N is an integer greater than 1. Its typical value depends on the sliding window depth requirements of the target application scenario, and can be, for example, 128, 256, 512, or 1024. Each register node is physically an independent storage unit, typically implemented by a set of synchronous D-type flip-flops. Its storage content consists of two parts: the first part is a logical address field with a width of L bits, and the second part is a storage data field with a width of H bits. The logical address width L must satisfy 2^L ≥ N to ensure that all logical locations within the array depth range can be uniquely identified. For example, when N = 256, L is at least 8 bits. The storage data width H depends on the application's data... Precision settings are commonly 8 bits, 12 bits, 16 bits, or 32 bits, to match the resolution of the analog-to-digital converter or the processor word length. Each register node in the circular memory array has a unique and permanently fixed physical address, which is determined by its physical wiring position during manufacturing. It is typically numbered sequentially using consecutive integers from 0 to N-1, and this physical address does not change with any operations on the data stored in the circular memory array. To achieve circular data flow, adjacent register nodes can be physically connected via shift logic circuits. Specifically, the register node with physical address i (0 ≤ i ≤ N-1) has its two ends connected to the register node with physical address (i+1) via shift logic circuits. The register nodes with a physical address of (i-1) mod N and the register nodes with a physical address of (i-1) mod N, and so on, eventually form a closed loop structure with all N register nodes physically connected end to end; the shift logic circuit includes a controlled data path selection function, which, under the action of the shift control signal, determines whether each register node retains its current stored content in each clock cycle or receives content passed from one of its neighboring nodes (which may not be directly adjacent, see the differential drive later for details); this shift logic circuit is usually composed of a set of multiplexers, and its selection end is driven by the shift execution unit.

[0024] The fixed read / write window is a pre-selected physical address from N physical addresses, serving as the sole hardware interface for data exchange with the microcontroller's internal system bus or external control logic. The register node corresponding to the selected physical address is designated as the fixed read / write window. In engineering implementation, to simplify address decoding and wiring, the physical address (RAM[0]) is usually preferred as the fixed read / write window. However, this application is not limited to this, and theoretically, any physical address between 0 and N-1 can be selected. The microcontroller's internal system bus or external control logic can only complete all write or read operations on the ring memory array by accessing this fixed physical address. This means that no matter which logical address the software or upper-level logic wants to access, it must ultimately "transport" the data corresponding to that logical address to this fixed physical address node through a mechanism before it can perform actual read / write operations. The above design is the key to this application's ability to eliminate the complexity of random addressing, because it permanently simplifies the external hardware interface into a single fixed access point.

[0025] A logical address is a concept decoupled from a physical address, used to characterize the position number of stored data in a certain logical sequence or semantic order. This logical sequence can be a continuous sampling sequence in time (e.g., the sampling point sequence of an analog-to-digital converter), a sliding window sequence in space, or a preset calibration parameter table index sequence, etc. For example, in continuous sampling applications of analog-to-digital converters, the logical address can be defined as the chronological order of sampling time. The logical address ram0 represents the earliest (or oldest) sampling point, and the logical address ramM-1 (where M is generally the same as N, and M is used here to distinguish between physical and logical addresses) represents the latest (or most recent) sampling point, or the opposite convention can be used. The mapping relationship between logical addresses and physical addresses is dynamic and variable. After the ring memory array is initialized, the data stored at any physical address corresponds to a specific logical address, and this "physical address-logical address-stored data" binding relationship is not immutable. It flows synchronously in the ring memory array with the shift storage operations described later.

[0026] The process of monitoring write or read instructions is accomplished by an instruction monitoring unit integrated into the ring memory array control logic. This unit monitors signals from the microcontroller's internal system bus or external control logic. A write instruction is typically represented by a write enable (e.g., we=1) pulse signal with a one-clock-cycle width, accompanied by a target logical address (target_idx) stabilized on the address bus and the data to be written (write_data) on the data bus. A read instruction is represented by a read enable (e.g., we=0) pulse signal with a one-clock-cycle width, accompanied by a target logical address stabilized on the address bus. The control logic needs to latch this information on the clock edge when the instruction is valid.

[0027] like Figure 2 As shown, when the instruction monitoring unit successfully latches a valid instruction, it triggers a shift storage process. This shift storage process is controlled by the shift execution unit, which dynamically adjusts the mapping relationship between logical addresses and physical addresses in the circular memory array. The target logical address specified in the instruction (and its current corresponding stored data) is moved to the register node (e.g., physical address RAM[0]) of the fixed read / write window through a circular rotation. Figure 3 As shown, to achieve this goal, the shift execution unit drives the shift logic circuit, causing the logical addresses and corresponding stored data stored in all register nodes that need to be moved in the circular memory array to move synchronously as a whole along a preset circular shift direction (clockwise or counterclockwise). Each time it moves, all data and their associated logical addresses move forward by one step's node position. This process iterates until an internal state comparison reveals that the target logical address has appeared in the logical address field of the fixed read / write window node; at this point, the alignment is considered complete. Figure 4 As shown, once alignment is complete, if the current operation is a write operation, the previously latched data to be written is overwritten into the fixed read / write window node; if the current operation is a read operation, the stored data is directly read from the fixed read / write window node, which is the data corresponding to the requested target logical address, and is output through the data bus. Therefore, the external interface is permanently simplified, and the complex address decoding and multiplexing network is replaced by a relatively simple shift control network and fixed read / write window, thereby achieving significant benefits in silicon area and access latency, which is particularly suitable for application scenarios with highly regular access patterns, such as sensor data streams.

[0028] Understandably, the shift storage process can employ a differential-driven mechanism, specifically including: calculating the address difference between the target logical address and the current logical address stored in the fixed read / write window; determining the shift step sequence based on the address difference, and driving the shift logic circuit to perform data rotation and alignment according to the shift step sequence; wherein, determining the shift step sequence based on the address difference specifically includes: splitting the address difference into a continuous shift step sequence, the shift step sequence including the first shift step, the second shift step, ..., the Kth shift step, where the sum of the values ​​of the first shift step, the second shift step, ..., the Kth shift step equals the address difference; the values ​​of all shift steps in the shift step sequence must satisfy: the total number of register nodes in the circular memory array is divisible by the value of the shift step, i.e., K mod N = 0. For example, suppose the total number of register nodes in the ring memory array is 1024 and the address difference is 11. The first shift step can be 8, the second shift step can be 2, and the third shift step can be 1. The sum of all shift steps is 8+2+1=11, which is exactly equal to the address difference of 11. It also satisfies that the total number of register nodes N in the ring memory array is divisible by the value of all shift steps.

[0029] The differential drive mechanism enables rotations with larger strides, thus completing alignment in fewer clock cycles, significantly reducing access latency and the dynamic power consumption of the rotation operation itself. This differential drive mechanism first requires calculating the address difference. The shift execution unit reads its currently stored logical address from the fixed read / write window node, called the current logical address (denoted as current_idx), and obtains the target logical address (denoted as target_idx) from the latched instruction. The address difference (denoted as delta) needs to represent the shortest rotation required to move from the current logical address current_idx to the target logical address target_idx. Due to the characteristics of the ring structure, there are clockwise and counterclockwise directions, and the difference calculation must consider the direction. A common calculation method is to first perform signed subtraction and then take the modulus: delta = |target_idx - current_idx| mod N, where delta represents the shortest number of rotation steps, and the sign (positive or negative) of target_idx - current_idx indicates the rotation direction to achieve that shortest number of rotation steps. For example, a positive sign usually corresponds to a clockwise direction, and a negative sign corresponds to a counterclockwise direction.

[0030] After obtaining the address difference delta, the differential driving mechanism determines a shift step sequence [S1, S2, ..., SK] based on this address difference, instead of simply performing delta single-step (step size 1) rotations; where K is the number of steps in the shift step sequence, each shift step Sj (1 ≤ j ≤ K) is a positive integer step size value, and the sum of all step size values ​​in the shift step sequence must equal the total number of rotations required (address difference delta), i.e., S1 + S2 + ... + SK=delta; During execution, the shift logic circuit will be configured with step sizes S1, S2, ..., SK in sequence, with each step size corresponding to a rotation operation in one clock cycle; for example, if delta=11 and a shift step size sequence [8,2,1] is used, the system will perform rotations with a step size of 8, a step size of 2, and a step size of 1 in three consecutive clock cycles, completing the alignment in a total of 3 cycles. Compared to performing 11 single-step rotations which requires 11 cycles, the speed is significantly improved.

[0031] The specific algorithm for determining the shift step sequence based on address differences can be efficiently implemented in hardware. A typical strategy is based on a predefined set of available step sizes that conforms to hardware constraints. The generation of this set of available step sizes follows a key constraint: the total number N of register nodes in the circular memory array must be divisible by the value of each selected shift step size Sj. The mathematical essence of this constraint is to ensure that the rotation operation performed with step size Sj is deterministic and will not lead to data conflicts or loss. For example, when N=1024, its factors include 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, and these values ​​constitute the set of available step sizes. Therefore, when N=1024, the address difference delta is 11, and the selected step sizes 8, 2, and 1 are all factors of 1024, satisfying the divisibility constraint.

[0032] An algorithm for determining the shift step sequence can be a greedy decomposition method: from the set of available step sizes (usually sorted in descending order), sequentially select the largest step size that does not exceed the remaining distance, until the remaining distance is reduced to 0; for example, for delta=11 and N=1024, the set of available step sizes is {1024,512,256,128,64,32,16,8,4,2,1}; first, when the remaining distance is 11, the maximum available step size is 8 (because 16>11), so select S1=8 and update the remaining distance to 11-8=3; then, when the remaining distance is 3, the maximum available step size is 2. (Because 4>3), select S2=2, update the remaining distance to 3-2=1; finally, when the remaining distance is 1, the maximum available step size is 1, select S3=1, update the remaining distance to 1-1=0; finally, the shift step size sequence [8,2,1] is obtained; this greedy decomposition method can be implemented in hardware by a priority encoder and a subtractor state machine, or for lower latency, the optimal shift step size sequence corresponding to all possible address differences delta (0 to N-1) can be pre-calculated and stored in a lookup table, and the shift step size sequence can be read directly by using the address difference delta as the index.

[0033] The drive shift logic circuit operates according to the shift step sequence, which means that in each clock cycle, according to the current shift step Sj, the register node with physical address i passes its contents (logical address + stored data) to the register node with physical address (i+Sj) mod N (clockwise) or (i-Sj) mod N (counterclockwise).

[0034] It is understandable that the shift storage process may also include a direction adaptive optimization step: calculate the distance between the clockwise shift path and the counterclockwise shift path based on the positive or negative attribute of the address difference and the total number of register nodes; select the direction corresponding to the shorter path as the preset circular shift direction.

[0035] Specifically, in a ring structure, there are two paths from one point to another, which may have different lengths. The adaptive optimization step ensures that the system always chooses the shortest path for rotation, thereby minimizing the number of rotation steps required. The specific calculation is performed immediately after obtaining the target logical address target_idx and the current logical address current_idx.

[0036] The formula for calculating the clockwise distance dist_cw is: dist_cw = (target_idx - current_idx + N) mod N; this formula ensures that when the target logical address target_idx is greater than or equal to the current logical address current_idx, the clockwise distance dist_cw is equal to their difference; when the target logical address target_idx is less than the current logical address current_idx, the clockwise distance dist_cw is equal to their difference plus N, and the result is a value within the range of [0, N - 1], representing the minimum number of steps required for clockwise rotation.

[0037] The formula for calculating the counterclockwise distance dist_ccw is: dist_ccw = (current_idx - target_idx + N) mod N; similarly, this counterclockwise distance represents the minimum number of steps required for counterclockwise rotation, and its range is also within [0, N - 1].

[0038] Subsequently, a comparator is used to compare the clockwise distance dist_cw and the counterclockwise distance dist_ccw; if dist_cw < dist_ccw, the clockwise direction is selected as the preset direction for this shift, and the final distance to be moved final_dist = dist_cw; if dist_ccw < dist_cw, the counterclockwise direction is selected, and the final distance to be moved final_dist = dist_ccw; if the two are equal (this may occur when N is even and the target is exactly at the diametric point), the clockwise or counterclockwise direction can be selected according to the preset default policy, such as fixedly selecting the clockwise direction; this value of the final distance to be moved final_dist is the address difference delta to be decomposed in the differential drive mechanism.

[0039] It can be understood that the shift storage process can be closed-loop controlled by timing signals, and the timing signals include: an alignment ready signal, which is used to indicate that the target logical address has been moved to the fixed read / write window and trigger a write or read operation; a step preview signal, which is used to give a preview when the target logical address is only one shift step away from the fixed read / write window to switch the timing state.

[0040] The alignment ready signal (denoted as rdy) is a status signal output to the upper-level controller. Its logic level is defined as follows: When rdy = 1 (high level), it indicates that the ring memory array is ready and can immediately accept and begin executing a new read / write instruction; when rdy = 0 (low level), it indicates that the ring memory array is busy performing a rotation alignment operation, and any new instruction pulses should be ignored. Its control logic is as follows: In the initial idle state or after an operation is completed, the alignment ready signal rdy is set to 1; when a valid instruction pulse is detected and the current alignment ready signal rdy = 1, the control logic latches... Within the same clock cycle of the instruction, the alignment ready signal rdy is pulled low to 0, indicating that the operation has started and the ring memory array enters a "busy" state. Thereafter, the alignment ready signal rdy remains 0 until the rotation alignment process is complete. At the clock cycle when alignment is complete, the alignment ready signal rdy is reset to 1, marking the end of the current operation and the ring memory array becoming ready again to accept the next command. For write operations, the actual data writing occurs on (or synchronously with) the clock edge when the alignment ready signal rdy changes from 0 to 1. For read operations, when the alignment ready signal rdy changes to 1, the data output from the fixed read / write window is the stable and valid target data.

[0041] The step size prediction signal (in this embodiment, for the case where the last step size in single-step rotation or differential drive is 1, it is commonly represented by the diff_one signal) is an internally used prediction signal to achieve smoother state transitions and "delay-free write" optimization. The step size prediction signal diff_one is set to a high level when the following conditions are met: After internal calculation or state tracking, it is determined that the target logic address is aligned to the fixed read / write window with only one shift step size remaining (i.e., alignment will definitely be completed in the next clock cycle). In single-step rotation mode, this means that the remaining rotation steps are equal to 1. In differential drive mode, this usually occurs one clock cycle before the clock cycle that executes the last step size (often 1) in the shift step sequence. The step size prediction signal diff_one is used to provide advance. When the step size prediction signal diff_one=1, the control logic... The algorithm can perform two important operations: First, it can release the ready signal in advance: the alignment ready signal rdy can be set to 1 in the current cycle (i.e., the cycle before alignment is completed), instead of waiting until the alignment is completed. In this way, from the perspective of the external bus, the wait for the last rotation cycle is "hidden". The bus can prepare the address and data for the next access while performing the last rotation inside the ring memory array, thereby realizing pipelined operation and improving throughput. Second, it can optimize the write timing: for write operations, if the data to be written has been latched in an internal register wd_reg when the instruction is issued, then when the step size warning signal diff_one=1 and the current state is write, the data in the internal register wd_reg can be used directly to perform the write in the next clock cycle (i.e., the alignment cycle). The control condition is usually (diff_one & we_state), where we_state is the state bit indicating the current state of the write operation. This avoids spending an extra cycle to fetch data from the bus or perform the write after alignment is completed, thereby achieving zero-beat write latency in some cases. Another special case is full alignment, where the target logical address is equal to the current logical address from the beginning. In this case, an unread signal diff_nul (diff_nul=1) will be generated, indicating that no rotation is needed. At this time, the alignment ready signal rdy remains at 1, and write or read operations can be performed immediately.

[0042] Understandably, the shift storage process also includes an output ready signal, which is used to report a busy status to the microcontroller bus during the shift storage operation and to release bus access permissions after alignment is complete, so as to achieve a delay-free data handshake.

[0043] Specifically, the output ready signal is the alignment ready signal rdy mentioned above. Here, we will focus on its specific functions and timing interactions in the handshake with the microcontroller bus, that is, the mechanism for achieving a delay-free data handshake.

[0044] In microcontroller systems, when the CPU needs to access a peripheral device (here, the memory management system of this application), a handshake protocol is typically used to coordinate the speed of both parties. A common protocol is that the master device (CPU) initiates the access, and the slave device (the memory management system of this application) indicates whether data transfer can be completed via a ready signal (the alignment ready signal rdy of this application). A typical example of its handshake timing is as follows: First, in the idle state, the slave device outputs rdy=1; the master device detects rdy=1 in the T0 clock cycle, and then initiates a write bus cycle in the T1 clock cycle, setting the write enable we high for one cycle, and simultaneously sending the target logical address target_idx and the data to be written write_data to the bus; the slave device detects we=1 and rdy=1 on the rising edge of the T1 clock, and then performs the following operations: latches target_idx and write_data into internal registers; immediately pulls the output port rdy low to 0 (this change occurs on the rising edge of the T1 clock cycle). (Effected within T1 cycle or at the beginning of T2 cycle); When the master device detects rdy=0 in T2 cycle, it knows that the slave device is not ready, so it enters a waiting state, keeps the address and data lines stable, and may insert a waiting cycle; At the same time, the slave device starts the rotation alignment operation internally; After several clock cycles, when the alignment is about to be completed (diff_one=1), the slave device presets rdy to 1 before the next clock cycle (let's say Tk); In the Tk clock cycle, the alignment is completed. If it is a write operation, the latched write_data is written to the fixed read / write window in this cycle; When the master device detects that rdy goes high again in Tk cycle, it knows that the current write operation is completed, so it ends the current bus transaction and can initiate a new access in the next cycle (Tk+1); For read operations, the process is similar. When the master device detects that rdy goes high, the read data read_data on the bus (from the fixed window) is valid data. The CPU latches the data and ends the read transaction.

[0045] Understandably, the ring memory array is also associated with a state synchronization mechanism, which is used to record the shift history in real time and synchronously update the mapping relationship between the logical address and the stored data in all register nodes when performing shift storage.

[0046] The state synchronization mechanism is designed to maintain the logical consistency of the ring memory array. It ensures that after each shift operation, the "logical address-stored data" pair stored in the register node corresponding to each physical address in the ring memory array can correctly reflect the data that the physical location should represent in the logical sequence after this rotation. This state synchronization mechanism can be automatically maintained by hardware and is transparent to software.

[0047] In this embodiment, when applied to a nonlinear calibration scenario of a rotary encoder, the ring storage array stores multiple preset reference calibration points. The ring storage array is driven to rotate clockwise or counterclockwise synchronously according to the mechanical rotation direction of the rotary encoder, so that the calibration parameters corresponding to the current mechanical position are always physically aligned with the fixed read / write window.

[0048] In this scenario, the rotary encoder outputs the raw digital readings of the shaft angular position. However, due to machining errors, installation eccentricity, or nonlinear transfer functions, these raw readings need to be corrected by a calibration table to obtain accurate angle values. Traditional methods use lookup tables, which require real-time calculation of which two calibration points the current angle falls between before addressing and interpolating, resulting in high hardware overhead.

[0049] The method of this application is implemented in the following steps: First, during the system calibration stage, the mechanical shaft of the rotary encoder is rotated at a constant speed for one full revolution. During this process, Q reference calibration points (Q=N, where N is the depth of the ring storage array) are selected at equal intervals or non-equal intervals according to the nonlinear characteristics. Each reference point f (0≤f≤Q-1) contains its corresponding precise mechanical angle θ_f and a set of calibration parameters P_f (e.g., the slope and intercept of linear correction, or the coefficients of higher-order polynomials). Logical addresses are sequentially assigned to these reference points in the clockwise direction of the mechanical rotation. For example, the logical address of the starting point (such as the zero position) is assigned... Set it to 0, the next clockwise logical address is 1, up to Q-1; then, these {logical address f, calibration parameter P_f} pairs are sequentially preloaded into the register nodes with consecutive physical addresses in the ring memory array; a convenient loading method is: write the parameter P_0 of logical address 0 to physical address 0, the parameter P_1 of logical address 1 to physical address 1, ..., the parameter P_{Q-1} of logical address Q-1 to physical address N-1; after initialization, ensure that the fixed read / write window (physical address 0) is aligned with the mechanical zero position of the encoder, that is, the parameter P_0 of logical address 0 is stored.

[0050] During operation, the rotary encoder shaft begins to rotate, typically generating two signals: an encoder pulse signal (one pulse is generated for each minimum angle unit of rotation) and a direction signal (DIR, high level indicates clockwise, low level indicates counterclockwise). The memory management system of this application is configured to: upon detecting an encoder pulse signal, drive the circular storage array to perform a single-step rotation based on the current direction signal DIR. If DIR indicates clockwise, the circular storage array performs a single-step clockwise rotation; if DIR indicates counterclockwise, the circular storage array performs a single-step counterclockwise rotation. This drive can be a direct hardware connection, with the encoder pulse signal serving as the shift trigger clock and the direction signal DIR serving as the shift direction control.

[0051] Understandably, the reference parameter table stored in the ring memory array flows synchronously in the same direction as the mechanical axis rotates, much like a parameter conveyor belt. The direct effect is that regardless of the encoder axis's mechanical position, the calibration parameters stored in the register node corresponding to the fixed read / write window (physical address 0) are always the parameters corresponding to the reference point at the current mechanical position. When the microcontroller software needs to read the current calibration parameters, it doesn't need to perform any calculations or table lookups; it simply reads the data from the fixed physical address to immediately obtain the correct parameters. This parameter servo mechanism tightly couples mechanical motion with memory access at the hardware level, completely eliminating runtime overhead from table lookup calculations, comparisons, and random access, achieving extremely low-latency parameter acquisition. It is particularly suitable for applications with extremely high real-time requirements, such as servo control and robot joint positioning.

[0052] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of devices and functional modules is merely an example. In practical applications, the functions described above can be assigned to different devices and functional modules as needed. For instance, the internal structure of a device can be divided into different functional modules, a device or functional module can be decomposed into several devices and / or functional modules, different devices and / or functional modules can be merged into one device or functional module, or parts of the internal structure of different devices can be recombined into a new functional module to complete all or part of the functions described above. The specific working process of the systems, devices, and units described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0053] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. If the integrated units are implemented as software functional units and sold or used as separate products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of this application, in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device or processor to execute all or part of the steps of the methods described in the various embodiments of this application.

[0054] The above embodiments are only used to provide a detailed description of the technical solutions of this application. However, the description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application, and should not be construed as a limitation of this application. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application.

Claims

1. A memory management method for low-power microcontrollers, characterized in that, include: Construct a ring-shaped storage array, which includes N register nodes, each of which is used to store a logical address and the corresponding storage data. Shift logic circuits are physically connected between adjacent register nodes to form a closed-loop structure, and the shift storage of the stored data can be realized through the shift logic circuits; each register node has a fixed physical address, and one of the physical addresses is designated as a fixed read / write window; Monitor write or read instructions, each of which includes at least a target logical address; When the write instruction or read instruction is received, the logical address and the corresponding stored data in the register node of the ring storage array are shifted and stored according to the preset ring shift direction until the target logical address and the corresponding stored data are moved to the register node to which the fixed read / write window belongs, while the physical address of each register node remains unchanged. The shift storage process adopts a differential driving mechanism, which specifically includes: calculating the address difference between the target logical address and the current logical address currently stored in the fixed read / write window, and breaking down a long-distance shift into multiple shifts of different lengths based on the address difference; Write or read operations are performed through the register node to which the fixed read / write window belongs.

2. The memory management method for low-power microcontrollers according to claim 1, characterized in that, The step of breaking down a long-distance shift into multiple shifts of different step lengths based on the address difference specifically includes: determining a shift step sequence based on the address difference, and driving the shift logic circuit to perform data rotation and alignment according to the shift step sequence.

3. The memory management method for low-power microcontrollers according to claim 2, characterized in that, The step of determining the shift step sequence based on the address difference specifically includes: splitting the address difference into a continuous shift step sequence, wherein the shift step sequence includes a first shift step, a second shift step, ..., a Kth shift step, and the sum of the values ​​of the first shift step, the second shift step, ..., the Kth shift step equals the address difference.

4. The memory management method for low-power microcontrollers according to claim 3, characterized in that, All shift step values ​​in the shift step sequence must satisfy the following condition: the total number N of register nodes in the circular storage array is divisible by the value of the shift step.

5. The memory management method for low-power microcontrollers according to claim 2, characterized in that, The shift storage process also includes a direction adaptive optimization step: based on the positive or negative attribute of the address difference and the total number of register nodes, the distance between the clockwise shift path and the counterclockwise shift path is calculated; the direction corresponding to the path with the shorter distance is selected as the preset circular shift direction.

6. The memory management method for low-power microcontrollers according to claim 1, characterized in that, The shift storage process is controlled in a closed loop using timing signals, which include: The alignment ready signal is used to indicate that the target logical address has been moved to the fixed read / write window and to trigger the write or read operation; A step size warning signal is used to issue a warning when the target logical address is only one shift step away from the fixed read / write window, so as to switch the timing state.

7. The memory management method for low-power microcontrollers according to claim 6, characterized in that, The shift storage process also includes an output ready signal, which is used to feed back a busy status to the microcontroller bus during the execution of the shift storage operation and to release bus access permissions after alignment is completed, so as to achieve a delay-free data handshake.

8. The memory management method for low-power microcontrollers according to claim 1, characterized in that, The ring-shaped storage array is also associated with a state synchronization mechanism, which is used to record the shift history in real time and synchronously update the mapping relationship between logical addresses and stored data in all register nodes when the shift storage is performed.

9. The memory management method for low-power microcontrollers according to claim 1, characterized in that: When applied to nonlinear calibration scenarios of rotary encoders, the ring storage array stores multiple preset reference calibration points. According to the mechanical rotation direction of the rotary encoder, the ring storage array is driven to rotate clockwise or counterclockwise synchronously, so that the calibration parameters corresponding to the current mechanical position are always physically aligned with the fixed read / write window.

10. A memory management system for low-power microcontrollers, characterized in that: The system implements the method as described in any one of claims 1-9, including A ring-shaped memory array includes multiple register nodes connected end-to-end by shift logic circuits for storing logical addresses and data, and is equipped with a fixed read / write window through which write or read operations are performed. The instruction monitoring unit is used to identify write or read instructions, including those targeting logical addresses. The shift execution unit is used to drive the shift logic circuit to perform data shifting and storage when the write instruction or read instruction is received, until the target logical address is moved to the fixed read / write window.

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