An auxiliary driving circuit and a display panel

Abstract

The application discloses an auxiliary driving circuit and a display panel. The auxiliary driving circuit comprises a clock driving module connected to a clock line and a pseudo gate driving module connected to the clock driving module. The clock driving module comprises a first pull-up unit and a first pull-down unit. The first pull-up unit and the first pull-down unit each comprise at least two series-connected switch tubes. The at least two series-connected switch tubes of the first pull-up unit are configured to be turned on in response to a first scanning signal output by one pseudo gate driving module when a clock signal is a rising edge, so as to perform level pull-up on the clock signal. The at least two series-connected switch tubes of the first pull-down unit are configured to be turned on in response to a second scanning signal output by another pseudo gate driving module when the clock signal is a falling edge, so as to perform level pull-down on the clock signal. In this way, the waveform quality of the clock signal can be improved, thereby improving the display quality.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an auxiliary driving circuit and a display panel. Background Technology

[0002] The display principle of liquid crystal displays (LCDs) lies in the deflection of liquid crystals under external control. The deflection state determines the light transmittance, and the different states of each pixel unit combine to create the desired display image. The deflection of the liquid crystal depends on the potential between the pixel electrode and the common electrode in the pixel unit. The potential is determined by the TFT (Thin-Film Transistor) device of the pixel unit as a switch and the data line as a data source.

[0003] The display process for each frame is performed in a line-by-line scanning manner. Each row of pixels has a scan line, which is activated line by line under the action of the scan signal (gate signal), thus completing the activation of each pixel and allowing the target voltage to be input through the data line. The activation of the scan lines is generally given by the GOA (Gate Driver on Array) circuit, which provides the scan signal and performs the function of activating each line.

[0004] The GOA (Gateway Auto-Action) is able to perform progressive scan because it contains cascaded gate drive modules. These modules sequentially output scan signals under the sequential drive of multiple clock signals. When the display panel size is large, the number of cascaded gate drive modules also increases. The path of the clock signal from the signal source through the clock line to the gate drive module becomes longer, resulting in greater signal attenuation. This causes distortion in the clock signal ultimately input to the gate drive module, affecting the scan signal output by the gate drive module and thus impacting the display effect. Summary of the Invention

[0005] This application provides an auxiliary driving circuit and a display panel that can improve the waveform quality of the clock signal, thereby improving the display quality.

[0006] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing an auxiliary driving circuit, the auxiliary driving circuit comprising: a clock driving module connected to a clock line, the clock line being connected to a gate driving module to provide a clock signal to the gate driving module; and a pseudo-gate driving module connected to the clock driving module, the pseudo-gate driving module being configured to output a scan signal; wherein, the clock driving module includes a first pull-up unit and a first pull-down unit, both the first pull-up unit and the first pull-down unit including at least two series-connected switching transistors, the at least two series-connected switching transistors of the first pull-up unit being configured to be turned on in response to a first scan signal output by a pseudo-gate driving module when the clock signal is a rising edge, to pull up the clock signal level, and the at least two series-connected switching transistors of the first pull-down unit being configured to be turned on in response to a second scan signal output by another pseudo-gate driving module when the clock signal is a falling edge, to pull down the clock signal level.

[0007] The first pull-up unit includes a first switch and a second switch. The first terminal of the first switch is configured to input a first drive signal, the second terminal of the first switch is connected to the first terminal of the second switch, the second terminal of the second switch is connected to a clock line, and the control terminals of the first and second switches are configured to input a first scan signal. The first pull-down unit includes a third switch and a fourth switch. The first terminal of the third switch is configured to input a second drive signal, the second terminal of the third switch is connected to the first terminal of the fourth switch, the second terminal of the fourth switch is connected to a clock line, and the control terminals of the third and fourth switches are configured to input a second scan signal.

[0008] The clock drive module further includes: a second pull-down unit, connected to the second end of the first switch transistor and serving as the first node, configured to pull down the level of the first node after the first and second switches transistors are turned off; and a second pull-up unit, connected to the second end of the third switch transistor and serving as the second node, configured to pull up the level of the second node after the third and fourth switches transistors are turned off.

[0009] The second pull-down unit includes a fifth switch transistor, the first end of which and the control end of which are connected to the first node, and the second end of which is configured to input a second drive signal; the second pull-up unit includes a sixth switch transistor, the first end of which and the control end of which are connected and configured to input a first drive signal, and the second end of which is connected to the second node.

[0010] The second pull-down unit includes a seventh switch transistor, the first end of which is connected to the first node, the second end of which is configured to input a second drive signal, and the control end of which is configured to input a second scan signal; the second pull-up unit includes an eighth switch transistor, the first end of which is configured to input a first drive signal, the second end of which is connected to the second node, and the control end of which is configured to input a first scan signal.

[0011] The second pull-down unit further includes a first capacitor, the first end of which is connected to the first node, and the second end of which is configured to input a first drive signal; the second pull-up unit further includes a second capacitor, the first end of which is connected to the second node, and the second end of which is configured to input a second drive signal.

[0012] The system comprises 8 clock drive modules and 8 pseudo-gate drive modules. Each of the 8 clock drive modules is connected to 8 clock lines, with each clock signal having a period of 8h and a rising edge delayed by h. The 8 pseudo-gate drive modules output 8 scan signals, each with a period of 8h, a pulse width of h, and a rising edge delayed by h, with each scan signal's rising edge delayed by h compared to the corresponding clock signal. The first scan signal of the nth clock drive module is the scan signal output by the nth pseudo-gate drive module, and the second scan signal of the nth clock drive module is the scan signal output by the (n+3)th or (n-5)th pseudo-gate drive module. Here, h represents unit time, and n is a positive integer from 1 to 8.

[0013] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide a display panel, the display panel including: scan lines; data lines, arranged in a crisscross pattern with the scan lines; clock lines; a gate driving module, connected to the clock lines and the scan lines; a main driving circuit, connected to the clock lines and the data lines, to provide clock signals to the clock lines and data signals to the data lines; and an auxiliary driving circuit, connected to the clock lines, the auxiliary driving circuit being the auxiliary driving circuit as described above.

[0014] The main drive circuit and the auxiliary drive circuit are respectively located at both ends of the display panel along the extension direction of the data line.

[0015] The clock lines are located at both ends along the scan line direction, and there are two auxiliary drive circuits, which are located at both ends along the scan line direction.

[0016] Unlike existing technologies, the auxiliary driving circuit of this application includes a clock driving module and a pseudo-gate driving module. The clock driving module is connected to a clock line, and the clock line is connected to the gate driving module to provide a clock signal to the gate driving module. The pseudo-gate driving module is connected to the clock driving module and is configured to output a scan signal. The clock driving module includes a first pull-up unit and a first pull-down unit. Both the first pull-up unit and the first pull-down unit include at least two series-connected switches. The at least two series-connected switches of the first pull-up unit are configured to turn on in response to a first scan signal output by a pseudo-gate driving module when the clock signal is rising, so as to pull up the clock signal. The at least two series-connected switches of the first pull-down unit are configured to turn on in response to a second scan signal output by another pseudo-gate driving module when the clock signal is falling, so as to pull down the clock signal. By using the scanning signal output from the pseudo-gate drive module as a control signal, the clock signal level is pulled up at the rising edge of the clock signal, causing the clock signal voltage to rise rapidly to the maximum voltage. Conversely, the clock signal level is pulled down at the falling edge of the clock signal, causing the clock signal voltage to drop rapidly. This enhances the clock signal and makes its waveform closer to the ideal state. Furthermore, by setting at least two series-connected switching transistors in the pull-up and pull-down units, the risk of switching transistor leakage can be reduced, ensuring the waveform quality of the clock signal. This allows the gate drive circuit to perform scanning normally, avoiding problems such as insufficient in-plane charging, incorrect charging, and uneven display caused by gate drive circuit malfunctions. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a schematic diagram of the structure of a display panel in related technologies; Figure 2 This is a waveform diagram of a clock signal in related technologies; Figure 3 This is a schematic diagram of the structure of an embodiment of the display panel provided in this application; Figure 4 This is a schematic diagram of an embodiment of the auxiliary drive circuit provided in this application; Figure 5 This is a schematic diagram of the structure of the first embodiment of the clock driving module; Figure 6 yes Figure 5 The waveform diagrams of the corresponding clock signal and scan signal; Figure 7 This is a schematic diagram of another embodiment of the auxiliary drive circuit provided in this application; Figure 8 yes Figure 7 The waveform diagrams of the corresponding clock signal and scan signal; Figure 9 This is a schematic diagram of the structure of the second embodiment of the clock driving module; Figure 10 This is a schematic diagram of the structure of the third embodiment of the clock driving module; Figure 11 This is a schematic diagram of the structure of the fourth embodiment of the clock driving module; Figure 12 This is a schematic diagram of the structure of the fifth embodiment of the clock driving module; Figure 13 This is a schematic diagram of another embodiment of the display panel provided in this application. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, it should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0019] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that any embodiment described herein can be combined with associated technical features in other embodiments.

[0020] The display principle of liquid crystal displays (LCDs) lies in the deflection of liquid crystals under external control. The deflection state determines the light transmittance, and the different states of each pixel unit combine to create the desired display image. The deflection of the liquid crystal depends on the potential between the pixel electrode and the common electrode in the pixel unit. The potential is determined by the TFT (Thin-Film Transistor) device of the pixel unit as a switch and the data line as a data source.

[0021] The display process for each frame is performed in a line-by-line scanning manner. Each row of pixels has a scan line, which is activated line by line under the action of the scan signal (gate signal), thus completing the activation of each pixel and allowing the target voltage to be input through the data line. The activation of the scan lines is generally given by the GOA (Gate Driver on Array) circuit, which provides the scan signal and performs the function of activating each line.

[0022] See Figure 1 , Figure 1 This is a schematic diagram of the structure of a display panel in related technologies. The display panel includes an active area (AA), a main driving circuit, a gate driving circuit, and a clock line.

[0023] The effective display area includes crisscrossing scan lines and data lines, as well as pixel units in the array defined by the scan lines and data lines. The main driving circuit typically uses COF (Chip On Film) technology, directly mounting the driving circuit chip onto a flexible printed circuit board. The gate driving circuit includes cascaded gate driving modules, which sequentially output scan signals to the scan lines under the sequential drive of multiple clock signals (provided by the main driving circuit via multiple clock lines).

[0024] Under normal circumstances, such as Figure 1 As shown, when a gate driving circuit is set on one side of the effective display area, a clock line is distributed on the corresponding side. When gate driving circuits are set on both opposite sides of the effective display area, clock lines are distributed on both corresponding sides. The length of the clock line is determined by the height of the effective display area. When the display panel size is large, more cascaded gate driving modules are used, and the path of the clock signal from the signal source through the clock line to the gate driving module is also longer.

[0025] Further reading Figure 2 , Figure 2 This is a waveform diagram of a clock signal in related technologies. The solid line represents the clock signal waveform near the main drive circuit on a clock line, while the dashed line represents the clock signal waveform far from the main drive circuit on the same clock line. It can be seen that the farther away from the main drive circuit, the worse the clock signal has Tr (rise time), Tf (fall time), and Vmax (maximum voltage). The deterioration of the clock signal waveform quality will cause instability in the gate drive circuit stage transmission, making it impossible to scan downwards normally, and will also lead to problems such as insufficient charging, incorrect charging, and uneven display in the plane.

[0026] In some embodiments, the clock signal can be increased (by increasing the number of clock lines), the pulse width of the clock signal can be widened, or the width of the clock lines can be increased. However, this can only improve the situation to a certain extent and places higher demands on the bezel of the display panel, the driving circuit, and so on.

[0027] See Figure 3 , Figure 3 This is a schematic diagram of a display panel embodiment provided in this application. The display panel 100 includes an active area (AA) 10, a main driving circuit 20, a gate driving circuit 30, a clock line 40, and an auxiliary driving circuit 50.

[0028] The effective display area 10 includes crisscrossing scan lines (not shown) and data lines (not shown), as well as pixel units (not shown) in the array defined by the scan lines and data lines. The gate driving circuit 30 includes multiple cascaded gate driving modules (not shown), which are connected to the clock line and the scan line. The main driving circuit 20 is connected to the clock line 40 and the data line to provide a clock signal (CLK) to the clock line 40 and a data signal (data) to the data line.

[0029] In this embodiment, the auxiliary drive circuit 50 is connected to the clock line 40 and is used to enhance the clock signal on the clock line 40.

[0030] For details, please refer to [link / reference]. Figure 4 , Figure 4 This is a schematic diagram of an embodiment of the auxiliary driving circuit provided in this application. The auxiliary driving circuit 50 includes a clock driving module 51 and a pseudo-gate driving module 52, wherein the clock driving module 51 is connected to the clock line and the pseudo-gate driving module 52 is connected to the clock driving module 51.

[0031] Understandably, the pseudo-gate drive module 52 has the same structure as the gate drive module cascaded in the gate drive circuit 30, except that the scan signal output by the pseudo-gate drive module 52 is not used to turn on the scan line, but is used to control the clock drive module 51. Specifically, the clock drive module 51 is configured to pull up the clock signal CLK in response to the first scan signal gate1 output by one pseudo-gate drive module 52 when the clock signal CLK is rising, and to pull down the clock signal CLK in response to the second scan signal gate2 output by another pseudo-gate drive module 52 when the clock signal CLK is falling.

[0032] In one embodiment, see Figure 5 , Figure 5This is a schematic diagram of the structure of the first embodiment of the clock driving module. The clock driving module 51 includes a first pull-up unit 511 and a first pull-down unit 512. The input terminal of the first pull-up unit 511 is configured to input a first driving signal VGH (high-level signal), the output terminal of the first pull-up unit 511 is connected to the clock line, and the control terminal of the first pull-up unit 511 is configured to input a first scan signal gate1. The input terminal of the first pull-down unit 512 is configured to input a second driving signal VSS (low-level signal), the output terminal of the first pull-down unit 512 is connected to the clock line, and the control terminal of the first pull-down unit 512 is configured to input a second scan signal gate2.

[0033] Specifically, the first pull-up unit 511 includes a first switch T1 and a second switch T2. The first terminal of the first switch T1 is configured to input a first drive signal VGH. The second terminal of the first switch T1 is connected to the first terminal of the second switch T2. The second terminal of the second switch T2 is connected to a clock line. The control terminals of the first switch T1 and the second switch T2 are configured to input a first scan signal gate1. The first pull-down unit 512 includes a third switch T3 and a fourth switch T4. The first terminal of the third switch T3 is configured to input a second drive signal VSS. The second terminal of the third switch T3 is connected to the first terminal of the fourth switch T4. The second terminal of the fourth switch T4 is connected to a clock line. The control terminals of the third switch T3 and the fourth switch T4 are configured to input a second scan signal gate2.

[0034] Understandably, since the pseudo-gate driving module 52 has the same structure as the gate driving module, it is only necessary to select the scan signals output by two pseudo-gate driving modules 52 corresponding to the rising and falling edges of the clock signal CLK from the multiple pseudo-gate driving modules 52, and use them as the pull-up control signal (first scan signal gate1) and the pull-down control signal (second scan signal gate2) respectively.

[0035] For details, please refer to [link / reference]. Figure 6 , Figure 6 yes Figure 5The waveform diagrams for the corresponding clock and scan signals are shown below. When the clock signal CLK reaches its rising edge, a scan signal that is currently on its rising edge, namely the first scan signal gate1, is selected. The first scan signal gate1 controls the first switch T1 and the second switch T2 to turn on. The first drive signal VGH pulls up the level of the clock signal CLK, causing the potential of the clock signal CLK to quickly reach its maximum voltage Vmax. When the clock signal CLK reaches its falling edge, a scan signal that is currently on its rising edge, namely the second scan signal gate2, is selected. The second scan signal gate2 controls the third switch T3 and the fourth switch T4 to turn on. The second drive signal VSS pulls down the level of the clock signal CLK, causing the potential of the clock signal CLK to quickly reach its minimum potential.

[0036] It is worth noting that in this embodiment, the first pull-up unit 511 uses two series-connected switching transistors (first switching transistor T1 and second switching transistor T2), and the first pull-down unit 512 also uses two series-connected switching transistors (third switching transistor T3 and fourth switching transistor T4). This is to prevent leakage problems that can occur when using a single switching transistor. For example, if the first pull-up unit 511 has only one switching transistor, and this transistor leaks when the clock signal CLK is low, it may pull the clock signal CLK high. Similarly, if the first pull-down unit 512 has only one switching transistor, and this transistor leaks when the clock signal CLK is high, it may pull the clock signal CLK low. Therefore, using two switching transistors in series effectively reduces the risk of leakage. It is understandable that in other embodiments, the number of series-connected switching transistors in the first pull-up unit 511 and the first pull-down unit 512 may be more than two; examples are not given here.

[0037] The following example uses an 8CK display panel. Understandably, the number of clock signals used by the gate driving module in the gate driving circuit 30 varies depending on the panel design, and is generally 2CK, 4CK, 6CK, 8CK, etc. 8CK means that there are a total of 8 clock signals, that is, 8 clock lines. The 8 clock lines can be set on the same side of the effective display area 10, or 4 lines can be set on each side.

[0038] For an 8CK display panel, the clock drive module 51 and the pseudo gate drive module 52 in the auxiliary drive circuit 50 of this embodiment are also set to 8.

[0039] See Figure 7 and Figure 8 , Figure 7 This is a schematic diagram of another embodiment of the auxiliary drive circuit provided in this application. Figure 8 yes Figure 7 The waveform diagrams of the corresponding clock signal and scan signal are shown.

[0040] Among them, the eight clock drive modules 51 are connected to eight clock lines respectively. The period of the eight clock signals (CK1~CK8) corresponding to the eight clock lines is 8h (in actual applications, it is generally slightly less than 8h, where h is a unit time), and the rising edge of the eight clock signals is delayed by h in sequence. The eight pseudo gate drive modules 52 output eight scan signals (GS1~GS8) with a period of 8h, a pulse width of h (in actual applications, it is generally slightly less than h), a rising edge of the eight scan signals being delayed by h in sequence, and the rising edge of each scan signal being delayed by h compared to the rising edge of the corresponding clock signal.

[0041] Understandably, in the above embodiments, when performing auxiliary pull-up and auxiliary pull-down, since the width of the clock signal CLK is not necessarily an integer multiple of h, the auxiliary pull-up can be performed at the rising edge of the clock signal CLK or the auxiliary pull-down at the falling edge of the clock signal CLK; only one of the two can be selected. When the clock signal CLK acts on in-plane scanning, it mainly relies on its falling edge to turn off the pixel TFT and avoid incorrect charging. Therefore, it is necessary to ensure a fast pull-down of its falling edge, thus ensuring the auxiliary driving of the falling edge to a limited extent. Taking the first clock signal CK1 as an example, the falling edge of the first clock signal CK1 is aligned with the rising edge of the scan signal GS4 of the fourth pseudo-gate driving module 52; and the rising edge of the first clock signal CK1 (at time t0) has a certain delay compared to the scan signal GS1 of the first pseudo-gate driving module 52. After the delay, the first clock signal CK1 is continuously pulled up, which provides sufficient driving time for the first clock signal CK1 to reach Vmax. The delay of less than 1h has basically no impact and can still achieve the expected auxiliary driving effect.

[0042] Furthermore, due to the addition of auxiliary pull-up and auxiliary pull-down drivers, the waveform quality of the clock signal CLK is improved (Tr and Tf are reduced), thus reducing the limitation on the selection of the clock signal CLK width. The CK width can be adjusted to an integer multiple of h, further avoiding the misalignment between the auxiliary pull-up and the rising edge of the clock signal CLK.

[0043] Therefore, the first scan signal of the nth clock driving module 51 is the scan signal output by the nth pseudo-gate driving module 52, and the second scan signal of the nth clock driving module 51 is the scan signal output by the (n+3)th (n≤5)th (n-5)th (n>5)th pseudo-gate driving module 52; where n is a positive integer from 1 to 8.

[0044] by Figure 7 and Figure 8Taking the corresponding 8CK module as an example, the gate of the first switch T1 of the first clock drive module 51 is connected to the output terminal of the first pseudo-gate drive module 52, and the gate of the second switch T2 of the first clock drive module 51 is connected to the output terminal of the fourth pseudo-gate drive module 52; the gate of the first switch T1 of the second clock drive module 51 is connected to the output terminal of the second pseudo-gate drive module 52, and the gate of the second switch T2 of the second clock drive module 51 is connected to the output terminal of the fifth pseudo-gate drive module 52; the gate of the first switch T1 of the third clock drive module 51 is connected to the output terminal of the third pseudo-gate drive module 52, and the gate of the second switch T2 of the third clock drive module 51 is connected to the output terminal of the sixth pseudo-gate drive module 52; the gate of the first switch T1 of the fourth clock drive module 51 is connected to the output terminal of the fourth pseudo-gate drive module 52, and the gate of the second switch T2 of the fourth clock drive module 51 is connected to the seventh pseudo-gate drive module 52. The output terminal of the 5th clock drive module 51; the gate of the first switch T1 of the 5th clock drive module 51 is connected to the output terminal of the 5th pseudo-gate drive module 52, and the gate of the second switch T2 of the 5th clock drive module 51 is connected to the output terminal of the 8th pseudo-gate drive module 52; the gate of the first switch T1 of the 6th clock drive module 51 is connected to the output terminal of the 6th pseudo-gate drive module 52, and the gate of the second switch T2 of the 6th clock drive module 51 is connected to the output terminal of the 1st pseudo-gate drive module 52; the gate of the first switch T1 of the 7th clock drive module 51 is connected to the output terminal of the 7th pseudo-gate drive module 52, and the gate of the second switch T2 of the 7th clock drive module 51 is connected to the output terminal of the 2nd pseudo-gate drive module 52; the gate of the first switch T1 of the 8th clock drive module 51 is connected to the output terminal of the 8th pseudo-gate drive module 52, and the gate of the second switch T2 of the 8th clock drive module 51 is connected to the output terminal of the 3rd pseudo-gate drive module 52.

[0045] The auxiliary driving circuit provided in this embodiment includes a clock driving module and a pseudo-gate driving module. The clock driving module is connected to a clock line, and the clock line is connected to the gate driving module to provide a clock signal to the gate driving module. The pseudo-gate driving module is connected to the clock driving module and is configured to output a scan signal. The clock driving module includes a first pull-up unit and a first pull-down unit. Both the first pull-up unit and the first pull-down unit include at least two series-connected switching transistors. The at least two series-connected switching transistors of the first pull-up unit are configured to turn on in response to a first scan signal output by one pseudo-gate driving module when the clock signal is rising, so as to pull up the clock signal. The at least two series-connected switching transistors of the first pull-down unit are configured to turn on in response to a second scan signal output by another pseudo-gate driving module when the clock signal is falling, so as to pull down the clock signal. By using the scanning signal output from the pseudo-gate drive module as a control signal, the clock signal level is pulled up at the rising edge of the clock signal, causing the clock signal voltage to rise rapidly to the maximum voltage. Conversely, the clock signal level is pulled down at the falling edge of the clock signal, causing the clock signal voltage to drop rapidly. This enhances the clock signal and makes its waveform closer to the ideal state. Furthermore, by setting at least two series-connected switching transistors in the pull-up and pull-down units, the risk of switching transistor leakage can be reduced, ensuring the waveform quality of the clock signal. This allows the gate drive circuit to perform scanning normally, avoiding problems such as insufficient in-plane charging, incorrect charging, and uneven display caused by gate drive circuit malfunctions.

[0046] See Figure 9 , Figure 9 This is a schematic diagram of the structure of the second embodiment of the clock driving module. The clock driving module 51 includes a first pull-up unit 511, a first pull-down unit 512, a second pull-down unit 513, and a second pull-up unit 514.

[0047] The first pull-up unit 511 includes a first switch T1 and a second switch T2. The first terminal of the first switch T1 is configured to input a first drive signal VGH. The second terminal of the first switch T1 is connected to the first terminal of the second switch T2. The second terminal of the second switch T2 is connected to a clock line. The control terminals of the first switch T1 and the second switch T2 are configured to input a first scan signal gate1. The first pull-down unit 512 includes a third switch T3 and a fourth switch T4. The first terminal of the third switch T3 is configured to input a second drive signal VSS. The second terminal of the third switch T3 is connected to the first terminal of the fourth switch T4. The second terminal of the fourth switch T4 is connected to a clock line. The control terminals of the third switch T3 and the fourth switch T4 are configured to input a second scan signal gate2.

[0048] The second pull-down unit 513 is connected to the second terminal of the first switch T1 and serves as the first node A. The second pull-down unit 513 is configured to pull down the level of the first node A after the first switch T1 and the second switch T2 are turned off. The second pull-up unit 514 is connected to the second terminal of the third switch T3 and serves as the second node B. The second pull-up unit 514 is configured to pull up the level of the second node B after the third switch T3 and the fourth switch T4 are turned off.

[0049] Understandably, leakage is still possible when multiple switches are connected in series. Specifically, because leakage occurs in the first switch T1 and the second switch T2 when the clock signal CLK is low, causing the low potential of the clock signal CLK to rise, a second pull-down unit 513 is added. This allows the first switch T1 and the second switch T2 to pull down the potential of the first node A during non-operating periods, preventing leakage from the first node A to the clock line through the second switch T2. Similarly, when the clock signal CLK is high, leakage occurs in the third switch T3 and the fourth switch T4, causing the high potential of the clock signal CLK to fall. Therefore, a second pull-up unit 514 is added. This allows the third switch T3 and the fourth switch T4 to pull up the potential of the second node B during non-operating periods, preventing leakage from the clock line to the second node B through the fourth switch T4.

[0050] See Figure 10 , Figure 10 This is a schematic diagram of the structure of the third embodiment of the clock driving module. The clock driving module 51 includes a first pull-up unit 511, a first pull-down unit 512, a second pull-down unit 513, and a second pull-up unit 514.

[0051] The first pull-up unit 511 includes a first switch T1 and a second switch T2. The first terminal of the first switch T1 is configured to input a first drive signal VGH. The second terminal of the first switch T1 is connected to the first terminal of the second switch T2. The second terminal of the second switch T2 is connected to a clock line. The control terminals of the first switch T1 and the second switch T2 are configured to input a first scan signal gate1. The first pull-down unit 512 includes a third switch T3 and a fourth switch T4. The first terminal of the third switch T3 is configured to input a second drive signal VSS. The second terminal of the third switch T3 is connected to the first terminal of the fourth switch T4. The second terminal of the fourth switch T4 is connected to a clock line. The control terminals of the third switch T3 and the fourth switch T4 are configured to input a second scan signal gate2.

[0052] The second pull-down unit 513 includes a fifth switch T5, the first end of the fifth switch T5 and the control end of the fifth switch T5 are connected to the first node A, and the second end of the fifth switch T5 is configured to input a second drive signal VSS; the second pull-up unit 514 includes a sixth switch T6, the first end of the sixth switch T6 and the control end of the sixth switch T6 are connected and configured to input a first drive signal VGH, and the second end of the sixth switch T6 is connected to the second node B.

[0053] Specifically, because leakage current in the first switch T1 and the second switch T2 causes the low potential of the clock signal CLK to rise when CLK is low, a fifth switch T5 is added. This allows the fifth switch T5 to conduct during the off-peak hours of the first and second switches T1 and T2, pulling down the potential of the first node A and preventing leakage from the first node A to the clock line through the second switch T2. Similarly, because leakage current in the third switch T3 and the fourth switch T4 causes the high potential of the clock signal CLK to fall when CLK is high, a sixth switch T6 is added. This allows the sixth switch T6 to conduct during the off-peak hours of the third and fourth switches T3 and T4, pulling up the potential of the second node B and preventing leakage from the clock line to the second node B through the fourth switch T4.

[0054] See Figure 11 , Figure 11 This is a schematic diagram of the structure of the fourth embodiment of the clock driving module. The clock driving module 51 includes a first pull-up unit 511, a first pull-down unit 512, a second pull-down unit 513, and a second pull-up unit 514.

[0055] The first pull-up unit 511 includes a first switch T1 and a second switch T2. The first terminal of the first switch T1 is configured to input a first drive signal VGH. The second terminal of the first switch T1 is connected to the first terminal of the second switch T2. The second terminal of the second switch T2 is connected to a clock line. The control terminals of the first switch T1 and the second switch T2 are configured to input a first scan signal gate1. The first pull-down unit 512 includes a third switch T3 and a fourth switch T4. The first terminal of the third switch T3 is configured to input a second drive signal VSS. The second terminal of the third switch T3 is connected to the first terminal of the fourth switch T4. The second terminal of the fourth switch T4 is connected to a clock line. The control terminals of the third switch T3 and the fourth switch T4 are configured to input a second scan signal gate2.

[0056] The second pull-down unit 513 includes a seventh switch T7, the first end of which is connected to the first node A, the second end of which is configured to input a second drive signal VSS, and the control end of which is configured to input a second scan signal gate2; the second pull-up unit 514 includes an eighth switch T8, the first end of which is configured to input a first drive signal VGH, the second end of which is connected to the second node B, and the control end of which is configured to input a first scan signal gate1.

[0057] Specifically, he, in conjunction with the above Figure 8 In this embodiment, taking GS1 as the first scan signal gate1 and GS4 as the second scan signal gate2 as an example, when the clock signal CLK is low, to prevent leakage of the first switch T1 and the second switch T2, GS4 will turn on the seventh switch T7 to pull the potential of the first node A low to VSS when the first pull-down unit 512 performs auxiliary pull-down, thus preventing the second switch T2 from pulling the clock signal CLK high due to leakage. Similarly, when the clock signal CLK is high, to prevent leakage of the third switch T3 and the fourth switch T4, GS1 will turn on the eighth switch T8 to pull the potential of the second node B high to VGH when the first pull-up unit 511 performs auxiliary pull-up, thus preventing the fourth switch T4 from pulling the clock signal CLK low due to leakage.

[0058] See Figure 12 , Figure 12 This is a schematic diagram of the structure of the fifth embodiment of the clock driving module. The clock driving module 51 includes a first pull-up unit 511, a first pull-down unit 512, a second pull-down unit 513, and a second pull-up unit 514.

[0059] The first pull-up unit 511 includes a first switch T1 and a second switch T2. The first terminal of the first switch T1 is configured to input a first drive signal VGH. The second terminal of the first switch T1 is connected to the first terminal of the second switch T2. The second terminal of the second switch T2 is connected to a clock line. The control terminals of the first switch T1 and the second switch T2 are configured to input a first scan signal gate1. The first pull-down unit 512 includes a third switch T3 and a fourth switch T4. The first terminal of the third switch T3 is configured to input a second drive signal VSS. The second terminal of the third switch T3 is connected to the first terminal of the fourth switch T4. The second terminal of the fourth switch T4 is connected to a clock line. The control terminals of the third switch T3 and the fourth switch T4 are configured to input a second scan signal gate2.

[0060] The second pull-down unit 513 includes a seventh switch T7, the first end of which is connected to the first node A, the second end of which is configured to input a second drive signal VSS, and the control end of which is configured to input a second scan signal gate2; the second pull-up unit 514 includes an eighth switch T8, the first end of which is configured to input a first drive signal VGH, the second end of which is connected to the second node B, and the control end of which is configured to input a first scan signal gate1.

[0061] The second pull-down unit 513 further includes a first capacitor C1, the first end of which is connected to the first node A, and the second end of which is configured to input the first driving signal VGH; the second pull-up unit 514 further includes a second capacitor C2, the first end of which is connected to the second node B, and the second end of which is configured to input the second driving signal VSS.

[0062] Specifically, he, in conjunction with the above Figure 8 In this embodiment, taking GS1 as the first scan signal gate1 and GS4 as the second scan signal gate2 as an example, when the clock signal CLK is low, to prevent leakage of the first switch T1 and the second switch T2, when the first pull-down unit 512 performs auxiliary pull-down, GS4 turns on the seventh switch T7 to pull the potential of the first node A low to VSS, which is maintained by the first capacitor C1, preventing the second switch T2 from pulling the clock signal CLK high due to leakage. Similarly, when the clock signal CLK is high, to prevent leakage of the third switch T3 and the fourth switch T4, when the first pull-up unit 511 performs auxiliary pull-up, GS1 turns on the eighth switch T8 to pull the potential of the second node B high to VGH, which is maintained by the second capacitor C2, preventing the fourth switch T4 from pulling the clock signal CLK low due to leakage.

[0063] Understandably, the aforementioned auxiliary driver strengthens the clock signal CLK, thus reducing the trace width of the clock lines. Furthermore, the increased number of clock lines (the number of clock signals) aims to widen the pulse width of the clock signal to improve its quality and transmission stability. Therefore, the addition of the auxiliary driver unit reduces the number of clock lines. Additionally, the dummy gate driver module 52 has a relatively small driving load, requiring only 2CK lines for driving, and its trace width requirement is small. Therefore, despite the addition of the clock driver module 51 and the dummy gate driver module 52, the required frame width is very small, resulting in a significant advantage in reducing frame width.

[0064] See again Figure 3In one embodiment, the main driving circuit 20 and the auxiliary driving circuit 50 are respectively disposed at both ends of the display panel along the data line extension direction. Understandably, since there is ample space on the opposite side of the main driving circuit 20, the clock driving module 51 and the dummy gate driving module 52 in the above embodiment can be arranged on the opposite side of the main driving circuit 20 without occupying other effective areas. Furthermore, the auxiliary driving of the clock signal waveform on the clock line on the opposite side of the main driving circuit 20 reduces the waveform difference between the clock signal on one side of the main driving circuit 20 and the opposite side, improving display uniformity.

[0065] See Figure 13 , Figure 13 This is a schematic diagram of another embodiment of the display panel provided in this application, which is different from... Figure 3 In this embodiment, two auxiliary driving circuits 50 may be provided, and the two auxiliary driving circuits 50 are respectively provided at both ends along the scan line direction.

[0066] In some embodiments, clock lines are positioned on both sides of the effective display area 10. To avoid increasing the trace length between the auxiliary drive circuit 50 and the clock lines, which could affect the waveform, in this embodiment, two auxiliary drive circuits 50 are respectively positioned corresponding to the clock lines on both sides, and remain opposite to the main drive circuit 20. This avoids the problem of clock signal waveform distortion caused by additional traces, further improving the waveform quality of the clock signal and thus enhancing the quality of the displayed image.

[0067] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0068] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0069] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0070] If the integrated units in the other embodiments described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0071] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made based on the description and drawings of this application, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An auxiliary driving circuit, characterized in that, The auxiliary drive circuit includes: A clock driving module is connected to a clock line, which is connected to a gate driving module to provide a clock signal to the gate driving module. A pseudo-gate driving module is connected to the clock driving module, and the pseudo-gate driving module is configured to output a scan signal. The clock driving module includes a first pull-up unit and a first pull-down unit. Both the first pull-up unit and the first pull-down unit include at least two series-connected switching transistors. The at least two series-connected switching transistors of the first pull-up unit are configured to turn on in response to a first scan signal output by one of the pseudo-gate driving modules when the clock signal is a rising edge, so as to pull up the clock signal. The at least two series-connected switching transistors of the first pull-down unit are configured to turn on in response to a second scan signal output by another pseudo-gate driving module when the clock signal is a falling edge, so as to pull down the clock signal.

2. The auxiliary drive circuit according to claim 1, characterized in that, The first pull-up unit includes a first switch and a second switch. The first terminal of the first switch is configured to input a first drive signal. The second terminal of the first switch is connected to the first terminal of the second switch. The second terminal of the second switch is connected to the clock line. The control terminals of the first switch and the second switch are configured to input the first scan signal. The first pull-down unit includes a third switch and a fourth switch. The first terminal of the third switch is configured to input a second drive signal. The second terminal of the third switch is connected to the first terminal of the fourth switch. The second terminal of the fourth switch is connected to the clock line. The control terminals of the third switch and the fourth switch are configured to input the second scan signal.

3. The auxiliary drive circuit according to claim 2, characterized in that, The clock driving module also includes: The second pull-down unit is connected to the second terminal of the first switch transistor and serves as the first node. The second pull-down unit is configured to pull down the level of the first node after the first switch transistor and the second switch transistor are turned off. The second pull-up unit is connected to the second terminal of the third switch and serves as the second node. The second pull-up unit is configured to pull up the level of the second node after the third switch and the fourth switch are turned off.

4. The auxiliary drive circuit according to claim 3, characterized in that, The second pull-down unit includes a fifth switch transistor, the first end of the fifth switch transistor and the control end of the fifth switch transistor are connected to the first node, and the second end of the fifth switch transistor is configured to input the second drive signal; The second pull-up unit includes a sixth switch transistor, the first end of which is connected to the control end of the sixth switch transistor and configured to input the first drive signal, and the second end of the sixth switch transistor is connected to the second node.

5. The auxiliary drive circuit according to claim 3, characterized in that, The second pull-down unit includes a seventh switch transistor, the first end of which is connected to the first node, the second end of which is configured to input the second drive signal, and the control end of which is configured to input the second scan signal. The second pull-up unit includes an eighth switch transistor, the first end of which is configured to input the first drive signal, the second end of which is connected to the second node, and the control end of which is configured to input the first scan signal.

6. The auxiliary driving circuit according to claim 5, characterized in that, The second pull-down unit further includes a first capacitor, a first end of which is connected to the first node, and a second end of which is configured to input the first drive signal. The second pull-up unit further includes a second capacitor, the first end of which is connected to the second node, and the second end of which is configured to input the second drive signal.

7. The auxiliary drive circuit according to any one of claims 1-6, characterized in that, The number of clock driving modules and the number of pseudo gate driving modules are both 8; The eight clock driving modules are connected to eight clock lines respectively. The eight clock signals corresponding to the eight clock lines have a period of 8h, and the rising edges of the eight clock signals are delayed by h in sequence. Among them, the period of the eight scan signals output by the eight pseudo-gate driving modules is 8h, the pulse width of the eight scan signals is h, the rising edge of the eight scan signals is delayed by h in sequence, and the rising edge of each scan signal is delayed by h compared with the rising edge of the corresponding clock signal. Wherein, the first scan signal of the nth clock driving module is the scan signal output by the nth pseudo-gate driving module, and the second scan signal of the nth clock driving module is the scan signal output by the (n+3)th or (n-5)th pseudo-gate driving module; Where h is the unit time and n is a positive integer from 1 to 8.

8. A display panel, characterized in that, The display panel includes: Scan lines; The data lines are arranged in a crisscross pattern with the scan lines; Clock line; A gate driving module, which connects the clock line and the scan line; The main drive circuit connects the clock line and the data line to provide a clock signal to the clock line and a data signal to the data line. An auxiliary driving circuit is connected to the clock line, wherein the auxiliary driving circuit is the auxiliary driving circuit according to any one of claims 1-7.

9. The display panel according to claim 8, characterized in that, The main driving circuit and the auxiliary driving circuit are respectively located at both ends of the display panel along the extension direction of the data line.

10. The display panel according to claim 9, characterized in that, The clock lines are respectively located at both ends along the direction of the scan line, and there are two auxiliary driving circuits, which are respectively located at both ends along the direction of the scan line.

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