A chip select signal calibration circuit and memory

Abstract

This disclosure provides a chip select signal calibration circuit and a memory. The chip select signal calibration circuit includes: a frequency divider enable circuit, used to generate an enabled clock enable signal when a chip select signal is received; a clock frequency divider circuit, connected to the frequency divider enable circuit, used to receive the clock enable signal and a preset clock signal, and when the clock enable signal is enabled, to perform frequency division processing on the preset clock signal to generate a frequency-divided clock signal, the clock period of the frequency-divided clock signal being consistent with the clock period of the chip select signal; and a chip select counter circuit, connected to the clock frequency divider circuit, used to receive the frequency-divided clock signal and the chip select signal, and to generate a count value by counting the level state of the chip select signal using the flip edge of the frequency-divided clock signal. This disclosure reduces circuit complexity and ensures accurate counting.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a chip select signal calibration circuit and a memory. Background Technology

[0002] Before the Dynamic Random Access Memory (DRAM) can function properly, the System on Chip (SoC) needs to calibrate the phase relationship between the chip select signal and the clock signal to ensure that the chip select signal can be correctly sampled after the clock signal reaches the DRAM.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] This disclosure provides a chip select signal calibration circuit and a memory.

[0005] In a first aspect, embodiments of this disclosure provide a chip select signal calibration circuit, including:

[0006] The frequency divider enable circuit is used to generate a clock enable signal for the enable state when a chip select signal is received.

[0007] A clock divider circuit, connected to the divider enable circuit, is used to receive the clock enable signal and a preset clock signal. When the clock enable signal is enabled, the preset clock signal is divided to generate a divided clock signal. The clock period of the divided clock signal is the same as the clock period of the chip select signal.

[0008] The chip select counting circuit, connected to the clock divider circuit, is used to receive the divided clock signal and the chip select signal, and to count the level state of the chip select signal by the flip edge of the divided clock signal to generate a count value.

[0009] Secondly, embodiments of this disclosure provide a memory including the chip select signal calibration circuit described in the first aspect.

[0010] This disclosure provides a chip select signal calibration circuit and a memory. On the one hand, by using an internal clock divider circuit to divide an externally provided high-frequency preset clock signal into a low-frequency divided clock signal for counting the chip select signal, not only is the circuit complexity reduced, but the circuit can also work normally at high frequencies. On the other hand, an enable clock signal is generated only when the chip select signal is received to enable the clock divider circuit to perform frequency division, so that the flip edge of the divided clock signal can correspond to the level state of the chip select signal. That is, the flip edge can always successfully sample the level state, avoiding the problem of inaccurate counting due to the uncertain sampling relationship caused by the mismatch between the positional relationship of the divided clock signal and the chip select signal. At the same time, it can also avoid the extra power consumption caused by the divided clock signal constantly flipping before counting is required. Attached Figure Description

[0011] Figure 1 A signal timing diagram provided for an embodiment of this disclosure Figure 1 ;

[0012] Figure 2 A signal timing diagram provided for an embodiment of this disclosure Figure 2 ;

[0013] Figure 3 A signal timing diagram provided for an embodiment of this disclosure Figure 3 ;

[0014] Figure 4 A schematic diagram of the composition structure of a chip select signal calibration circuit provided in this embodiment of the present disclosure. Figure 1 ;

[0015] Figure 5 A schematic diagram of the composition structure of a chip select signal calibration circuit provided in this embodiment of the present disclosure. Figure 2 ;

[0016] Figure 6 A schematic diagram of the composition structure of a chip select signal calibration circuit provided in this embodiment of the present disclosure. Figure 3 ;

[0017] Figure 7 A signal timing diagram provided for an embodiment of this disclosure Figure 4 ;

[0018] Figure 8 A signal timing diagram provided for an embodiment of this disclosure Figure 5 ;

[0019] Figure 9 A signal timing diagram provided for an embodiment of this disclosure Figure 6 ;

[0020] Figure 10 A schematic diagram of a chip select counting circuit provided in this embodiment of the present disclosure. Figure 1 ;

[0021] Figure 11 A schematic diagram of a chip select counting circuit provided in this embodiment of the present disclosure. Figure 2 ;

[0022] Figure 12 A schematic diagram of a chip select counting circuit provided in this embodiment of the present disclosure. Figure 3 ;

[0023] Figure 13 A schematic diagram of a chip select counting circuit provided in this embodiment of the present disclosure. Figure 4 . Detailed Implementation

[0024] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining the relevant applications and are not intended to limit the scope of this disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the relevant applications are shown in the accompanying drawings.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0026] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0027] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0028] Before providing a further detailed description of the embodiments of this disclosure, the nouns and terms used in the embodiments of this disclosure will be explained. The nouns and terms used in the embodiments of this disclosure shall be interpreted as follows:

[0029] Dynamic Random Access Memory (DRAM);

[0030] System on Chip (SoC);

[0031] Double Data Rate (DDR);

[0032] Low-power DDR (LPDDR);

[0033] Chip Select (Cs);

[0034] D-flip-flop (or delayflip-flop, DFF).

[0035] Before the DRAM can operate normally, the SoC needs to calibrate the phase relationship between the chip select signal and the clock signal to ensure that the chip select signal can be correctly sampled after the clock signal reaches the DRAM. For example, in LPDDR6, the relevant timing of the standard chip select signal calibration method is as follows: Figure 1 As shown, CK_t and CK_c are a pair of inverted system clock signals, Cs is the chip select signal, CA is the command address signal, CMD is the command signal, WCK_t and WCK_c are a pair of inverted write clock signals, DQ

[11] is the signal of data pin

[11] , DQ

[10] is the signal of data pin

[10] , DQ[9] is the signal of data pin[9], and DQ[7:0] is the signal of data pin[0] to data pin[7].

[0036] like Figure 1 As shown, the SoC first enters the chip select signal calibration mode by writing to the specified register in the DRAM, and then pulls the DQ

[11] pin of the DRAM high. At this time, the DRAM switches to high frequency working mode. Then, the reference voltage of the chip select signal is set by DQ[7:0], and then the calibration circuit inside the DRAM is reset by DQ[9]. Finally, 16 consecutive chip select signals are sent ( Figure 1 As shown in ①), the DRAM internally samples and counts the high and low levels of the chip select signal according to the system clock signal. If 16 high and low levels can be sampled, the calibration is successful; otherwise, the calibration fails and the phase relationship between the chip select signal and the clock signal needs to be adjusted before continuing the calibration operation.

[0037] LPDDR6 specifies a maximum operating frequency of 3.6GHz, with a clock period of 278ps. Directly using this high-speed clock to design calibration circuits would significantly increase the complexity of the circuit design. Therefore, this disclosure provides a solution: frequency division of the input clock signal (such as the system clock signal), greatly reducing the design complexity. However, since the positional relationship between the input clock signal and the chip select signal is random, the sampling relationship between the frequency-divided clock signal and the chip select signal is not fixed; the high level of the chip select signal may appear at the rising or falling edge of the frequency-divided clock signal.

[0038] For example Figure 2 As shown, Clk represents the clock signal, Cs represents the chip select signal, Divide_Ck represents the clock signal obtained by frequency division, denoted as the first clock signal, CsH_Cnt represents the count value of the high level of the chip select signal (denoted as the high-level count value), and CsL_Cnt represents the count value of the low level of the chip select signal (denoted as the low-level count value). The high level of the chip select signal Cs occurs at the rising edge of the first clock signal Divide_Ck, and the low level of the chip select signal Cs occurs at the falling edge of the first clock signal Divide_Ck. Therefore, the high-level count value CsH_Cnt of the chip select signal Cs is obtained from the rising edge of the first clock signal Divide_Ck, and the low-level count value CsL_Cnt of the chip select signal Cs is obtained from the falling edge of the first clock signal Divide_Ck.

[0039] For example Figure 3 As shown, the high level of the chip select signal Cs occurs at the falling edge of the first clock signal Divide_Ck, and the low level of the chip select signal Cs occurs at the rising edge of the first clock signal Divide_Ck. Therefore, the high-level count value CsH_Cnt of the chip select signal Cs is obtained from the falling edge of the first clock signal Divide_Ck, and the low-level count value CsL_Cnt of the chip select signal Cs is obtained from the rising edge of the first clock signal Divide_Ck.

[0040] Based on this, the present disclosure further proposes a chip select signal calibration circuit, which includes: a frequency divider enable circuit, used to generate an enabled clock enable signal when a chip select signal is received; a clock frequency divider circuit, connected to the frequency divider enable circuit, used to receive the clock enable signal and a preset clock signal, and when the clock enable signal is in the enabled state, to perform frequency division processing on the preset clock signal to generate a frequency divider clock signal, the clock period of the frequency divider clock signal being consistent with the clock period of the chip select signal; and a chip select counter circuit, connected to the clock frequency divider circuit, used to receive the frequency divider clock signal and the chip select signal, and to count the level state of the chip select signal by using the flip edge of the frequency divider clock signal to generate a count value.

[0041] In this way, on the one hand, by using an internal clock divider circuit to divide the externally provided high-frequency preset clock signal into a low-level divided clock signal for counting the chip select signal, not only is the complexity of the circuit reduced, but the circuit can also work normally at high frequencies. On the other hand, only when the chip select signal is confirmed to be received is an enable clock signal generated to enable the clock divider circuit to perform frequency division. This ensures that the flipping edge in the divided clock signal corresponds to the level state of the chip select signal, that is, the flipping edge can always successfully sample the level state. This avoids the problem of inaccurate counting due to the uncertain sampling relationship caused by the mismatch between the positional relationship of the divided clock signal and the chip select signal. At the same time, it can also avoid the extra power consumption caused by the divided clock signal constantly flipping before counting is required.

[0042] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0043] In one embodiment of this disclosure, see [link to embodiment]. Figure 4 This illustrates a schematic diagram of the composition of a chip select signal calibration circuit 10 provided in an embodiment of this disclosure. Figure 4 As shown, the chip select signal calibration circuit 10 includes:

[0044] The frequency divider enable circuit 20 is used to generate a clock enable signal in the enable state when a chip select signal is received.

[0045] The clock divider circuit 30 is connected to the divider enable circuit 20 and is used to receive the clock enable signal and the preset clock signal. When the clock enable signal is enabled, the preset clock signal is divided to generate a divided clock signal. The clock period of the divided clock signal is the same as the clock period of the chip select signal.

[0046] The chip select counting circuit 40 is connected to the clock divider circuit 30. It is used to receive the divided clock signal and the chip select signal, and to generate a count value by counting the level state of the chip select signal using the flip edge of the divided clock signal.

[0047] It should be noted that, typically, the chip select signal is active low during operation. The chip select signal calibration circuit 10 in this embodiment performs the training process for chip select signal calibration as specified in the standard (SPEC). The received chip select signal is a test pattern sent by the host or test equipment. During training, it first enters test mode, then configures relevant parameters and circuits, and then performs test training. This embodiment does not show the relevant mode entry circuit, configuration circuit, etc., in detail. In test mode, the chip select signal under test exhibits periodic alternation between high and low levels. Here, the period of alternation between high and low levels of the chip select signal (also called the clock period) is the same as the clock period of the frequency divider clock signal to achieve smooth sampling.

[0048] It should also be noted that the preset clock signal can be the high-frequency clock signal of the system, which is divided to obtain a low-frequency divided clock signal. In this embodiment, the frequency of the chip select signal can be half of the preset clock signal. Therefore, the frequency of the divided clock signal can be made half of the preset clock signal by the frequency division process, so that the frequency of the divided clock signal is the same as the frequency of the chip select signal.

[0049] Here, you can refer to Figure 2 or Figure 3 As shown, during test calibration, the chip select signal Cs initially remains low for an extended period (during which the state of the chip select signal Cs can be considered the default state). After the circuit completes the relevant configuration and settings, the chip select signal Cs is pulled high, exhibiting a regular alternation between high and low levels. That is, after the state of the chip select signal Cs flips from the default state, it enters the period requiring counting. In this embodiment, for the frequency divider enable circuit 20, when the chip select signal Cs flips from the long-term static default state to another state, it is considered that the chip select signal Cs has been received, and a clock enable signal for the enabled state is generated. It can be understood that in... Figure 2 and Figure 3 In the example, the default state is low and the toggled state is high; in other examples, the default state can also be high and the toggled state can be low, without any specific limitation.

[0050] In this embodiment of the disclosure, the level state of the chip select signal may include a first level state and a second level state, wherein one of the first level state and the second level state is a high level state and the other is a low level state, that is, the two are inverses of each other; the flip edge of the frequency divider clock signal may include a first flip edge and a second flip edge, wherein one of the first flip edge and the second flip edge is a rising edge and the other is a falling edge; the count value may include a first count value and a second count value, wherein the first count value is the count value obtained by counting the first level state and the second count value is the count value obtained by counting the second level state.

[0051] The chip select counting circuit 40 can be used to receive a frequency-divided clock signal and a chip select signal, and generate a count value by counting the level state of the chip select signal using the flip edge of the frequency-divided clock signal. In some embodiments, the chip select counting circuit 40 can use the first flip edge of the frequency-divided clock signal to count the first level state of the chip select signal to obtain a first count value; the chip select counting circuit 40 can also use the second flip edge of the frequency-divided clock signal to count the second level state of the chip select signal to obtain a second count value.

[0052] It should be noted that when counting the first level state of the chip select signal using the first flip edge of the frequency divider clock signal, if the chip select signal is in the first level state at the flip edge of the frequency divider clock signal, meaning the first level state of the chip select signal can be successfully sampled using the first flip edge of the frequency divider clock signal, then the first level state is successfully counted once, and the first count value is incremented by 1. Otherwise, if the chip select signal is in the second level state, meaning the first level state is not successfully counted, the first count value remains unchanged. Similarly, when counting the second level state of the chip select signal using the second flip edge of the frequency divider clock signal, if the chip select signal is in the second level state at the second flip edge of the frequency divider clock signal, meaning the second level state of the chip select signal can be successfully sampled using the second flip edge of the frequency divider clock signal, then the second level state is successfully counted once, and the second count value is incremented by 1. Otherwise, if the chip select signal is in the first level state, meaning the second level state is not successfully counted, the second count value remains unchanged.

[0053] In this way, by using a frequency-divided clock signal to sample the chip select signal, the frequency of the divided clock signal is lower than the original preset clock signal. This not only reduces the complexity of the circuit design but also ensures that the circuit can operate normally at high frequencies. Simultaneously, the frequency divider enable circuit 20 only generates an enabled clock enable signal when it confirms the receipt of the chip select signal Cs. This enables the clock frequency divider circuit 30 to divide the preset clock signal into a divided clock signal. On the one hand, this avoids the power consumption caused by the frequency divider clock signal constantly toggling when counting is not required. On the other hand, since frequency division only occurs after the chip select signal arrives, a proper design of the clock frequency divider circuit 30 is sufficient to ensure that the toggle edge of the divided clock signal is always aligned with the level state of the chip select signal (i.e., the level state after toggling from the default state). This ensures successful sampling of the level state and avoids counting errors caused by the mismatch between the toggle edge of the divided clock signal and the level state of the chip select signal.

[0054] In some embodiments, such as Figure 5 As shown, the chip select signal calibration circuit 10 also includes a frequency divider counting circuit 50;

[0055] The frequency divider counting circuit 50 is connected to the clock frequency divider circuit 30. It is used to receive the frequency divider clock signal, count based on the frequency divider clock signal, and generate an end count value. When the end count value reaches a preset value, it generates an enabled frequency divider end signal. In other cases, it generates an disabled frequency divider end signal.

[0056] The frequency divider enable circuit 20 is also used to receive the frequency divider end signal and generate a clock enable signal in the disabled state when the frequency divider end signal is in the enabled state.

[0057] In this embodiment, the preset value can be the number of first level states in the chip select signal when there is no abnormality in the chip select signal.

[0058] It should be noted that once the chip select signal periodically alternates between high and low levels and returns to the default state, counting is no longer required. Therefore, the clock divider circuit 30 can be turned off, preventing the divided clock signal from toggling and saving power. Assuming the preset value is 16 and the first toggle edge of the divided clock signal is the first toggle edge, the divider counter circuit 50 can count based on the divided clock signal. Specifically, it can increment the count value by 1 at each first toggle edge of the divided clock signal. When the final count value reaches 16, the preset value is reached, and the chip select counter circuit 40 no longer needs to count. At this point, the divider counter circuit 50 generates an enabled divider end signal. Under the control of the enabled divider end signal, the divider enable circuit 20 generates a disabled clock enable signal, thereby controlling the clock divider circuit 30 to end the divider, the divided clock signal no longer toggles, and the chip select counter circuit 40 stops counting.

[0059] This ensures that the frequency divider clock signal does not flip after the chip select counter circuit 40 has completed the required counting work, saving power consumption; at the same time, it also avoids counting errors in the chip select counter circuit 40.

[0060] In some embodiments, such as Figure 6 As shown, the frequency divider enable circuit 20 can be an RS latch. The first input terminal of the RS latch receives the chip select signal Cs, the second input terminal of the RS latch receives the frequency divider end signal ClkEnd, and the output terminal of the RS latch outputs the clock enable signal ClkEn.

[0061] It should be noted that, taking the clock enable signal ClkEn as an example where the enable state is high and the disable state is low, in this embodiment of the disclosure, the first input terminal of the RS latch is its set terminal (S terminal), and the second input terminal is its reset terminal (R terminal).

[0062] Specifically, an RS latch can consist of two NOR gates, such as... Figure 6 As shown, the RS latch includes a first NOR gate nor1 and a second NOR gate nor2, wherein:

[0063] The first input of the first NOR gate NOR1 serves as the first input of the frequency divider enable circuit 20, used to receive the chip select signal Cs; the second input of the first NOR gate NOR1 is connected to the output of the second NOR gate NOR2; the first input of the second NOR gate NOR2 serves as the second input of the frequency divider enable circuit 20, connected to the output of the frequency divider counter circuit 50, used to receive the frequency division end signal ClkEnd; the second input of the second NOR gate NOR2 is connected to the output of the first NOR gate NOR1; the output of the second NOR gate NOR2 serves as the output of the frequency divider enable circuit 20, used to output the clock enable signal ClkEn.

[0064] Thus, this embodiment of the present disclosure uses an RS latch to control the state of the clock enable signal ClkEn, thereby enabling the clock divider circuit 30 to be turned on when needed and turned off when not needed, making the circuit implementation relatively simple.

[0065] It should also be noted that, Figure 6 The specific structure of the frequency divider enable circuit 20 shown is only an example and is not limited thereto.

[0066] The frequency-divided clock signal can be a single clock signal or it can include two clock signals. In some embodiments, such as... Figure 6 As shown, the frequency-divided clock signal includes a first frequency-divided clock signal Div_Clk and a second frequency-divided clock signal Div_ClkN, and the first frequency-divided clock signal Div_Clk and the second frequency-divided clock signal Div_ClkN are inverses of each other;

[0067] The chip select counting circuit 40 is used to receive the first divided clock signal Div_Clk, the second divided clock signal Div_ClkN, and the chip select signal Cs. It uses the flip edge of the first divided clock signal Div_Clk or the second divided clock signal Div_ClkN to count the first level state of the chip select signal Cs to generate a first count value CNtH; and uses the flip edge of the first divided clock signal Div_Clk or the second divided clock signal Div_ClkN to count the second level state of the chip select signal Cs to generate a second count value CNtL.

[0068] In some implementations, the flip edge may include a rising edge and a falling edge, for example, using the rising edge of the first divided clock signal Div_Clk to count the first level state of the chip select signal Cs, and using the falling edge of the first divided clock signal Div_Clk to count the second level state of the chip select signal Cs.

[0069] In other implementations, the flip edges can all be rising edges. For example, the rising edge of the first divided clock signal Div_Clk is used to count the first level state of the chip select signal Cs, and the rising edge of the second divided clock signal Div_ClkN is used to count the second level state of the chip select signal Cs.

[0070] It should be noted that when the frequency division clock signal includes the first frequency division clock signal Div_Clk and the second frequency division clock signal Div_ClkN, the frequency division counting circuit 50 can receive the first frequency division clock signal Div_Clk or the second frequency division clock signal Div_ClkN, and perform counting based on the first frequency division clock signal Div_Clk or the second frequency division clock signal Div_ClkN to generate an end count value.

[0071] like Figure 6 As shown, the clock divider circuit 30 may include:

[0072] The first logic circuit 301 is used to receive the clock enable signal ClkEn and the second frequency divider clock signal Div_ClkN; when the clock enable signal ClkEn is enabled, the second frequency divider clock signal Div_ClkN is output as a sampling input signal.

[0073] The sampling circuit 302 is electrically connected to the first logic circuit 301 and is used to receive the sampling input signal and the preset clock signal Clk, sample the sampling input signal based on the preset clock signal Clk, and output the first frequency divided clock signal Div_Clk and the second frequency divided clock signal Div_ClkN respectively.

[0074] It should be noted that when the clock enable signal ClkEn is enabled, the clock divider circuit 30 performs a frequency division operation, dividing the preset clock signal Clk into a first divided clock signal Div_Clk and a second divided clock signal Div_ClkN. Specifically, the second divided clock signal Div_ClkN can be used as the input signal of the sampling circuit 302, and the signal can be sampled based on the preset clock signal Clk to achieve frequency division.

[0075] Specifically, such as Figure 6 As shown, the first logic circuit 301 includes a first AND gate AND1, and the sampling circuit 302 includes a first flip-flop D1;

[0076] The first input of the first AND gate AND1 receives the second divided clock signal Div_ClkN, and the second input of the first AND gate AND1 receives the clock enable signal ClkEn.

[0077] The output of the first AND gate AND1 is connected to the input of the first flip-flop D1 to output the sampled input signal;

[0078] The clock terminal of the first flip-flop D1 receives the preset clock signal Clk, the first output terminal of the first flip-flop D1 outputs the first divided clock signal Div_Clk, and the second output terminal of the first flip-flop D1 outputs the second divided clock signal Div_ClkN.

[0079] It should be noted that the first flip-flop D1 can specifically be a DFF. Its input is the D terminal, the clock terminal is the CK terminal, and it includes the Q terminal and... It has two output terminals. Figure 6 In the example, Q is used as the first output terminal. The Q terminal serves as the second output terminal, and the signal output from the Q terminal serves as the first frequency-divided clock signal, Div_Clk. The output signal serves as the second divided clock signal, Div_ClkN. In other examples, it could also be: The Q terminal is used as the first output terminal, and the Q terminal is used as the second output terminal. The signal output from the Q terminal is used as the first frequency divider clock signal, and the signal output from the Q terminal is used as the second frequency divider clock signal; no specific restrictions are made on this.

[0080] It should also be noted that, such as Figure 6 As shown, the first flip-flop D1 may also include a reset terminal for receiving a reset signal rst and resetting the output signal based on the reset signal rst.

[0081] Thus, the clock divider circuit 30 can be implemented using a simple combination of AND gates and flip-flops in this embodiment of the present disclosure. The circuit structure is simple and easy to implement.

[0082] In some embodiments, the chip select signal calibration circuit 10 may also be connected to a control circuit (not shown in the figures); the control circuit is used to receive a first count value CNtH and a second count value CNtL, and after the chip select counting circuit 10 stops counting, it determines whether the first count value CNtH and the second count value CNtL are both preset values; if so, it determines that the calibration is successful, otherwise, it determines that the calibration has failed.

[0083] It should be noted that the preset value can be, for example, 16 as mentioned above, and the control circuit can be the host or the test machine, etc.

[0084] It should also be noted that the frequency division counting circuit 50 can also send the frequency division end signal ClkEnd to the control circuit. When the control circuit receives the frequency division end signal ClkEnd in the enabled state, it determines whether the first count value CNtH and the second count value CNtL are both preset values.

[0085] based on Figure 6The principle of the chip select signal calibration circuit 10 provided in this embodiment of the application is as follows: First, when the chip select signal Cs is input, the clock enable signal ClkEn is pulled high using the RS latch. Then, the clock divider circuit 30 (which can be called the self-dividing circuit) starts to work, dividing the input high-frequency clock (i.e., the preset clock signal Clk) to obtain the first divided clock signal Div_Clk. After the first divided clock signal Div_Clk is counted to 16 in the divider counting circuit 50, the divider end signal ClkEnd in the enabled state is output. After the divider end signal ClkEnd passes through the RS latch, it pulls the clock enable signal ClkEn low, thereby turning off the clock divider circuit 30. The first frequency divider clock signal Div_Clk is toggled 16 times. Its rising and falling edges (i.e. the rising edges of the second frequency divider clock signal Div_ClkN) are sampled and counted in the chip select counting circuit 40 to represent the high and low levels of the input chip select signal Cs, respectively. The counting results are the first count value CNtH and the second count value CNtL.

[0086] by Figure 6 The circuit structure shown is illustrated, with a preset value of 16. The chip select signal Cs is sampled at a high level on the rising edge of the first divided clock signal Div_Clk and at a low level on the falling edge of the first divided clock signal Div_Clk. See [reference needed]. Figures 7 to 9 It shows the relevant timing diagram.

[0087] like Figure 7 As shown, when the chip select signal Cs is input (i.e., it flips from a long-term low level to a high level), the clock enable signal ClkEn output by the RS latch is pulled high, and the clock divider circuit 30 starts working. After the first divided clock signal Div_Clk is triggered 16 times (i.e., when the end count value Div_cnt reaches 16), the divided end signal ClkEnd is pulled high. After the divided end signal ClkEnd is pulled high, the clock enable signal ClkEn is immediately turned off (i.e., in the disabled state), and the clock divider circuit 30 also stops working. The rising and falling edges of the first divided clock signal Div_Clk count the high and low levels of the chip select signal Cs, respectively, to obtain the first count value CNtH and the second count value CNtL.

[0088] like Figure 8 As shown, the input chip select signal Cs is abnormal, and three high levels are lost during transmission. At this time, the first frequency divider clock signal Div_Clk will not be affected. When the rising edge of the clock does not sample the high level of the chip select signal Cs, the first count value CntH will remain unchanged. The falling edge of the clock will count the low level of the chip select signal Cs normally.

[0089] like Figure 9As shown, the input chip select signal Cs is abnormal, and three low levels are lost during transmission. At this time, the first frequency divider clock signal Div_Clk will not be affected. When the falling edge of the clock does not sample the low level of the chip select signal Cs, the second count value CntL will remain unchanged. The rising edge of the clock will count the high level of the chip select signal Cs normally.

[0090] It should be noted that, in Figures 7 to 9 In the timing diagram shown, when the count value of the frequency divider counting circuit 50 reaches 16, the clock enable signal ClkEn is pulled low. The count value 16 of the end count value Div_cnt is not shown in the attached figure.

[0091] In this way, the embodiments of this disclosure use a self-generated frequency-divided clock (i.e., the first frequency-divided clock signal Div_Clk and / or the second frequency-divided clock signal Div_ClkN) to sample the chip select signal Cs. This not only ensures that the circuit can work normally at high frequencies, but also eliminates the need to input an additional frequency-divided clock signal from an external circuit. This avoids the problem of inconsistent sampling edges between the external frequency-divided signal and the chip select signal Cs, and also reduces the power consumption of the circuit.

[0092] Furthermore, in this embodiment of the disclosure, the inverted signal of the chip select signal can also be defined as an inverted chip select signal. It can be understood that the first level state of the chip select signal corresponds to the second level state of the inverted chip select signal, and the second level state of the chip select signal corresponds to the first level state of the inverted chip select signal; that is, the high level state of the chip select signal corresponds to the low level state of the inverted chip select signal, and the low level state of the chip select signal corresponds to the high level state of the inverted chip select signal. The first topping edge of the first divided clock signal corresponds to the second topping edge of the second divided clock signal, and the second topping edge of the first divided clock signal corresponds to the first topping edge of the second divided clock signal; that is, the rising edge of the first divided clock signal corresponds to the falling edge of the second divided clock signal, and the falling edge of the first divided clock signal corresponds to the rising edge of the second divided clock signal.

[0093] Therefore, in this embodiment of the disclosure, the first level state of the chip select signal Cs, which is the flip edge of the first divided clock signal Div_Clk or the second divided clock signal Div_ClkN, can include the following specific forms:

[0094] The first level state of the chip select signal is counted using the first flip edge of the first frequency divider clock signal.

[0095] Alternatively, the first level state of the counting chip select signal can be used by utilizing the second flip edge of the second frequency divider clock signal;

[0096] Alternatively, the second level state of the inverted chip select signal can be counted using the first flip edge of the first frequency divider clock signal.

[0097] Alternatively, the second level state of the inverted chip select signal can be counted using the second flip edge of the second divided clock signal.

[0098] The second level state of the chip select signal Cs can be counted using the flip edge of the first divided clock signal Div_Clk or the second divided clock signal Div_ClkN, and can include the following specific forms:

[0099] The second level state of the counting chip select signal is directly utilized by the second flip edge of the first frequency divider clock signal;

[0100] Alternatively, the second level state of the counting chip select signal can be used by utilizing the first flip edge of the second frequency divider clock signal;

[0101] Alternatively, the second flip edge of the first frequency divider clock signal can be used to count the first level state of the inverted chip select signal;

[0102] Alternatively, the first level state of the inverted chip select signal can be counted using the first flip edge of the second frequency divider clock signal.

[0103] Based on this, the structure of the chip select counting circuit 40 will be described in detail by way of example.

[0104] like Figure 10 As shown, in some embodiments, the chip select counting circuit 40 includes:

[0105] The first chip select counting circuit 401 is configured to receive a chip select signal and a first divided clock signal, and use the first flip edge of the first divided clock signal to count the first level state of the chip select signal to generate a first count value; or, receive a chip select signal and a second divided clock signal, and use the second flip edge of the second divided clock signal to count the first level state of the chip select signal to generate a first count value; or, receive an inverted chip select signal and a first divided clock signal, and use the first flip edge of the first divided clock signal to count the second level state of the inverted chip select signal to generate a first count value; or, receive an inverted chip select signal and a second divided clock signal, and use the second flip edge of the second divided clock signal to sample the second level state of the inverted chip select signal to generate a first count value.

[0106] The second chip select counting circuit 402 is used to receive a chip select signal and a first frequency-divided clock signal, and use the second flip edge of the first frequency-divided clock signal to count the second level state of the chip select signal to generate a second count value; or, it receives a chip select signal and a second frequency-divided clock signal, and uses the first flip edge of the second frequency-divided clock signal to count the second level state of the chip select signal to generate a second count value; or, it receives an inverted chip select signal and a first frequency-divided clock signal, and uses the second flip edge of the first frequency-divided clock signal to count the first level state of the inverted chip select signal to generate a second count value; or, it receives an inverted chip select signal and a second frequency-divided clock signal, and uses the first flip edge of the second frequency-divided clock signal to count the first level state of the inverted chip select signal to generate a second count value.

[0107] It should be noted that, taking the example of the first chip select counting circuit 401 receiving the chip select signal Cs and the first divided clock signal Div_Clk, and obtaining the first count value CNtH by sampling the high level state of the chip select signal Cs based on the rising edge of the first divided clock signal Div_Clk; and the second chip select counting circuit 402 receiving the chip select signal Cs and the first divided clock signal Div_Clk, and obtaining the second count value CNtL by sampling the low level state of the chip select signal Cs based on the falling edge of the first divided clock signal Div_Clk, the relevant timing can be referred to the aforementioned... Figures 7-9 As shown.

[0108] For example Figure 7 As shown, the dashed line ① represents the rising edge of the first divided clock signal Div_Clk, which is aligned with the high level state of the chip select signal Cs. Thus, the high level state of the chip select signal Cs is successfully sampled using the rising edge of the first divided clock signal Div_Clk. Each successful sample increments the first count value CNtH by 1. The dashed line ② represents the falling edge of the first divided clock signal Div_Clk, which is aligned with the low level state of the chip select signal Cs. Thus, the low level state of the chip select signal Cs is successfully sampled using the falling edge of the first divided clock signal Div_Clk. Each successful sample increments the second count value CNtL by 1.

[0109] It should also be noted that, taking the high-level state of the chip select signal Cs using the rising edge of the first divided clock signal Div_Clk and the low-level state of the chip select signal Cs using the falling edge of the first divided clock signal Div_Clk as an example, assuming that the first count value CntH includes N bits of the first counter sub-signal CntH[i-1], and the second count value CntL includes N bits of the second counter sub-signal CntL[i-1], where N is a positive integer and i is an integer greater than 0 and less than or equal to N; Figure 11As shown, both the first chip select counting circuit 401 and the second chip select counting circuit 402 include N levels of counting sub-circuits 403. Taking N=4 as an example, the four levels of counting sub-circuits 403 in the first chip select counting circuit 401 are respectively denoted as: counting sub-circuit 1-1, counting sub-circuit 1-2, counting sub-circuit 1-3 and counting sub-circuit 1-4; the four levels of counting sub-circuit 403 in the second chip select counting circuit 402 are respectively denoted as: counting sub-circuit 2-1, counting sub-circuit 2-2, counting sub-circuit 2-3 and counting sub-circuit 2-4.

[0110] like Figure 11 As shown, each counter sub-circuit 403 includes a second logic circuit 4031 and a second flip-flop D2;

[0111] In the first-stage counting sub-circuit 403 of the first chip select counting circuit 401 and the second chip select counting circuit 402, the second logic circuit 4031 is the first NAND gate nand1, and in the second to Nth stage counting sub-circuits 403, the second logic circuit 4031 is the first NOT gate not1.

[0112] The first input terminal of the first NAND gate nand1 in the first chip select counting circuit 401 receives the chip select signal Cs, and the first input terminal of the first NAND gate nand1 in the second chip select counting circuit 402 receives the inverted chip select signal CsN.

[0113] In the first chip select counting circuit 401 and the second chip select counting circuit 402, the second input terminal of the first NAND gate nand1 is connected to the output terminal of the first stage second flip-flop D2 and the clock terminal of the second stage second flip-flop D2, and the output terminal of the first NAND gate nand1 is connected to the input terminal of the first stage second flip-flop D2; the clock terminal of the first stage second flip-flop D2 receives the first divided clock signal Div_Clk or the second divided clock signal Div_ClkN; the clock terminals of the second to Nth stage second flip-flops D2 are connected to the output terminals of the previous stage second flip-flops D2; the input terminal of the first NOT gate not1 is connected to the output terminal of the corresponding second flip-flop D2, and the output terminal of the first NOT gate not1 is connected to the input terminal of the corresponding second flip-flop D2;

[0114] In the first chip selector counting circuit 401, the output of the i-th second flip-flop D2 is used to output the i-th bit first counter sub-signal CntH[i-1];

[0115] In the second chip select counting circuit 402, the output of the i-th second flip-flop D2 is used to output the i-th bit second counter sub-signal CntL[i-1].

[0116] It should be noted that the second flip-flop D2 can specifically be a DFF, with its input terminal being the D terminal, its clock terminal being the CK terminal, and its output terminal being the Q terminal.

[0117] It should also be noted that, such as Figure 11 As shown, the second chip select counting circuit 402 may further include a fourth NOT gate not4; the input of the fourth NOT gate not4 receives the chip select signal Cs, and the output is connected to the first input of the first NAND gate nand1. The fourth NOT gate not4 is used to invert the chip select signal Cs into an inverted chip select signal CsN and then provide it to the first NAND gate nand1.

[0118] Thus, based on Figure 11 The circuit shown uses a cascaded N-stage counter circuit 403 to form a counter. In the first chip select counter circuit 401, whenever the rising edge of the first divided clock signal Div_Clk can successfully sample the high level of the chip select signal Cs, the first count value CNtH will be incremented by 1. In the second chip select counter circuit 402, whenever the falling edge of the first divided clock signal Div_Clk can successfully sample the low level of the chip select signal Cs, specifically, when the rising edge of the second divided clock signal Div_ClkN can successfully sample the high level of the inverted chip select signal CsN, the second count value CNtL will be incremented by 1. Ultimately, it can successfully count the high and low levels of the chip select signal Cs.

[0119] It should also be noted that the first frequency divider clock signal Div_Clk can be input to the clock terminal of the counter circuit 2-1, and the second frequency divider clock signal Div_ClkN can be input to the clock terminal of the counter circuit 1-1. This allows the counting chip select signal Cs to be high at the falling edge of the first frequency divider clock signal Div_Clk and low at the rising edge of the first frequency divider clock signal Div_Clk.

[0120] Thus, in this embodiment of the present disclosure, a counting circuit is formed by combining cascaded flip-flops with related logic circuits to realize the separate counting of the high and low levels of the chip select signal Cs.

[0121] In other embodiments, such as Figure 12 As shown, the chip select counting circuit 40 includes:

[0122] The first sampling circuit 404 is configured to receive a chip select signal and a first frequency-divided clock signal, and generate a first sampled signal by sampling the first level state of the chip select signal based on the first flip edge of the first frequency-divided clock signal; or, it is configured to receive a chip select signal and a second frequency-divided clock signal, and generate a first sampled signal by sampling the first level state of the chip select signal based on the second flip edge of the second frequency-divided clock signal; or, it is configured to receive a first frequency-divided clock signal and an inverted chip select signal, and generate a first sampled signal by sampling the second level state of the inverted chip select signal based on the first flip edge of the first frequency-divided clock signal; or, it is configured to receive a second frequency-divided clock signal and an inverted chip select signal, and generate a first sampled signal by sampling the second level state of the inverted chip select signal based on the second flip edge of the second frequency-divided clock signal.

[0123] The second sampling circuit 405 is configured to receive a chip select signal and a first frequency-divided clock signal, and generate a second sampled signal by sampling the second level state of the chip select signal based on the second flip edge of the first frequency-divided clock signal; or, it is configured to receive a chip select signal and a second frequency-divided clock signal, and generate a second sampled signal by sampling the second level state of the chip select signal based on the first flip edge of the second frequency-divided clock signal; or, it is configured to receive a first frequency-divided clock signal and an inverted chip select signal, and generate a second sampled signal by sampling the first level state of the inverted chip select signal based on the second flip edge of the first frequency-divided clock signal; or, it is configured to receive a second frequency-divided clock signal and an inverted chip select signal, and generate a second sampled signal by sampling the first level state of the inverted chip select signal using the first flip edge of the second frequency-divided clock signal.

[0124] The first counting circuit 406 is electrically connected to the first sampling circuit 404, and is used to receive the first sampling signal and count based on the first sampling signal to generate a first count value;

[0125] The second counting circuit 407 is electrically connected to the second sampling circuit 405. It is used to receive the second sampling signal and count based on the second sampling signal to generate a second count value.

[0126] It should be noted that, taking the example of the first sampling circuit 404 receiving the chip select signal Cs and the first divided clock signal Div_Clk and sampling the high level state of the chip select signal Cs based on the rising edge of the first divided clock signal Div_Clk to obtain the first sampled signal; the first counting circuit 406 receiving the first sampled signal and counting to obtain the first count value CNtH; the second sampling circuit 405 receiving the chip select signal Cs and the first divided clock signal Div_Clk and sampling the low level state of the chip select signal Cs based on the falling edge of the first divided clock signal Div_Clk to obtain the second sampled signal; and the second counting circuit 407 receiving the second sampled signal and counting to obtain the second count value CNtL, the relevant timing can be referred to the aforementioned example. Figures 7-9 As shown.

[0127] It should also be noted that, taking the example where the first sampling circuit 404 receives the chip select signal and the first frequency-divided clock signal, the first flip edge is a rising edge, and the first level state is a high level state, each time the first sampling circuit 404 successfully samples the high level state of the chip select signal using the rising edge of the first frequency-divided clock signal, a flip edge is generated in the first sampled signal. That is, the number of flip edges in the first sampled signal is the number of times the high level state of the chip select signal has been successfully sampled. The first counting circuit 406 counts the flip edges in the first sampled signal to obtain the first count value. The other cases are similar and will not be elaborated here.

[0128] Taking the second sampling circuit 405 receiving the inverted chip select signal and the second divided clock signal, with the first flip edge being a rising edge and the first level state being a high level state as an example, each time the second sampling circuit 405 successfully samples the high level state of the inverted chip select signal using the rising edge of the second divided clock signal, a flip edge is generated in the second sampled signal. That is, the number of flip edges in the second sampled signal is the number of times the high level state of the inverted chip select signal has been successfully sampled. The second counting circuit 407 counts the flip edges in the second sampled signal to obtain the second count value. The other cases are similar and will not be elaborated here.

[0129] In other words, the first sampling circuit 404 is used to generate a flip edge in the first sampling signal if a first level state of the chip select signal is sampled at the first flip edge of the first frequency division clock signal, or if a first level state of the chip select signal is sampled at the second flip edge of the second frequency division clock signal, or if a second level state of the inverted chip select signal is sampled at the first flip edge of the first frequency division clock signal, or if a second level state of the inverted chip select signal is sampled at the second flip edge of the second frequency division clock signal;

[0130] The second sampling circuit 405 is used to generate a flip edge in the second sampling signal if the second level state of the chip select signal is sampled at the second flip edge of the first frequency divider clock signal, or if the second level state of the chip select signal is sampled at the first flip edge of the second frequency divider clock signal, or if the first level state of the inverted chip select signal is sampled at the second flip edge of the first frequency divider clock signal, or if the first level state of the inverted chip select signal is sampled at the first flip edge of the second frequency divider clock signal.

[0131] The first counting circuit 406 is used to count the flip edges in the first sampled signal to obtain a first count value;

[0132] The second counting circuit 407 is used to count the flip edges in the second sampled signal to obtain the second count value.

[0133] Specifically, such as Figure 13 As shown, the first sampling circuit 404 may include: a second AND gate AND2, a third flip-flop D3, and a second NOT gate NOT2;

[0134] The first input of the second AND gate AND2 receives the chip select signal Cs, and the output of the second AND gate AND2 is connected to the input of the third flip-flop D3; the clock input of the third flip-flop D3 receives the first divided clock signal Div_Clk; the output of the third flip-flop D3 is connected to the input of the second NOT gate NOT2, and the output of the third flip-flop D3 is used to output the first sampling signal S1; the output of the second NOT gate NOT2 is connected to the second input of the second AND gate AND2.

[0135] The second sampling circuit 405 may include: a third AND gate (AND3), a fourth flip-flop (D4), and a third NOT gate (NOT3);

[0136] The first input of the third AND gate AND3 receives the inverted chip select signal CsN. The output of the third AND gate AND3 is connected to the input of the fourth flip-flop D4. The clock input of the fourth flip-flop D4 receives the second divided clock signal Div_ClkN. The output of the fourth flip-flop D4 is connected to the input of the third NOT gate NOT3. The output of the fourth flip-flop D4 is used to output the second sampling signal S2. The output of the third NOT gate NOT3 is connected to the second input of the third AND gate AND3.

[0137] It should be noted that, as Figure 13 As shown, both the third flip-flop D3 and the fourth flip-flop D4 can be DFF. The first sampling circuit 404 and the second sampling circuit 405 have the same structure and the same working principle. Taking the first sampling circuit 404 as an example, as... Figure 13 As shown, for the third flip-flop D3, before calibration training, the output of the third flip-flop D3 can be reset to 0 using a reset signal (not shown in the figure). Then, the output of the second NOT gate (not2) will be 1, meaning the signal received at the second input of the second AND gate (and2) will be 1. This transmits the chip select signal Cs to the input of the third flip-flop D3. The third flip-flop D3 samples the high-level state of the chip select signal Cs using the rising edge of the first divided clock signal Div_Ck. After successfully sampling a high-level state once, the output of the second NOT gate (not2) will flip to 0, returning to control the input of the third flip-flop D3. The final effect is that each successful sampling of the high-level state of the chip select signal Cs using the rising edge of the first divided clock signal Div_Ck causes the first sampling signal S1 to flip once. Therefore, the number of flip edges of the first sampling signal S1 is the number of times the high-level state of the chip select signal Cs is successfully sampled. The second sampling circuit 405 works similarly and will not be described further here.

[0138] Thus, this embodiment of the present disclosure utilizes a simple combination of logic gates and flip-flops to sample the corresponding level state of the chip select signal using the corresponding frequency-divided clock signal. This not only reduces the complexity of circuit design but also ensures that the circuit can work normally at high frequencies and guarantees the correct sampling of the chip select signal.

[0139] Furthermore, in this embodiment of the present disclosure, the specific method for counting the flip edges can be: processing the flip edge into pulses, and then counting the pulses. Therefore, as Figure 13 As shown, the first counting circuit 406 may include:

[0140] The first pulse generation circuit 4061 is used to receive the first sampling signal S1 and generate a pulse at each flip edge of the first sampling signal S1 to obtain the first pulse signal.

[0141] The first counting sub-circuit 4062 is used to receive the first pulse signal, count based on the first pulse signal, and obtain the first count value CNtH.

[0142] The second counting circuit 407 may include:

[0143] The second pulse generation circuit 4071 is used to receive the second sampling signal S2 and generate a pulse at each flip edge of the second sampling signal S2 to obtain the second pulse signal.

[0144] The second counting sub-circuit 4072 is used to receive the second pulse signal, count based on the second pulse signal, and obtain the second count value CntL.

[0145] It should be noted that the first counting circuit 406 and the second counting circuit 407 have the same structure. The first pulse generation circuit 4061 and the second pulse generation circuit 4071 can both be double-edge pulse generation circuits, that is, pulses are generated on both the rising and falling edges of the signal. The first counting sub-circuit 4062 and the second counting sub-circuit 4072 can both be counters, used to count the pulses or rising edges of the received signal.

[0146] Thus, this embodiment converts the level state (first level state or second level state) of the chip select signal into the overturning edge of the sampling signal (first sampling signal or second sampling signal), then converts the overturning edge of the sampling signal into a pulse signal (first pulse signal or second pulse signal), and finally counts the pulses, thereby realizing the counting of the high and low levels of the chip select signal.

[0147] In summary, the embodiments of this disclosure provide a chip select signal calibration circuit capable of generating its own frequency-divided clock. On the one hand, by using an internal clock divider circuit to divide the externally provided high-frequency preset clock signal into a low-frequency divided clock signal for counting the chip select signal, not only is the circuit complexity reduced, but the circuit can also operate normally at high frequencies. On the other hand, an enable clock signal is generated only when the chip select signal is confirmed to be received, which enables the clock divider circuit to perform frequency division. This ensures that the flipping edge in the divided clock signal corresponds to the level state of the chip select signal, meaning that the flipping edge can always successfully sample the corresponding level state. This ensures that the level state corresponding to the flipping edge is counted, avoiding the problem of inaccurate counting due to the uncertain sampling relationship caused by the mismatch between the positional relationship of the divided clock signal and the chip select signal. At the same time, it also avoids the extra power consumption caused by the divided clock signal constantly flipping before counting is required.

[0148] In another embodiment of this disclosure, a memory is also provided, which includes the chip select signal calibration circuit 10 of the foregoing embodiments.

[0149] The memory can be DRAM. In this embodiment, the DRAM can conform to memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, and DDR6, as well as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, and LPDDR6. No limitation is made here.

[0150] In this way, by using the aforementioned chip select signal calibration circuit 10 to calibrate the chip select signal, the circuit can operate normally at high frequencies, and the frequency division clock signal can correctly sample the chip select signal.

[0151] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0152] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0153] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0154] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0155] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0156] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0157] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A chip select signal calibration circuit, comprising: include: The frequency divider enable circuit is used to generate a clock enable signal for the enable state when a chip select signal is received. A clock divider circuit, connected to the divider enable circuit, is used to receive the clock enable signal and a preset clock signal. When the clock enable signal is enabled, the preset clock signal is divided to generate a divided clock signal. The clock period of the divided clock signal is the same as the clock period of the chip select signal. A chip select counting circuit, connected to the clock divider circuit, is used to receive the divided clock signal and the chip select signal, and to count the level state of the chip select signal by the flip edge of the divided clock signal to generate a count value. The chip select signal has two levels: a first level and a second level, which are inverses of each other. The flip edges include a first flip edge and a second flip edge, one of which is a rising edge and the other a falling edge. The count values ​​include a first count value and a second count value. The first count value is obtained by counting the first level using one of the first and second flip edges, and the second count value is obtained by counting the second level using the other of the first and second flip edges. After counting, if both the first and second count values ​​are preset values, the calibration is successful.

2. The chip select signal calibration circuit of claim 1, wherein, The frequency-divided clock signal includes a first frequency-divided clock signal and a second frequency-divided clock signal, wherein the first frequency-divided clock signal and the second frequency-divided clock signal are out of phase with each other; The chip select counting circuit is used to receive the first frequency-divided clock signal, the second frequency-divided clock signal, and the chip select signal; count the first level state of the chip select signal using the flip edge of the first frequency-divided clock signal or the second frequency-divided clock signal to generate the first count value; and count the second level state of the chip select signal using the flip edge of the first frequency-divided clock signal or the second frequency-divided clock signal to generate the second count value.

3. The chip select signal calibration circuit of claim 1, wherein, The chip select signal calibration circuit also includes a frequency division counting circuit; The frequency division counting circuit is connected to the clock frequency division circuit and is used to receive the frequency division clock signal, count based on the frequency division clock signal, and generate an end count value; when the end count value reaches a preset value, it generates an enabled frequency division end signal. The frequency division enable circuit is also used to receive the frequency division end signal, and when the frequency division end signal is in the enabled state, generate the clock enable signal in the disabled state.

4. The chip select signal calibration circuit of claim 3, wherein, The frequency divider enable circuit is an RS latch. The first input terminal of the RS latch receives the chip select signal, the second input terminal of the RS latch receives the frequency divider end signal, and the output terminal of the RS latch outputs the clock enable signal.

5. The chip select signal calibration circuit of claim 2, wherein, The clock divider circuit includes: A first logic circuit is configured to receive the clock enable signal and the second frequency-divided clock signal; when the clock enable signal is in the enabled state, the second frequency-divided clock signal is output as a sampling input signal. The sampling circuit, electrically connected to the first logic circuit, is used to receive the sampling input signal and the preset clock signal, sample the sampling input signal based on the preset clock signal, and output the first frequency-divided clock signal and the second frequency-divided clock signal respectively.

6. The chip select signal calibration circuit of claim 5, wherein, The first logic circuit includes a first AND gate, and the sampling circuit includes a first flip-flop; The first input terminal of the first AND gate receives the second frequency-divided clock signal, and the second input terminal of the first AND gate receives the clock enable signal; The output of the first AND gate is connected to the input of the first flip-flop, and is used to output the sampled input signal; The clock terminal of the first flip-flop receives the preset clock signal, the first output terminal of the first flip-flop outputs the first frequency-divided clock signal, and the second output terminal of the first flip-flop outputs the second frequency-divided clock signal.

7. The chip select signal calibration circuit of claim 2, wherein, The chip select counting circuit includes: The first chip select counting circuit is used to receive the chip select signal and the first frequency divider clock signal, and use the first flip edge of the first frequency divider clock signal to count the first level state of the chip select signal to generate the first count value. Alternatively, the chip select signal and the second divided clock signal are received, and the first level state of the chip select signal is counted using the second flip edge of the second divided clock signal to generate the first count value; Alternatively, receive the inverted chip select signal and the first frequency divider clock signal, and use the first flip edge of the first frequency divider clock signal to count the second level state of the inverted chip select signal to generate the first count value; Alternatively, the inverted chip select signal and the second divided clock signal are received, and the second level state of the inverted chip select signal is sampled using the second flip edge of the second divided clock signal to generate the first count value; The second chip select counting circuit is used to receive the chip select signal and the first frequency divider clock signal, and use the second flip edge of the first frequency divider clock signal to count the second level state of the chip select signal to generate the second count value; Alternatively, the chip select signal and the second divided clock signal are received, and the second level state of the chip select signal is counted using the first flip edge of the second divided clock signal to generate the second count value; Alternatively, the inverted chip select signal and the first frequency-divided clock signal are received, and the second count value is generated by counting the first level state of the inverted chip select signal using the second flip edge of the first frequency-divided clock signal. Alternatively, the inverted chip select signal and the second divided clock signal are received, and the first level state of the inverted chip select signal is counted using the first flip edge of the second divided clock signal to generate the second count value; Wherein, the inverted chip select signal is the inverted signal of the chip select signal; one of the first flip edge and the second flip edge is a rising edge and the other is a falling edge.

8. The chip select signal calibration circuit according to claim 7, characterized in that, The first count value includes an N-bit first count sub-signal, and the second count value includes an N-bit second count sub-signal, where N is a positive integer; both the first chip select counting circuit and the second chip select counting circuit include N levels of counting sub-circuits; each of the counting sub-circuits includes a second logic circuit and a second flip-flop; In the first-level counting sub-circuit, the second logic circuit is a first NAND gate; in the second to Nth-level counting sub-circuits, the second logic circuit is a first NOT gate. The first input terminal of the first NAND gate in the first chip select counting circuit receives the chip select signal, and the first input terminal of the first NAND gate in the second chip select counting circuit receives the inverted chip select signal; The second input of the first NAND gate is connected to the output of the first-stage second flip-flop and the clock terminal of the second-stage second flip-flop; the output of the first NAND gate is connected to the input of the first-stage second flip-flop; the clock terminal of the first-stage second flip-flop receives either the first divided clock signal or the second divided clock signal; the clock terminals of the second to Nth stages of the second flip-flop are connected to the output of the previous stage of the second flip-flop; the input of the first NOT gate is connected to the output of the corresponding second flip-flop; the output of the first NOT gate is connected to the input of the corresponding second flip-flop. In the first chip select counting circuit, the output of the i-th second flip-flop is used to output the i-th bit of the first counting sub-signal; In the second chip select counting circuit, the output of the i-th second flip-flop is used to output the i-th bit of the second counting sub-signal; i is an integer greater than 0 and less than or equal to N.

9. The chip select signal calibration circuit according to claim 2, characterized in that, The chip select counting circuit includes: A first sampling circuit is configured to receive the chip select signal and the first frequency-divided clock signal, and generate a first sampling signal by sampling the first level state of the chip select signal based on the first flip edge of the first frequency-divided clock signal. Alternatively, it can be used to receive the chip select signal and the second divided clock signal, sample the first level state of the chip select signal based on the second flip edge of the second divided clock signal, and generate the first sampled signal; Alternatively, it can be used to receive the first frequency-divided clock signal and the inverted chip select signal, and generate the first sampling signal by sampling the second level state of the inverted chip select signal based on the first flip edge of the first frequency-divided clock signal; Alternatively, it can be used to receive the second frequency-divided clock signal and the inverted chip select signal, and sample the second level state of the inverted chip select signal based on the second flip edge of the second frequency-divided clock signal to generate the first sampling signal; The second sampling circuit is used to receive the chip select signal and the first frequency-divided clock signal, and to sample the second level state of the chip select signal based on the second flip edge of the first frequency-divided clock signal to generate a second sampling signal; Alternatively, it can be used to receive the chip select signal and the second divided clock signal, sample the second level state of the chip select signal based on the first flip edge of the second divided clock signal, and generate the second sampled signal; Alternatively, it can be used to receive the first frequency-divided clock signal and the inverted chip select signal, and sample the first level state of the inverted chip select signal based on the second flip edge of the first frequency-divided clock signal to generate the second sampling signal; Alternatively, it can be used to receive the second divided clock signal and the inverted chip select signal, and use the first flip edge of the second divided clock signal to sample the first level state of the inverted chip select signal to generate the second sampling signal; wherein, the inverted chip select signal is the inverted signal of the chip select signal, and one of the first flip edge and the second flip edge is a rising edge and the other is a falling edge; A first counting circuit, electrically connected to the first sampling circuit, is used to receive the first sampling signal and count based on the first sampling signal to generate the first count value; The second counting circuit, electrically connected to the second sampling circuit, is used to receive the second sampling signal and count based on the second sampling signal to generate the second count value.

10. The chip select signal calibration circuit according to claim 9, characterized in that, The first sampling circuit is further configured to: if the first level state of the chip select signal is sampled at the first flip edge of the first frequency-divided clock signal, or if the first level state of the chip select signal is sampled at the second flip edge of the second frequency-divided clock signal, or if the second level state of the inverted chip select signal is sampled at the first flip edge of the first frequency-divided clock signal, or if the second level state of the inverted chip select signal is sampled at the second flip edge of the second frequency-divided clock signal, then generate a flip edge in the first sampling signal; The second sampling circuit is further configured to: if the second level state of the chip select signal is sampled at the second flip edge of the first frequency-divided clock signal, or if the second level state of the chip select signal is sampled at the first flip edge of the second frequency-divided clock signal, or if the first level state of the inverted chip select signal is sampled at the second flip edge of the first frequency-divided clock signal, or if the first level state of the inverted chip select signal is sampled at the first flip edge of the second frequency-divided clock signal, then generate a flip edge in the second sampling signal; The first counting circuit is used to count the flip edges in the first sampled signal to obtain the first count value; The second counting circuit is used to count the flip edges in the second sampled signal to obtain the second count value.

11. The chip select signal calibration circuit according to claim 10, characterized in that, The first sampling circuit includes: a second AND gate, a third flip-flop, and a second NOT gate; The first input of the second AND gate receives the chip select signal, and the output of the second AND gate is connected to the input of the third flip-flop; the clock terminal of the third flip-flop receives the first frequency-divided clock signal; the output of the third flip-flop is connected to the input of the second NOT gate, and the output of the third flip-flop is used to output the first sampled signal; the output of the second NOT gate is connected to the second input of the second AND gate. The second sampling circuit includes: a third AND gate, a fourth flip-flop, and a third NOT gate; The first input terminal of the third AND gate receives the inverted chip select signal, and the output terminal of the third AND gate is connected to the input terminal of the fourth flip-flop; the clock terminal of the fourth flip-flop receives the second frequency-divided clock signal; the output terminal of the fourth flip-flop is connected to the input terminal of the third NOT gate, and the output terminal of the fourth flip-flop is used to output the second sampling signal; the output terminal of the third NOT gate is connected to the second input terminal of the third AND gate.

12. The chip select signal calibration circuit according to claim 10, characterized in that, The first counting circuit includes: The first pulse generation circuit is used to receive the first sampled signal and generate a pulse on each flip edge of the first sampled signal to obtain the first pulse signal. A first counting sub-circuit is used to receive the first pulse signal, count based on the first pulse signal, and obtain the first count value; The second counting circuit includes: The second pulse generation circuit is used to receive the second sampled signal and generate a pulse on each flip edge of the second sampled signal to obtain the second pulse signal. The second counting sub-circuit is used to receive the second pulse signal, count based on the second pulse signal, and obtain the second count value.

13. The chip select signal calibration circuit according to claim 2, characterized in that, The chip select signal calibration circuit is also connected to the control circuit; The control circuit is used to receive the first count value and the second count value, and after the chip select counting circuit stops counting, determine whether the first count value and the second count value are both the preset value; If yes, the calibration is confirmed as successful; otherwise, the calibration is confirmed as failed.

14. A memory, characterized in that, Includes the chip select signal calibration circuit as described in any one of claims 1-13.

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