Semiconductor structure and memory device

Abstract

The embodiment of the invention relates to a semiconductor structure, comprising a substrate which comprises an active region and a peripheral region; the bit line structure is located in the active region and is stacked parallel to the surface of the substrate, and at least one end of the bit line structure is provided with a step structure; the vertical word lines are electrically connected with the bit line structures; the first conduction structure is located in the peripheral region, one end of the first conduction structure is connected with the substrate, and the other end of the first conduction structure is flush with the top surface of the vertical word line; the horizontal word line is located above the vertical word line, the first peripheral word line is located above the first conduction structure, the horizontal word line is electrically connected with the vertical word line, and the first peripheral word line is electrically connected with the first conduction structure; a metal layer is also arranged above the horizontal word line and the first peripheral word line, and the metal layer is electrically connected with the horizontal word line and the first peripheral word line respectively; a first doped region is further arranged below the first conduction structure, the first doped region is located in the substrate, a PN junction is arranged in the first doped region, or the first doped region and the first conduction structure form the PN junction.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and in particular to a semiconductor structure and memory device. Background Technology

[0002] The development of dynamic random access memory (DRAM) pursues performance indicators such as high speed, high integration density, and low power consumption. However, with the miniaturization of semiconductor device structures, the technological barriers encountered by existing structures are becoming increasingly apparent. The emergence of three-dimensional dynamic random access memory (3DDRAM) meets these requirements. However, the current 3D DRAM manufacturing process can cause plasma-induced damage (PID), which leads to electrical misalignment and reliability degradation, affecting the performance and yield of the device structure. Summary of the Invention

[0003] This disclosure provides a semiconductor structure and memory device that at least helps to solve the PID effect problem.

[0004] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including:

[0005] The substrate includes the active region and the peripheral region;

[0006] Bitline structures are stacked in the active region and parallel to the substrate surface, and at least one end of the bitline structure has a stepped structure in a direction perpendicular to the substrate surface.

[0007] Vertical character lines are perpendicular to the substrate surface and electrically connected to the character line structure.

[0008] The first conductive structure is located in the outer area. One end of the first conductive structure is connected to the base, and the other end of the first conductive structure is flush with the top surface of the vertical character line.

[0009] The horizontal character line is located above the vertical character line, the first outer character line is located above the first conductive structure, the horizontal character line is electrically connected to the vertical character line, and the first outer character line is electrically connected to the first conductive structure.

[0010] A metal layer is also provided above the horizontal character line and the first peripheral character line, and the metal layer is electrically connected to the horizontal character line and the first peripheral character line respectively.

[0011] Below the first conductive structure, there is a first doped region located within the substrate. The first doped region contains a PN junction, or the first doped region and the first conductive structure form a PN junction.

[0012] In some embodiments, the first peripheral word line, the first conductive structure, and the first doped region together constitute a first conductive path, and the metal layer is electrically connected to at least one first conductive path.

[0013] In some embodiments, the first conducting structure is doped polysilicon, and the doped polysilicon and the first doped region form a PN junction; the first conducting structure is N-type doped, and the first doped region is P-type doped.

[0014] In some embodiments, the first conducting structure is a metal, and the first doped region includes a first sub-doped region and a second sub-doped region. The doping types of the first sub-doped region and the second sub-doped region are opposite. The first sub-doped region is located below the second sub-doped region, and the first sub-doped region and the second sub-doped region form a PN junction. The first sub-doped region is N-type doped and the second sub-doped region is P-type doped.

[0015] In some embodiments, the horizontal word line and the first peripheral word line are located at the same level; the metal layer is electrically connected to the first peripheral word line and the horizontal word line respectively through the first connecting via and the second connecting via.

[0016] In some embodiments, the first peripheral character line and the first conductive structure further have a first connecting structure, and the vertical character line and the horizontal character line further have a second connecting structure, the first connecting structure and the second connecting structure being located at the same level; the first connecting structure further includes a first contact structure and a first transfer structure; the second connecting structure further includes a second contact structure and a second transfer structure.

[0017] In some embodiments, a second conducting structure is further included. The second conducting structure is located in the peripheral region. One end of the second conducting structure is connected to the substrate, and the other end of the second conducting structure is flush with the top surface of the vertical word line. Below the second conducting structure, there is a second doped region located in the substrate. The second doped region has a PN junction or the second doped region and the second conducting structure form a PN junction.

[0018] In some embodiments, the second conduction structure is doped polysilicon, and the doped polysilicon and the second doped region form a PN junction; the second conduction structure is N-type doped, and the second doped region is P-type doped.

[0019] In some embodiments, the second conducting structure is a metal, and the second doped region includes a third sub-doped region and a fourth sub-doped region. The third sub-doped region and the fourth sub-doped region have opposite doping types. The third sub-doped region is located below the fourth sub-doped region, and the third sub-doped region and the fourth sub-doped region form a PN junction. The third sub-doped region is N-type doped, and the fourth sub-doped region is P-type doped.

[0020] In some embodiments, a plug structure is provided at one end of the bit line structure near the second conductive structure. The plug structure is electrically connected to the bit line structure, and the top of the plug structure is flush with the top surface of the vertical word line.

[0021] In some embodiments, a second peripheral word line is also included, which is located above the second conductive structure and extends above the plug structure. The second peripheral word line is electrically connected to the second conductive structure and the plug structure, respectively. The first peripheral word line and the second peripheral word line are located at the same level.

[0022] In some embodiments, the second conductive structure and the second doped region together constitute a second conductive path, and the second peripheral word line is electrically connected to at least one second conductive path.

[0023] In some embodiments, a third connecting structure is provided between the plug structure and the second peripheral word line, and a fourth connecting structure is provided between the second peripheral word line and the second conductive structure. The third connecting structure and the fourth connecting structure are located at the same level. The third connecting structure further includes a third contact structure and a third transfer structure, and the fourth connecting structure further includes a fourth contact structure and a fourth transfer structure.

[0024] Another aspect of this disclosure provides a storage device, including:

[0025] The substrate includes the active region and the peripheral region;

[0026] The word line structure and bit line structure are arranged in a mesh pattern on the active region;

[0027] At least one end of the word line structure and / or bit line structure has a lead-out structure, which is electrically connected to the conduction structure of the peripheral area;

[0028] The substrate beneath the conductive structure also contains a doped region, which contains a PN junction or the doped region and the conductive structure together form a PN junction.

[0029] The lead-out structure, the conductive structure, and the doped region constitute the conductive path.

[0030] In some embodiments, the bit line structure is stacked parallel to the substrate surface, and at least one end of the bit line structure has a stepped structure in a direction perpendicular to the substrate surface; the word line structure is perpendicular to the substrate surface and electrically connected to the bit line structure.

[0031] In some embodiments, word line structures are stacked parallel to the substrate surface, and at least one end of the word line structure has a stepped structure in a direction perpendicular to the substrate surface; bit line structures are perpendicular to the substrate surface and electrically connected to the word line structures.

[0032] In some embodiments, the conducting structure is doped polysilicon, and the doped polysilicon and the doped region form a PN junction; the conducting structure is N-type doped, and the doped region is P-type doped.

[0033] In some embodiments, the conducting structure is metal, and the doped region includes a first sub-doped region and a second sub-doped region. The doping types of the first sub-doped region and the second sub-doped region are opposite. The first sub-doped region is located below the second sub-doped region, and the first sub-doped region and the second sub-doped region form a PN junction. The first sub-doped region is N-type doped and the second sub-doped region is P-type doped.

[0034] The technical solution provided in this disclosure provides at least a first conductive structure and a first doped region in the peripheral region. The first doped region has a PN junction or the first doped region and the first conductive structure form a PN junction. The PN junction has a unidirectional conduction function, so that the plasma generated during the process is introduced into the substrate through the first conductive structure and the first doped region, thereby preventing PID effect and improving the performance and yield that affect the device structure. Attached Figure Description

[0035] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0037] Figure 2 A schematic diagram of a semiconductor structure provided for another embodiment of this disclosure;

[0038] Figure 3 This is a schematic diagram of a semiconductor structure provided in yet another embodiment of the present disclosure;

[0039] Figure 4 This is a schematic diagram of a semiconductor structure provided in yet another embodiment of the present disclosure;

[0040] Figure 5 A schematic diagram of a semiconductor structure provided in an embodiment of this disclosure;

[0041] Figure 6 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure;

[0042] Figure 7 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure;

[0043] Figure 8 This is another schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0044] Figure 9 Top view of the peripheral area provided in the embodiments of this disclosure;

[0045] Figure 10 A schematic diagram of a 3D DRAM architecture provided in this disclosure embodiment;

[0046] Figure 11 A schematic diagram of another 3D DRAM architecture provided in this disclosure embodiment;

[0047] Figure 12 A schematic diagram of a storage device provided in an embodiment of this disclosure;

[0048] Figure 13 A schematic diagram of another storage device provided in an embodiment of this disclosure;

[0049] Figure 14 A schematic diagram of another storage device provided in an embodiment of this disclosure;

[0050] Figure 15 This is a schematic diagram of another storage device provided in an embodiment of the present disclosure. Detailed Implementation

[0051] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0052] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0053] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0054] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0055] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0056] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0057] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 2 A schematic diagram of a semiconductor structure provided for another embodiment of this disclosure; Figure 3 This is a schematic diagram of a semiconductor structure provided in yet another embodiment of the present disclosure; Figure 4 This is a schematic diagram of a semiconductor structure provided in yet another embodiment of the present disclosure; Figure 5 A schematic diagram of a semiconductor structure provided in an embodiment of this disclosure; Figure 6 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure; Figure 7 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure; Figure 8 This is another schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 9 Top view of the peripheral area provided in the embodiments of this disclosure; Figure 10 A schematic diagram of a 3D DRAM architecture provided in this disclosure embodiment; Figure 11 A schematic diagram of another 3D DRAM architecture provided in this disclosure embodiment; Figure 12 A schematic diagram of a storage device provided in an embodiment of this disclosure;

[0058] Figure 13 A schematic diagram of another storage device provided in an embodiment of this disclosure; Figure 14 A schematic diagram of another storage device provided in an embodiment of this disclosure; Figure 15 This is a schematic diagram of another storage device provided in an embodiment of the present disclosure.

[0059] Figure 1This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure; the semiconductor structure includes: a substrate 10, the substrate 10 including an active region 101 and a peripheral region 102; a bit line structure 20, located in the active region 101 and stacked parallel to the surface of the substrate 10, at least one end of the bit line structure 20 having a stepped structure 201 along a direction perpendicular to the surface of the substrate 10, as shown by the dashed box in the figure; a vertical word line 30, perpendicular to the surface of the substrate 10 and electrically connected to the bit line structure 20; a first conduction structure 401, located in the peripheral region 102, one end of the first conduction structure 401 connected to the substrate 10, and the other end of the first conduction structure 401 flush with the top surface of the vertical word line 30. The horizontal character line 51 is located above the vertical character line 30, and the first peripheral character line 501 is located above the first conductive structure 401. The horizontal character line 51 is electrically connected to the vertical character line 30, and the first peripheral character line 501 is electrically connected to the first conductive structure 401. A metal layer 60 is also provided above the horizontal character line 51 and the first peripheral character line 501, and the metal layer 60 is electrically connected to the horizontal character line 51 and the first peripheral character line 501 respectively. A first doped region 701 is also provided below the first conductive structure 401. The first doped region 701 is located in the substrate 10, and the first doped region 701 has a PN junction or the first doped region 701 and the first conductive structure 401 form a PN junction.

[0060] It should be noted that, in Figure 1 In the illustrated 3D DRAM, bit line structures 20 are stacked along a direction perpendicular to the substrate 10 to form a multi-layer structure. Each layer contains multiple memory cells, which are connected through metal interconnect layers (such as BEOL, BackEnd Of Line) to enable data read and write operations. To achieve efficient data access in the multi-layer structure, the 3D DRAM incorporates a stepped structure 201. As shown in the figure, stepped contact points are formed at the edges of each bit line structure 20. These stepped contact points are the stepped structure 201, which is connected to the circuitry of the next or top layer via vertical conductive vias (such as TSV, Through Silicon Via). This design allows for high-speed data transmission in the vertical direction while reducing horizontal wiring, thereby lowering latency and power consumption.

[0061] It should be noted that in 3D DRAM, the horizontal word line 51 and the vertical word line 30 are used to select and control memory cells for data read and write operations, but their implementation and function differ in the three-dimensional architecture. In each layer of 3D DRAM, the horizontal word line 51 is used to select the row of memory cells in that layer. When a horizontal word line is activated, it turns on the transistors of all memory cells in that row, allowing the bit line structure 20 to interact with the capacitors of these memory cells. In the vertical stacking structure of 3D DRAM, the vertical word line 30 is used to select memory cells in different layers. Unlike the horizontal word line, the vertical word line 30 is arranged along the direction of the memory cell stack. By activating a specific vertical word line, the row of memory cells in different layers can be controlled. This design allows 3D DRAM to achieve higher storage density in the vertical direction, while the selection mechanism of the vertical word line enables precise access to memory cells in a specific layer.

[0062] Furthermore, the first peripheral word line 501 is actually the peripheral word line in 3D DRAM. To facilitate the distinction between different positions, this application divides the peripheral word lines into first and second peripheral word lines. It should be noted that the functions of both the first peripheral word line here and the second peripheral word line mentioned later are the same as those of the peripheral word lines in 3D DRAM. In 3D DRAM, peripheral word lines are used to control auxiliary circuits related to the memory cell array to ensure the normal operation of the memory and the correct reading and writing of data. That is, peripheral word lines are usually used to control the functions in the peripheral circuits of the memory, such as refresh circuits, address decoders, and read / write circuits.

[0063] The first peripheral word line 501, the first conductive structure 401, and the first doped region 701 together constitute a first conductive path D1, and the metal layer 60 is electrically connected to at least one of the first conductive paths D1. In one embodiment, such as Figure 1As shown, the first conductive structure 401 is doped polysilicon, and the doped polysilicon and the first doped region 701 form a PN junction; the first conductive structure is N-type doped, and the first doped region is P-type doped, wherein the substrate 10 can be P-type doped. It should be noted that the figures in this application show that the surface area of ​​the first doped region 701 is equal to the bottom area of ​​the first conductive structure 401 in contact with it. However, in other embodiments, the projection of the first conductive structure 401 on the substrate 10 may also be located within the first doped region 701, that is, the surface area of ​​the first doped region 701 is greater than the bottom area of ​​the first conductive structure 401 in contact with it. This allows the first conductive structure 401 to make better contact with the bottom first doped region 701. The surface area of ​​the second doped region 702 mentioned later may also be greater than the bottom area of ​​the second conductive structure 402 in contact with it.

[0064] In semiconductor manufacturing processes, multiple plasma etching and ion implantation steps are required. In the plasma environment, a large number of ions and electrons are generated by the discharge. These ions and electrons are collected by the metal layer 60 of the BEOL, at which point the metal layer 60 functions as an "antenna." As more and more ions and electrons are collected, they may damage the device on the silicon wafer. This damage is known as plasma-induced damage (PID). Specifically, since the metal layer 60 is electrically connected to the vertical word line 30, the ions and electrons collected by the metal layer 60 also accumulate on the vertical word line 30. Because the word line structure has a gate dielectric layer (not shown in the figure), the gate dielectric layer can be regarded as the dielectric layer of a capacitor. As more and more charge is collected on the vertical word line 30, the gate voltage becomes higher and higher, causing the gate dielectric layer to tunnel, which in turn causes a shift in threshold voltage and current, reducing the yield of semiconductor devices and affecting their reliability. In this embodiment, by setting a first conductive path D1 electrically connected to the vertical word line 30, ions and electrons collected by the metal layer 60 are introduced into the substrate 10, preventing tunneling effect. Furthermore, since the first conductive structure 401 is doped polysilicon, the first conductive structure is N-type doped, and the first doped region is P-type doped, the doped polysilicon and the first doped region 701 form a PN junction. The PN junction has the function of unidirectional conduction and reverse cutoff, that is, it has the function of an equivalent diode. This allows ions and electrons collected by the metal layer 60 to flow through the first peripheral word line 501, the first conductive structure 401, and the first doped region 701 and be introduced into the substrate 10, thereby preventing the vertical word line 30 from generating a tunneling effect and improving the yield and reliability of semiconductor devices.

[0065] Figure 2 A schematic diagram of a semiconductor structure provided in another embodiment of this disclosure, such as... Figure 2As shown, unlike the previous embodiment, the first conductive structure 401 is a metal, and the first doped region 701 includes a first sub-doped region 7011 and a second sub-doped region 7012. The doping types of the first sub-doped region 7011 and the second sub-doped region 7012 are opposite. The first sub-doped region 7011 is located below the second sub-doped region 7012, and the first sub-doped region 7011 and the second sub-doped region 7012 form a PN junction. The first sub-doped region 7011 is N-type doped, and the second sub-doped region 7012 is P-type doped. The fact that the first conductive structure 401 is a metal can improve conductivity. The first conductive structure 401 can be a metal or alloy such as gold, silver, copper, aluminum, or tungsten, and the specific metal type is not limited. In one embodiment, the first conductive structure 401 can include a multilayer structure, such as a stack of titanium, titanium nitride, and tungsten layered from bottom to top. The titanium and titanium nitride form an ohmic contact with the substrate 10. When the first conducting structure 401 is metal, in order to achieve the equivalent diode function, that is, the ions and electrons collected by the metal layer 60 can be unidirectionally conducted into the substrate, the first sub-doped region 7011 and the second sub-doped region 7012 form a PN junction due to opposite doping types, and the electrons collected by the metal layer 60 are unidirectionally conducted into the substrate.

[0066] In some embodiments, such as Figure 1 and Figure 2 As shown, the horizontal word line 51 and the first peripheral word line 501 are located at the same level; the metal layer 60 is electrically connected to the first peripheral word line 501 and the horizontal word line 51 respectively through the first connecting via CT1 and the second connecting via CT2. Since 3D DRAM is composed of multiple vertically stacked layers, the statement that the horizontal word line 51 and the first peripheral word line 501 are at the same level means that they are on the same physical plane, i.e., on the same layer. In the vertically stacked structure, the memory cells and control circuits are on the same physical plane, and they together constitute the memory cell array of each layer. Data reading and writing are realized through the control of the word line and bit line structures. In this application, "the same level" refers to being on the same layer, i.e., on the same physical plane.

[0067] In some embodiments, such as Figure 1 and Figure 2As shown, a first connecting structure 81 is provided between the first peripheral character line 501 and the first conductive structure 401, and a second connecting structure 82 is provided between the vertical character line 30 and the horizontal character line 51. The first connecting structure 81 and the second connecting structure 82 are located at the same level. The first connecting structure 81 also includes a first contact structure 811 and a first transfer structure 812. The second connecting structure 82 also includes a second contact structure 821 and a second transfer structure 822. The first connecting structure 81 realizes the electrical connection between the vertical character line 30 and the horizontal character line 51 through the first contact structure 811 and the first transfer structure 812. The second connecting structure 82 realizes the electrical connection between the first peripheral character line 501 and the first conductive structure 401 through the second contact structure 821 and the second transfer structure 822. The materials of the first contact structure 811 and the second contact structure 821 can be titanium, titanium nitride, or a mixture of titanium and titanium nitride. Other conductive materials are acceptable as long as they can achieve the conductive effect. The materials of the first transfer structure 812 and the second transfer structure 822 are also conductors.

[0068] Figure 3 This is a schematic diagram of a semiconductor structure provided in another embodiment of the present disclosure. Unlike the previous embodiment, the semiconductor structure further includes a second conductive structure 402. The second conductive structure 402 is located in the peripheral region 102. One end of the second conductive structure 402 is connected to the substrate 10, and the other end is flush with the top surface of the vertical word line 30. Below the second conductive structure 402, there is also a second doped region 702 located within the substrate 10. The second doped region 702 contains a PN junction, or the second doped region 702 and the second conductive structure 402 form a PN junction. It should be noted that the active region 101 has peripheral regions 102 on both sides. The first doped region 701 is located in the peripheral region 102 on one side of the active region 101, and the second doped region 702 is located in the peripheral region 102 on the other side of the active region 101. The second conducting structure 402 is doped polysilicon, and the doped polysilicon and the second doped region 702 form a PN junction; the second conducting structure 402 is N-type doped, and the second doped region 702 is P-type doped.

[0069] Figure 4 This is a schematic diagram of a semiconductor structure provided in yet another embodiment of the present disclosure, and... Figure 3The difference lies in the fact that the second conductive structure 402 is a metal. The material of the second conductive structure 402 can be the same as that of the first conductive structure 401, such as gold, silver, copper, aluminum, tungsten, or other metals or alloys. There is no limitation on the specific metal type. In one embodiment, the first conductive structure 401 may include a multilayer structure, such as a stack of titanium, titanium nitride, and tungsten layers layered from bottom to top. The titanium and titanium nitride form an ohmic contact with the substrate 10. The second doped region 702 includes a third sub-doped region 7021 and a fourth sub-doped region 7022. The doping types of the third sub-doped region 7021 and the fourth sub-doped region 7022 are opposite. The third sub-doped region 7021 is located below the fourth sub-doped region 7022, and the third sub-doped region 7021 and the fourth sub-doped region 7022 form a PN junction. The third sub-doped region 7021 is N-type doped, and the fourth sub-doped region 7022 is P-type doped.

[0070] like Figure 3 and Figure 4 As shown, a plug structure 90 is provided at one end of the bit line structure 20 near the second conductive structure 402. The plug structure 90 is electrically connected to the bit line structure 20, and the top of the plug structure 90 is flush with the top surface of the vertical word line 30. The plug structure 90 also includes a first sub-plug structure 901 and a second sub-plug structure 902. The second sub-plug structure 902 is parallel to and connected to the bit line structure 20. The second sub-plug structure 902 does not occupy the stepped structure 201 at the end of the bit line structure 20 to lead out the signal. The first sub-plug structure 901 is located above the second sub-plug structure 902 and is perpendicular to it. In addition, the projection of the first sub-plug structure 901 onto the second sub-plug structure 902 is located within the second sub-plug structure 902, that is, the cross-sectional area of ​​the first sub-plug structure 901 is smaller than the top area of ​​the second sub-plug structure 902, so that the contact window of the first sub-plug structure 901 on the second sub-plug structure 902 is larger. Even if the first sub-plug structure 901 is slightly offset, it will not affect the electrical connection between the first sub-plug structure 901 and the second sub-plug structure 902. The top of the plug structure 90 is flush with the top surface of the vertical word line 30 to control the structure of different areas to be located in the same layer, so as to facilitate subsequent processes.

[0071] In some embodiments, a second peripheral word line 502 is further included. The second peripheral word line 502 is located above the second conductive structure 402 and extends above the plug structure 90. The second peripheral word line 502 is electrically connected to both the second conductive structure 402 and the plug structure 90. The first peripheral word line 501 and the second peripheral word line 502 are located at the same level. The second conductive structure 402 and the second doped region 702 together constitute a second conductive path D2. The second peripheral word line 502 is electrically connected to at least one second conductive path D2, that is, at least one bit line structure 20 is electrically connected to the second conductive path D2 through the second peripheral word line 502.

[0072] In some embodiments, a third connecting structure 83 is provided between the plug structure 90 and the second peripheral word line 502, and a fourth connecting structure 84 is provided between the second peripheral word line 502 and the second conductive structure 402. The third connecting structure 83 and the fourth connecting structure 84 are located at the same level. The third connecting structure 83 further includes a third contact structure 831 and a third transfer structure 832, and the fourth connecting structure 84 further includes a fourth contact structure 841 and a fourth transfer structure 842.

[0073] In this embodiment, at least one vertical word line 30 is electrically connected to the first conductive path D1, and at least one bit line structure 20 is electrically connected to the second conductive path D2. Since the PID effect accumulates not only on the metal layer 60 but also on the second peripheral word line 502, and since the second peripheral word line 502, as a conductor, can also collect ions or electrons, this application adds a second conductive path D2 to conduct the ions or electrons collected by the second peripheral word line 502 into the substrate 10, preventing the PID effect from affecting the bit line structure 20. That is, in this embodiment, the first conductive path D1 conducts the ions or electrons collected by the metal layer 60 into the substrate, and the second conductive path D2 conducts the ions or electrons collected by the second peripheral word line 502 into the substrate, further improving the yield and reliability of the semiconductor device.

[0074] Specific examples Figure 3 As shown, the second conductive structure 402 is N-type doped polysilicon, and the second doped region 702 below the second conductive structure 402 is P-type doped. The second conductive structure 402 and the second doped region 702 form a PN junction, allowing the collected electrons to be unidirectionally introduced into the substrate. Specifically, as shown... Figure 4 As shown, the second conducting structure 402 is metal, the third sub-doped region 7021 within the second doped region 702 is N-type doped, and the fourth sub-doped region 7022 is P-type doped. The third sub-doped region 7021 and the fourth sub-doped region 7022 form a PN junction, allowing the collected electrons to be unidirectionally introduced into the substrate. The PN junction configuration ensures unidirectional electron conduction, preventing interference with the vertical word line 30 and the bit line structure 20. It should also be noted that during normal device operation, if a positive voltage is applied to the vertical word line 30, the current will not flow into the substrate 10 but will be reversed due to the unidirectional conduction of the PN junction in the first conducting path D1. Therefore, the first conducting path D1 is only used to address the PID effect and does not affect the normal operation of the device. Specifically, the first conductive structure 401 and the second conductive structure 402 can be formed by first performing slit etching (SLE) on the top of the stacked structure of the 3D DRAM to form an initial opening, then performing lateral etching on the initial opening to form a final opening, and filling the final opening with conductive material to form the first conductive structure 401 and the second conductive structure 402.

[0075] Figure 5 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure, and... Figure 3 The difference is that each vertical word line 30 is electrically connected to a first conductive path D1 through a metal layer 60, and each bit line structure 30 is electrically connected to a second conductive path D2 through a second peripheral word line 502. Figure 5 The diagram shows three bit line structures 30, only schematically illustrating two second conductive paths D2. It should be noted that this is merely illustrative; in reality, each bit line structure 20 is electrically connected to one second conductive path D2 in this embodiment. Furthermore, multiple first doped regions 701 are isolated from each other by an isolation structure 103, and multiple second doped regions 702 are also isolated from each other by the isolation structure 103. Figure 5 As shown, both the first conducting structure 401 and the second conducting structure 402 are doped polysilicon, and both are N-type doped. The first doped region 701 and the second doped region 702 are both P-type doped. The first conducting structure 401 and the first doped region 701 form a PN junction, and the second conducting structure 402 and the second doped region 702 also form a PN junction. Figure 3 The same repetitive structures will not be elaborated here; please refer to [reference needed]. Figure 3 In this embodiment, each vertical word line 30 is electrically connected to a first conductive path D1 through a metal layer 60, and each bit line structure 30 is electrically connected to a second conductive path D2 through a second peripheral word line 502. This allows more ions and electrons accumulated in the metal layer 60 to be introduced into the substrate, reducing the impact of PID effect on device performance.

[0076] Figure 6 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure, and... Figure 5 The difference is: Figure 5 The first conducting structure 401 and the second conducting structure 402 are both doped polycrystalline silicon. Figure 6 The first conductive structure 401 and the second conductive structure 402 are both metals, and as shown in the figure... Figure 6As shown, the first doped region 701 includes a first sub-doped region 7011 and a second sub-doped region 7012. The first sub-doped region 7011 is N-type doped, and the second sub-doped region 7012 is P-type doped. The first sub-doped region 7011 and the second sub-doped region 7012 form a PN junction. The second doped region 702 includes a third sub-doped region 7021 and a fourth sub-doped region 7022. The third sub-doped region 7021 is N-type doped, and the fourth sub-doped region 7022 is P-type doped. The third sub-doped region 7021 and the fourth sub-doped region 7022 form a PN junction. Multiple first doped regions 701 are isolated from each other by an isolation structure 103, and multiple second doped regions 702 are also isolated from each other by an isolation structure 103. In this embodiment, each vertical word line 30 is electrically connected to a first conductive path D1 through a metal layer 60, and each bit line structure 30 is electrically connected to a second conductive path D2 through a second peripheral word line 502, so that more ions and electrons gathered in the metal layer 60 can be introduced into the substrate, reducing the impact of PID effect on device performance.

[0077] Figure 7 Another schematic diagram of a semiconductor structure provided in this disclosure embodiment, such as... Figure 7As shown, each vertical character line 30 is electrically connected to at least one first conductive path D1 through the metal layer 60. The figure shows the metal layer 60 being electrically connected to two first conductive paths D1. It should be noted that the metal layer 60 can be electrically connected to multiple first conductive paths D1. Since the metal layer 60 accumulates a large number of ions or electrons, setting only one first conductive path D1 may not be able to completely introduce the accumulated ions or electrons into the substrate 10. Therefore, in this embodiment, the metal layer 60 can be electrically connected to multiple first conductive paths D1, and the multiple first doped regions 701 are isolated by the isolation structure 103. Each bit line structure 20 is electrically connected to at least one second conductive path D2. The figure shows a second peripheral word line 502 electrically connected to two second conductive paths D2. It should be noted that the second peripheral word line 502 can be electrically connected to multiple second conductive paths D2. Because the second peripheral word line 502 accumulates a large number of ions or electrons, setting only one second conductive path D2 may not be sufficient to completely guide the accumulated ions or electrons into the substrate 10. Therefore, in this embodiment, the second peripheral word line 502 can be electrically connected to multiple second conductive paths D2. Multiple second doped regions 702 are isolated by an isolation structure 103. In this embodiment, both the first conducting structure 401 and the second conducting structure 402 are doped polysilicon, and both are N-type doped. The first doped region 701 and the second doped region 702 are P-type doped. The first conducting structure 401 and the first doped region 701 form a PN junction, and the second conducting structure 402 and the second doped region 702 also form a PN junction. The horizontal character line 51 is located above the vertical character line 30, and the first peripheral character line 501 is located above each first conductive structure 401. The horizontal character line 51 is electrically connected to the vertical character line 30, and the first peripheral character line 501 is electrically connected to each first conductive structure 401. A metal layer 60 is provided above the horizontal character line 51 and the first peripheral character line 501, and the metal layer 60 is electrically connected to the horizontal character line 51 and the first peripheral character line 501, respectively. The horizontal character line 51 and the first peripheral character line 501 are located at the same level. The metal layer 60 is electrically connected to the first peripheral character line 501 and the horizontal character line 51, respectively, through the first connecting through hole CT1 and the second connecting through hole CT2. The first peripheral character line 501 and the first conductive structure 401 are further provided with a first connecting structure 81, and the vertical character line 30 and the horizontal character line 51 are further provided with a second connecting structure 82. The first connecting structure 81 and the second connecting structure 82 are located at the same level. The first connecting structure 81 also includes a first contact structure 811 and a first transfer structure 812. The second connecting structure 82 also includes a second contact structure 821 and a second transfer structure 822.The second peripheral word line 502 is located above the plurality of second conductive structures 402 and extends above the plug structure 90. The second peripheral word line 502 is electrically connected to the plug structure 90 and the second conductive structure 402 respectively through the third connecting structure 83 and the fourth connecting structure 84. The third connecting structure 83 includes a third contact structure 831 and a third transfer structure 832, and the fourth connecting structure 84 includes a fourth contact structure 841 and a fourth transfer structure 842.

[0078] Figure 8 This is another schematic diagram of a semiconductor structure provided in the embodiments of this disclosure, and... Figure 7 The difference lies in the embodiment of this application, where both the first conducting structure 401 and the second conducting structure 402 are metals. The first doped region 701 includes a first sub-doped region 7011 and a second sub-doped region 7012, where the first sub-doped region 7011 is N-type doped and the second sub-doped region 7012 is P-type doped, forming a PN junction. The second doped region 702 includes a third sub-doped region 7021 and a fourth sub-doped region 7022, where the third sub-doped region 7021 is N-type doped and the fourth sub-doped region 7022 is P-type doped, forming a PN junction. Figure 7 The same parts will not be repeated here. In this embodiment, the metal layer 60 is electrically connected to at least one first conductive path D1, and the second peripheral word line 502 is electrically connected to at least one second conductive path D2, so that the electrons accumulated on the metal layer 60 and the second peripheral word line 502 can be more completely introduced into the substrate 10, reducing plasma etching damage and improving the yield and performance of semiconductor devices.

[0079] Figure 9 This is a top view of the peripheral area provided in an embodiment of this disclosure; please refer to the following for details. Figure 9 Taking the peripheral region 102 on one side of the active region 101 as an example, the peripheral region 102 may include multiple first doped regions 701. The multiple first doped regions 701 are parallel to each other and distributed in a strip shape. There are multiple isolation structures 103 spaced apart between the multiple first doped regions 701 along the extension direction of the first doped regions 701. The isolation structures 103 are distributed in a block-shaped spaced distribution because in 3D DRAM, due to the vertical stacking of multiple layers, the isolation structures 103 are distributed in a block-shaped spaced distribution in order to provide sufficient support. Figure 9 The blank areas not shown in the diagram can serve as supporting structures.

[0080] Figure 10 This is a schematic diagram of a 3D DRAM architecture provided in an embodiment of the present disclosure; as shown... Figure 10The 3D DRAM architecture shown includes a substrate 10, on which silicon pillars 100 are spaced apart along the Z and Y directions, as shown by the dashed box in the figure. Both ends of the silicon pillars 100 have a source (S) or a drain (D), i.e., S / D. Bitline structures (BL) are stacked along the Z direction and extend along the Y direction. One end of the S / D is connected to the BL, and the other end of the S / D is connected to a capacitor (CAP). Word line structures (WL) are perpendicular to the surface of the substrate 10 and spaced apart along the Y direction. The WL can be a fully encircling word line or a plate-shaped word line, which is not limited here. At least one end of the BL has a stepped structure 201. The WL and BL are arranged in a mesh pattern on the active region.

[0081] Figure 11 This is a schematic diagram of another 3D DRAM architecture provided in an embodiment of this disclosure; as shown below. Figure 11 The 3D DRAM architecture shown includes a substrate 10, on which silicon pillars 100 are spaced apart along the Z and Y directions, as shown by the dashed box in the figure. Both ends of the silicon pillars 100 have S / D; BL is stacked along the Y direction and extends along the Z direction. One end of the S / D is connected to the BL, and the other end of the S / D is connected to the CAP. WL extends parallel to the surface of the substrate 10 along the Y direction and is spaced apart along the Z direction. WL can be a full-wrap word line or a plate-shaped word line, which is not limited here. At least one end of the WL has a stepped structure 301. WL and BL are arranged in a mesh pattern on the active region.

[0082] Figure 10 and Figure 11 The difference lies in the layered structure. Figure 10 The middle BL is stacked along the Z direction, and the stepped structure 201 is provided at at least one end of the BL. Figure 11 The WL is stacked along the Z-direction, and the step structure 301 is disposed at at least one end of the WL. In other embodiments, the 3D DRAM architecture can also be configured in other forms, as long as the dynamic storage function can be realized, and it is not limited here. The technical solution in the embodiments of this application can be used for any 3D DRAM architecture. That is, as long as there is a PID effect in the semiconductor structure, regardless of whether the semiconductor structure is a two-dimensional architecture or a three-dimensional architecture, any three-dimensional architecture can be used to introduce ions or electrons into the substrate by setting a conductive path and through the forward conduction and reverse cutoff function of the PN junction, so as to reduce plasma etching damage.

[0083] Figure 12 A schematic diagram of a storage device provided in an embodiment of this disclosure; as shown Figure 12As shown, a memory device includes: a substrate 10, which includes an active region 101 and a peripheral region 102; a word line structure WL and a bit line structure BL arranged in a mesh on the active region 101. At least one end of the word line structure WL has a lead-out structure 50A, which is electrically connected to a conductive structure 40A in the peripheral region; a doped region 70A is also present in the substrate 10 below the conductive structure 40A, which has a PN junction or the doped region 70A and the conductive structure 40A form a PN junction; the lead-out structure 50A, the conductive structure 40A, and the doped region 70A constitute a conductive path A. At least one end of the bitline structure BL has a lead-out structure 50B, which is electrically connected to the conductive structure 40B in the peripheral region. The substrate 10 below the conductive structure 40B also has a doped region 70B, which contains a PN junction or forms a PN junction with the conductive structure 40B. The lead-out structure 50B, the conductive structure 40B, and the doped region 70B constitute a conductive path B. Figure 12 The bit line structure BL shown is stacked parallel to the surface of the substrate 10. At least one end of the bit line structure BL has a stepped structure 201 in a direction perpendicular to the substrate surface. The word line structure WL is perpendicular to the surface of the substrate 10 and electrically connected to the bit line structure BL. The substrate 10 also has silicon pillars 100 spaced apart along the Z and Y directions, as shown by the dashed box in the figure. Both ends of the silicon pillars 100 have a source or drain, i.e., S / D. The bit line structure BL is stacked along the Z direction and extends along the Y direction. One end of the S / D is connected to the BL, and the other end of the S / D is connected to the capacitor CAP. In this embodiment, the conduction structure 40A or 40B is doped polysilicon. The conduction structure 40A and the doped region 70A form a PN junction; the conduction structure 40B and the doped region 70B form a PN junction. The conduction structure 40A or 40B is N-type doped, and the doped region 70A or 70B is P-type doped. This application embodiment is an architecture in which the BL is stacked along the Z direction. In this 3D DRAM architecture, by setting an outgoing structure at at least one end of the WL or BL, and the outgoing structure is electrically connected to the conducting structure, and a doped region is set below the conducting structure, the conducting structure and the doped region form a PN junction, so that the charge accumulated during the process is unidirectionally introduced into the substrate through the conductive path, preventing the PID effect from affecting the memory and improving the performance of the memory.

[0084] Figure 13 This is a schematic diagram of another storage device provided in an embodiment of the present disclosure; as shown below. Figure 13As shown, a memory device includes: a substrate 10, which includes an active region 101 and a peripheral region 102; a word line structure WL and a bit line structure BL arranged in a mesh on the active region 101. At least one end of the word line structure WL has a lead-out structure 50A, which is electrically connected to a conductive structure 40A in the peripheral region; a doped region 70A is also present in the substrate 10 below the conductive structure 40A, which has a PN junction or the doped region 70A and the conductive structure 40A form a PN junction; the lead-out structure 50A, the conductive structure 40A, and the doped region 70A constitute a conductive path A. At least one end of the bitline structure BL has a lead-out structure 50B, which is electrically connected to the conductive structure 40B in the peripheral region. The substrate 10 below the conductive structure 40B also has a doped region 70B. The doped region 70B has a PN junction, or the doped region 70B and the conductive structure 40B form a PN junction. The lead-out structure 50B, the conductive structure 40B, and the doped region 70B constitute a conductive path B. Figure 13 The word line structure WL shown is stacked parallel to the surface of the substrate 10. At least one end of the word line structure WL has a stepped structure 301 along a direction perpendicular to the surface of the substrate 10. The bit line structure BL is perpendicular to the surface of the substrate 10 and electrically connected to the word line structure WL. The substrate 10 also has silicon pillars 100 spaced apart along both the Z and Y directions, as shown by the dashed box in the figure. Both ends of the silicon pillars 100 have S / D terminals. The word line structure WL is stacked along the Z direction and extends along the Y direction. One end of the S / D terminal is connected to the BL terminal, and the other end of the S / D terminal is connected to the CAP terminal. In this embodiment, the conduction structure 40A or 40B is doped polysilicon. The conduction structure 40A and the doped region 70A form a PN junction; the conduction structure 40B and the doped region 70B form a PN junction. The conduction structure 40A or 40B is N-type doped, and the doped region 70A or 70B is P-type doped. This application embodiment is an architecture in which WL is stacked along the Z direction. In this 3D DRAM architecture, by setting an outgoing structure at at least one end of WL or BL, and the outgoing structure is electrically connected to the conducting structure, and a doped region is set below the conducting structure, the conducting structure and the doped region form a PN junction, so that the charge accumulated during the process is unidirectionally introduced into the substrate through the conductive path, preventing the PID effect from affecting the memory and improving the performance of the memory.

[0085] Figure 14 This is a schematic diagram of another storage device provided in an embodiment of the present disclosure. Figure 14 and Figure 12The difference lies in the fact that the conductive structure 40A or 40B is metal, and the doped region 70A connected to WL includes a first sub-doped region 701A and a second sub-doped region 702A. The doping types of the first sub-doped region 701A and the second sub-doped region 702A are opposite. The first sub-doped region 701A is located below the second sub-doped region 702A. The first sub-doped region 701A and the second sub-doped region 702A form a PN junction. The first sub-doped region 701A is N-type doped and the second sub-doped region 702A is P-type doped. The doped region 70B connected to BL includes a first sub-doped region 701B and a second sub-doped region 702B. The first sub-doped region 701B and the second sub-doped region 702B have opposite doping types. The first sub-doped region 701B is located below the second sub-doped region 702B, and the first sub-doped region 701B and the second sub-doped region 702B form a PN junction; the first sub-doped region 701B is N-type doped, and the second sub-doped region 702B is P-type doped. Figure 12 The same parts will not be repeated. The embodiments of this application are of an architecture in which the BL is stacked along the Z direction. In this 3D DRAM architecture, an outgoing structure is provided at at least one end of the WL or BL, and the outgoing structure is electrically connected to the conductive structure. The conductive structure is metal. A doped region is provided below the conductive structure. The doped region includes a first sub-doped region and a second sub-doped region. The first sub-doped region and the second sub-doped region form a PN junction, so that the charge accumulated during the process is unidirectionally introduced into the substrate through the conductive path, preventing the PID effect from affecting the memory and improving the performance of the memory.

[0086] Figure 15 This is a schematic diagram of another storage device provided in an embodiment of the present disclosure. Figure 15 and Figure 13 The difference lies in the following: The conductive structure 40A or 40B is metallic. The doped region 70A connected to WL includes a first sub-doped region 701A and a second sub-doped region 702A. The doping types of the first sub-doped region 701A and the second sub-doped region 702A are opposite. The first sub-doped region 701A is located below the second sub-doped region 702A, and the first sub-doped region 701A and the second sub-doped region 702A form a PN junction. The first sub-doped region 701A is N-type doped, and the second sub-doped region 702A is P-type doped. The doped region 70B connected to BL includes a first sub-doped region 701B and a second sub-doped region 702B. The doping types of the first sub-doped region 701B and the second sub-doped region 702B are opposite. The first sub-doped region 701B is located below the second sub-doped region 702B, and the first sub-doped region 701B and the second sub-doped region 702B form a PN junction. The first sub-doped region 701B is N-type doped, and the second sub-doped region 702B is P-type doped. and Figure 13The same parts will not be repeated. The embodiments of this application are architectures in which WL is stacked along the Z direction. In this 3D DRAM architecture, an outgoing structure is provided at at least one end of WL or BL, and the outgoing structure is electrically connected to the conductive structure. The conductive structure is metal, and a doped region is provided below the conductive structure. The doped region includes a first sub-doped region and a second sub-doped region. The first sub-doped region and the second sub-doped region form a PN junction, so that the charge accumulated during the process is unidirectionally introduced into the substrate through the conductive path, preventing the PID effect from affecting the memory and improving the performance of the memory.

[0087] Figure 14 and Figure 15 The difference lies in the architecture of 3D DRAM. Figure 14 The middle layer is a BL architecture stacked along the Z direction. Figure 15 This is an architecture where WL and BL are stacked along the Z-direction. Regardless of the 3D DRAM architecture, as long as a lead-out structure is provided at at least one end of WL or BL, and the lead-out structure is electrically connected to the conductive structure, and a doped region is provided below the conductive structure, with a PN junction within the doped region or the doped region and the conductive structure forming a PN junction, the charge accumulated during the process can be unidirectionally conducted into the substrate through a conductive path. This can prevent the PID effect from affecting the memory and improve memory performance. This embodiment does not limit the specific 3D DRAM architecture. In addition, other contact structures are also included between the lead-out structure and WL or BL, and between the conductive structure and BL or WL, which are not limited here, as long as the conduction function can be achieved.

[0088] The various semiconductor structures illustrated in this specific embodiment can be used in electronic devices with storage functions. These electronic devices can be terminal devices, such as mobile phones, tablets, and smart bracelets, or personal computers (PCs), servers, workstations, etc. The storage function in these electronic devices can be implemented using the following types of memory: Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (PCM), Magnetic Random Access Memory (MRAM), or Resistive Random Access Memory (RRAM).

[0089] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, the substrate comprising an active region and a peripheral region; Bitline structures are stacked in the active region and parallel to the substrate surface, and at least one end of the bitline structure has a stepped structure in a direction perpendicular to the substrate surface. Vertical character lines are perpendicular to the surface of the substrate and electrically connected to the bit line structure. A first conductive structure is located in the peripheral area. One end of the first conductive structure is connected to the base, and the other end of the first conductive structure is flush with the top surface of the vertical character line. The horizontal character line is located above the vertical character line, the first outer character line is located above the first conductive structure, the horizontal character line is electrically connected to the vertical character line, and the first outer character line is electrically connected to the first conductive structure. A metal layer is also provided above the horizontal character line and the first peripheral character line, and the metal layer is electrically connected to the horizontal character line and the first peripheral character line respectively. Below the first conductive structure, there is a first doped region located within the substrate. The first doped region contains a PN junction, or the first doped region and the first conductive structure form a PN junction.

2. The semiconductor structure according to claim 1, characterized in that, The first peripheral word line, the first conductive structure, and the first doped region together constitute a first conductive path, and the metal layer is electrically connected to at least one of the first conductive paths.

3. The semiconductor structure according to claim 1, characterized in that, The first conducting structure is doped polysilicon, and the doped polysilicon and the first doped region form the PN junction; the first conducting structure is N-type doped, and the first doped region is P-type doped.

4. The semiconductor structure according to claim 1, characterized in that, The first conductive structure is metal, and the first doped region includes a first sub-doped region and a second sub-doped region. The doping type of the first sub-doped region is opposite to that of the second sub-doped region. The first sub-doped region is located below the second sub-doped region, and the first sub-doped region and the second sub-doped region constitute the PN junction. The first sub-doped region is N-type doped and the second sub-doped region is P-type doped.

5. The semiconductor structure according to claim 1, characterized in that, The horizontal character line and the first peripheral character line are located at the same level; the metal layer is electrically connected to the first peripheral character line and the horizontal character line respectively through the first connecting through hole and the second connecting through hole.

6. The semiconductor structure according to claim 1, characterized in that, The first peripheral character line and the first conductive structure also have a first connecting structure, and the vertical character line and the horizontal character line also have a second connecting structure. The first connecting structure and the second connecting structure are located at the same level. The first connecting structure also includes a first contact structure and a first transfer structure. The second connecting structure also includes a second contact structure and a second transfer structure.

7. The semiconductor structure according to any one of claims 1-6, characterized in that, It also includes a second conductive structure, which is located in the peripheral area. One end of the second conductive structure is connected to the substrate, and the other end of the second conductive structure is flush with the top surface of the vertical character line. Below the second conductive structure, there is a second doped region located within the substrate. The second doped region contains a PN junction, or the second doped region and the second conductive structure form a PN junction.

8. The semiconductor structure according to claim 7, characterized in that, The second conducting structure is doped polysilicon, and the doped polysilicon and the second doped region form the PN junction; the second conducting structure is N-type doped, and the second doped region is P-type doped.

9. The semiconductor structure according to claim 7, characterized in that, The second conductive structure is metal, and the second doped region includes a third sub-doped region and a fourth sub-doped region. The third sub-doped region and the fourth sub-doped region have opposite doping types. The third sub-doped region is located below the fourth sub-doped region. The third sub-doped region and the fourth sub-doped region form the PN junction. The third sub-doped region is N-type doped and the fourth sub-doped region is P-type doped.

10. The semiconductor structure according to any one of claims 8-9, characterized in that, A plug structure is provided at one end of the bit line structure near the second conductive structure. The plug structure is electrically connected to the bit line structure, and the top of the plug structure is flush with the top surface of the vertical character line.

11. The semiconductor structure according to claim 10, characterized in that, It also includes a second peripheral word line, which is located above the second conductive structure and extends above the plug structure. The second peripheral word line is electrically connected to the second conductive structure and the plug structure, respectively. The first outer character line and the second outer character line are located at the same level.

12. The semiconductor structure according to claim 11, characterized in that, The second conductive structure and the second doped region together constitute the second conductive path, and the second peripheral word line is electrically connected to at least one of the second conductive paths.

13. The semiconductor structure according to claim 11, characterized in that, A third connecting structure is provided between the plug structure and the second peripheral word line, and a fourth connecting structure is provided between the second peripheral word line and the second conductive structure. The third connecting structure and the fourth connecting structure are located at the same level. The third connection structure further includes a third contact structure and a third transfer structure, and the fourth connection structure further includes a fourth contact structure and a fourth transfer structure.

14. A storage device, characterized in that, include: A substrate, the substrate comprising an active region and a peripheral region; The word line structure and bit line structure are arranged in a mesh on the active region; At least one end of the word line structure and / or the bit line structure has a lead-out structure, which is electrically connected to the conductive structure of the peripheral area; The substrate beneath the conductive structure also has a doped region, which has a PN junction or the doped region and the conductive structure form a PN junction. The lead-out structure, the conductive structure, and the doped region constitute a conductive path.

15. The storage device according to claim 14, characterized in that, The bit line structure is stacked parallel to the substrate surface, and at least one end of the bit line structure has a stepped structure in a direction perpendicular to the substrate surface; The word line structure is perpendicular to the substrate surface and is electrically connected to the bit line structure.

16. The storage device according to claim 14, characterized in that, The character line structure is stacked parallel to the substrate surface, and at least one end of the character line structure has a stepped structure in a direction perpendicular to the substrate surface; The bit line structure is perpendicular to the substrate surface and is electrically connected to the word line structure.

17. The storage device according to any one of claims 15-16, characterized in that, The conducting structure is doped polysilicon, and the doped polysilicon and the doped region form the PN junction; the conducting structure is N-type doped, and the doped region is P-type doped.

18. The storage device according to any one of claims 15-16, characterized in that, The conductive structure is metal, and the doped region includes a first sub-doped region and a second sub-doped region. The doping type of the first sub-doped region is opposite to that of the second sub-doped region. The first sub-doped region is located below the second sub-doped region. The first sub-doped region and the second sub-doped region constitute the PN junction. The first sub-doped region is N-type doped and the second sub-doped region is P-type doped.

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