Enhanced GaN HEMT device regulated and controlled by nanopillar array and preparation method thereof

Abstract

The invention discloses an enhanced GaN HEMT (High Electron Mobility Transistor) device regulated and controlled by a nanorod array and a preparation method thereof. The device comprises a substrate layer, a nucleating layer, a buffer layer, a channel layer and a barrier layer which are stacked in sequence, a source electrode, a p-GaN gate, a p-GaN nanorod array and a drain electrode are sequentially arranged on the barrier layer at intervals; the p-GaN nanorod array comprises two columns of p-GaN nanorods which are distributed at intervals along a first direction, and each column of p-GaN nanorods comprises a plurality of arranged p-GaN nanorods; the passivation layer covers the barrier layer, the p-GaN gate and the p-GaN nanorod array, and a gate groove is formed in the passivation layer; and the gate covers the p-GaN gate and the passivation layer right above the p-GaN nanorod array and fills the gate groove. The invention can actively regulate and control the electric field distribution of one side area of the grid close to the drain, inhibits the electric field concentration phenomenon at the edge of the grid, improves the breakdown voltage of the device, and enhances the reliability and stability of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to an enhanced GaNHEMT device controlled by a nanopillar array and its fabrication method. Background Technology

[0002] In recent years, GaN, as a representative of third-generation wide-bandgap semiconductor materials, has shown great development potential in the field of power electronics due to its excellent material properties such as large bandgap, high breakdown field strength, and fast saturated electron drift velocity. At the AlGaN / GaN heterojunction interface, a two-dimensional electron gas with high concentration and high mobility is formed due to polarization. However, conventional GaN HEMT devices based on this structure are naturally depletion-mode. Considering circuit safety and energy saving, enhancement-mode GaNHEMT devices have become essential. Among them, p-GaN gate enhancement-mode HEMT devices have become the mainstream solution for realizing enhancement-mode devices due to their simple structure, stable threshold voltage, and high reliability. However, in p-GaN gate enhancement-mode HEMT devices, when the device is in the off state, an abnormally high electric field strength occurs in the edge region between the gate and drain (especially on the side of the gate closer to the drain). This problem of concentrated electric field at the gate edge easily leads to premature breakdown of the device, severely restricting its breakdown voltage performance, reliability, and long-term operational stability.

[0003] Currently, existing technologies for reducing the electric field concentration at the gate edge of p-GaN gate enhancement HEMT devices generally have several limitations. Regarding gate structure optimization, for example, edge rounding requires extremely high precision in photolithography and processes. This not only significantly increases manufacturing costs and yield risks, but excessive structural modification may also weaken the gate's control over the channel, and some complex gate structures may even introduce new electric field concentration points. While field plate technology can effectively disperse the electric field, its introduction usually significantly increases parasitic capacitance, leading to a decrease in device switching speed and affecting high-frequency performance. Simultaneously, the end of the field plate itself may become a new electric field peak point, and defects in the added dielectric layer can cause device reliability issues. Modifying the drift region, such as using gradient doping, can adjust the electric field distribution, but its process window is narrow, repeatability control is difficult, and it often exacerbates the inherent contradiction between on-resistance and breakdown voltage, making it difficult to coordinate device performance optimization. Furthermore, composite structural solutions combining multiple technologies face challenges such as complex design parameter coupling, long optimization cycles, and poor process integration compatibility. The limitations of these existing methods collectively restrict further performance breakthroughs for p-GaN gate-enhanced HEMT devices in high-voltage applications, making it difficult to achieve an ideal balance between improving withstand voltage and maintaining high-speed switching characteristics.

[0004] Therefore, a new technical solution is urgently needed to overcome the shortcomings of existing technologies, significantly reduce the electric field concentration effect at the gate edge, and improve the device's withstand voltage performance. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides an enhanced GaN HEMT device controlled by a nanopillar array and its fabrication method.

[0006] The technical problem to be solved by this invention is achieved through the following technical solution: An enhancement-mode GaN HEMT device modulated by a nanopillar array includes a substrate, an epitaxial structure, a p-GaN gate, a p-GaN nanopillar array, a source, a drain, a gate, and a passivation layer; wherein, The epitaxial structure is located on the substrate layer; the epitaxial structure includes a nucleation layer, a buffer layer, a channel layer and a barrier layer stacked sequentially from bottom to top; The source electrode, the p-GaN gate, the p-GaN nanopillar array, and the drain electrode are sequentially spaced along a first direction on the barrier layer; the p-GaN nanopillar array includes two rows of p-GaN nanopillars spaced along the first direction; each row of p-GaN nanopillars includes multiple p-GaN nanopillars arranged along a second direction; the second direction is perpendicular to the first direction. The passivation layer covers the barrier layer between the source and the drain, and also covers the p-GaN gate and the p-GaN nanopillar array; the passivation layer above the p-GaN gate has a gate groove, and the bottom of the gate groove is located within the passivation layer; The gate covers the passivation layer directly above the p-GaN gate and the p-GaN nanopillar array, and fills the gate recess.

[0007] Optionally, the width of the p-GaN nanopillar array is less than or equal to the width of the p-GaN gate; the length of the p-GaN nanopillar is 0.1 μm to 2 μm; the height of the p-GaN nanopillar is less than the thickness of the p-GaN gate; and the spacing between adjacent p-GaN nanopillars is 1 μm to 2 μm.

[0008] Optionally, the thickness of the p-GaN gate is 70nm~120nm; the p-GaN gate is spaced 1μm~2μm from the nearest row of p-GaN nanopillars in the first direction.

[0009] Optionally, the substrate layer is made of any one of silicon, sapphire, silicon carbide, gallium nitride, and diamond self-supporting substrates.

[0010] Optionally, the nucleation layer is made of AlN superlattice and has a thickness of 0.5 nm to 2 nm.

[0011] Optionally, the buffer layer is made of GaN or AlGaN and has a thickness of 0.2 μm to 1 μm.

[0012] Optionally, the channel layer is made of GaN and has a thickness of 100nm~300nm.

[0013] Optionally, the barrier layer is made of AlGaN, InAlN, AlN, or InGaN, and has a thickness of 10nm to 30nm.

[0014] Optionally, the source and drain are both made of Ti / Al / Ni / Au or Ti / Al / Ti / Au multilayer metal; the gate is made of Ni / Au or Ni / TiN multilayer metal.

[0015] This invention also provides a method for fabricating an enhancement-mode GaN HEMT device controlled by a nanopillar array, comprising: Step 1: Epitaxially grow a core layer, a buffer layer, a channel layer, a barrier layer, and a p-GaN layer sequentially on the substrate to form an epitaxial structure; Step 2: Define a p-GaN gate region on the p-GaN layer, and etch the p-GaN layer outside the p-GaN gate region to a preset depth; Step 3: Deposit a Si3N4 hard mask on the surface of the current sample, and form an etching mask on the hard mask through photolithography and etching processes; Step 4: Using the etching mask as a barrier layer, etch the p-GaN layer outside the p-GaN gate region to form a p-GaN gate directly below the p-GaN gate region, and form two rows of p-GaN nanopillars on one side of the p-GaN gate. Step 5: Remove the etching mask; Step 6: Obtain patterned device mesas using photolithography and perform mesas isolation; Step 7: Define the source and drain regions on the upper surface of the barrier layer using photolithography, and deposit metal stacks in the source and drain regions to form the source and drain. Step 8: Deposit a passivation layer on the surface of the current sample; Step 9: Etch the passivation layer directly above the p-GaN gate to form a gate recess, the bottom of which is located within the passivation layer; Step 10: Obtain a patterned gate pattern through photolithography. Deposit gate metal over the gate groove, the p-GaN gate, and the two rows of p-GaN nanopillars, and then perform metal stripping to form the gate.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The nanopillar array-controlled enhancement-mode GaN HEMT device provided by this invention effectively solves the p-GaN gate enhancement problem by introducing a p-GaN nanopillar array in the region adjacent to and close to the drain. The core issue in GaN gate-enhanced GaN HEMTs is the concentration of the electric field at the gate edge. This p-GaN nanopillar array utilizes p The depletion effect of GaN material on the two-dimensional electron gas of heterojunction actively modulates and homogenizes the electric field distribution in the region near the drain of the gate, significantly suppressing the electric field concentration phenomenon near the drain edge of the gate, thereby improving the breakdown voltage of the device and enhancing the reliability and long-term stability of the device under high-voltage operating conditions.

[0017] 2. This invention, through the spatial distribution and structural design of the p-GaN nanopillar array, effectively disperses and balances the peak electric field in the gate edge region, preventing excessive concentration of the electric field in a single area. This results in a smoother and more uniform electric field distribution across the entire gate edge, fundamentally enhancing the breakdown voltage. Furthermore, the optimized distribution of the nanopillar array, while achieving electric field modulation, avoids excessive depletion of the two-dimensional electron gas below the gate edge, minimizing adverse effects on key performance parameters such as the on-state saturation current and maintaining the device's excellent conduction characteristics.

[0018] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of an enhanced GaN HEMT device regulated by a nanopillar array provided in an embodiment of the present invention; Figure 2 This is a top view of an enhanced GaN HEMT device regulated by a nanopillar array provided in an embodiment of the present invention; Figure 3 This is a flowchart of a method for fabricating an enhanced GaN HEMT device controlled by a nanopillar array, as provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of the fabrication process of an enhanced GaN HEMT device regulated by a nanopillar array, provided in an embodiment of the present invention. Figure label: 1. Substrate layer; 2. Nucleation layer; 3. Buffer layer; 4. Channel layer; 5. Barrier layer; 6. p-GaN gate; 7. p-GaN nanopillar array; 8. Source; 9. Drain; 10. Passivation layer; 11. Gate; 61. p-GaN layer. Detailed Implementation

[0020] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0021] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following, in conjunction with the accompanying drawings and specific embodiments, provides a detailed description of the enhanced GaN HEMT device controlled by a nanopillar array and its fabrication method proposed in this invention.

[0022] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0023] The nanopillar array-controlled enhancement GaN HEMT device provided in this embodiment of the invention, see [link to relevant documentation]. Figure 1 and Figure 2 It includes: a substrate layer 1, an epitaxial structure, a p-GaN gate 6, a p-GaN nanopillar array 7, a source 8, a drain 9, a gate 11, and a passivation layer 10.

[0024] The epitaxial structure is located on the substrate layer 1. The epitaxial structure includes a nucleation layer 2, a buffer layer 3, a channel layer 4, and a barrier layer 5 stacked sequentially from bottom to top; A source 8, a p-GaN gate 6, a p-GaN nanopillar array 7, and a drain 9 are sequentially spaced along a first direction on the barrier layer 5; the p-GaN nanopillar array 7 includes two rows of p-GaN nanopillars spaced along the first direction; each row of p-GaN nanopillars includes multiple p-GaN nanopillars arranged along a second direction; here, the second direction is perpendicular to the first direction. Passivation layer 10 covers barrier layer 5 between source 8 and drain 9, and covers p-GaN gate 6 and p-GaN nanopillar array 7; passivation layer 10 above p-GaN gate 6 has gate groove, the bottom of gate groove is located inside passivation layer 10; gate 11 covers passivation layer 10 directly above p-GaN gate 6 and p-GaN nanopillar array 7, and fills gate groove.

[0025] For details, see Figure 1 and Figure 2On the barrier layer 5, a source 8, a p-GaN gate 6, a p-GaN nanopillar array 7, and a drain 9 are sequentially arranged from one end of the barrier layer 5 to the other. The source 8 and drain 9 are located at the two ends, and the p-GaN nanopillar array 7 is adjacent to the p-GaN gate 6. The p-GaN nanopillar array 7 includes two rows of p-GaN nanopillars spaced apart along a first direction, and each row of p-GaN nanopillars includes multiple p-GaN nanopillars arranged along a second direction. The first direction is the direction of the line connecting the source 8 and the drain 9.

[0026] In one alternative implementation, the width of the p-GaN nanopillar array is less than or equal to the width of the p-GaN gate; the length of the p-GaN nanopillars is 0.1 μm to 2 μm, the height of the p-GaN nanopillars is less than the thickness of the p-GaN gate, and the spacing between adjacent p-GaN nanopillars is 1 μm to 2 μm.

[0027] Preferably, the length of a single p-GaN nanopillar is 200 nm, the width is 200 nm, and the height is 40 nm; the spacing between adjacent p-GaN nanopillars is 1 μm.

[0028] It should be noted that the width of the p-GaN nanopillar array and the width of the p-GaN gate refer to the dimensions of the p-GaN nanopillar array and the p-GaN gate along the first direction. The spacing between the p-GaN nanopillars and their adjacent p-GaN nanopillars is 1 μm to 2 μm.

[0029] In one alternative implementation, the thickness of the p-GaN gate 6 is 70 nm to 120 nm; the p-GaN gate 6 is spaced 1 μm to 2 μm from the nearest row of p-GaN nanopillars in the first direction.

[0030] Optionally, both the p-GaN nanopillars and the p-GaN gate 6 are made of p-type doped GaN. The dopant ion can be Mg, with a doping concentration of 1 × 10⁻⁶. 17 cm -3 ~2×10 20 cm -3 .

[0031] It is understood that this invention effectively modulates the abnormal increase in electric field that occurs at the edge region of the gate 11 near the drain 9 by introducing a p-GaN nanopillar array 7 in the region adjacent to the p-GaN gate 6 and close to the drain 9. It utilizes the depletion effect of the p-GaN material on the two-dimensional electron gas in the heterojunction to achieve a uniform electric field distribution, effectively solving the problem of p-GaN gate 11 near the drain 9. The core issue in GaN gate-enhanced GaN HEMTs is the concentration of the electric field at the gate edge.

[0032] In one alternative implementation, the substrate 1 is made of any one of silicon, sapphire, silicon carbide, gallium nitride, and diamond self-supporting substrates.

[0033] In one alternative implementation, the nucleation layer 2 is made of an AlN superlattice with a thickness of 0.5 nm to 2 nm.

[0034] In one alternative implementation, the buffer layer 3 can be made of unintentionally doped GaN or AlGaN. The thickness of the buffer layer 3 is preferably 0.2 μm to 1 μm. It is understood that the buffer layer 3 can further filter defects and achieve a smooth transition from the nucleation layer 2 to the channel layer 4, ensuring that the channel layer 4 has high crystal quality.

[0035] In one alternative implementation, the channel layer 4 is made of unintentionally doped GaN, and its thickness is preferably 100 nm to 300 nm. This channel layer 4 is the core region for the formation and transport of two-dimensional electron gas, and its excellent crystal quality and thickness are crucial for obtaining high electron mobility.

[0036] In one alternative implementation, the barrier layer 5 is made of AlGaN, InAlN, AlN, or InGaN, and its thickness is preferably 10 nm to 30 nm. For example, when AlGaN is used, the atomic percentage content of the aluminum component is preferably between 10% and 30%.

[0037] Understandably, through band engineering, the barrier layer 5 forms a heterojunction with the underlying channel layer 4, thereby inducing a high-concentration, high-mobility two-dimensional electron gas at the interface.

[0038] In one implementation, the passivation layer 10 is a Si3N4 passivation layer, and the thickness of the passivation layer 10 is preferably 10nm~300nm.

[0039] In one alternative implementation, the source 8 and drain 9 are both made of Ti / Al / Ni / Au or Ti / Al / Ti / Au multilayer metal; the gate 11 is made of Ni / Au or Ni / TiN multilayer metal.

[0040] Here, the source 8 and drain 9 are ohmic contact electrodes, while the gate 11 covers the p-GaN gate 6 and the passivation layer 10 directly above the p-GaN nanopillar array 7, and fills the gate groove. Figure 1 As shown, the bottom of the gate recess is located within the passivation layer 10, and a portion of the passivation layer 10 is still retained below the gate recess as a gate under dielectric layer.

[0041] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The nanopillar array-controlled enhancement-mode GaN HEMT device provided by this invention effectively solves the p-GaN gate enhancement problem by introducing a p-GaN nanopillar array in the region adjacent to and close to the drain. The core issue in GaN gate-enhanced GaN HEMTs is the concentration of the electric field at the gate edge. This p-GaN nanopillar array utilizes p The depletion effect of GaN material on the two-dimensional electron gas of heterojunction actively modulates and homogenizes the electric field distribution in the region near the drain of the gate, significantly suppressing the electric field concentration phenomenon near the drain edge of the gate, thereby improving the breakdown voltage of the device and enhancing the reliability and long-term stability of the device under high-voltage operating conditions.

[0042] 2. This invention, through the spatial distribution and structural design of the p-GaN nanopillar array, effectively disperses and balances the peak electric field in the gate edge region, preventing excessive concentration of the electric field in a single area. This results in a smoother and more uniform electric field distribution across the entire gate edge, fundamentally enhancing the breakdown voltage. Furthermore, the optimized distribution of the nanopillar array, while achieving electric field modulation, avoids excessive depletion of the two-dimensional electron gas below the gate edge, minimizing adverse effects on key performance parameters such as the on-state saturation current and maintaining the device's excellent conduction characteristics.

[0043] Based on the same inventive concept as the enhanced GaN HEMT device regulated by the aforementioned nanopillar array, this invention also provides a method for its fabrication, see [link to details]. Figure 3 The preparation method includes the following steps: Step 1: Epitaxially grow a core layer, a buffer layer, a channel layer, a barrier layer, and a p-GaN layer sequentially on the substrate to form an epitaxial structure.

[0044] For example, see Figure 4 In sub-figure (a), a metal-organic chemical vapor deposition (MOCVD) process can be used to epitaxially grow a nucleation layer 2, a buffer layer 3, a channel layer 4, a barrier layer 5, and a p-GaN layer 61 sequentially on a substrate layer 1. The substrate can be selected from silicon, sapphire, silicon carbide, gallium nitride, or diamond self-supporting substrates; the nucleation layer 2 is made of AlN superlattice with a thickness of 0.5 nm to 2 nm; the buffer layer 3 is made of GaN or AlGaN with a thickness of 0.2 μm to 1 μm; the channel layer 4 is made of GaN with a thickness of 100 nm to 300 nm; the barrier layer 5 is made of AlGaN, InAlN, AlN, or InGaN with a thickness of 10 nm to 30 nm; and the p-GaN layer 61 is made of p-type doped GaN. The dopant ion can be Mg, with a doping concentration of 1 × 10⁻⁶. 17 cm -3 ~2×10 20 cm -3The thickness of the p-GaN layer 61 is preferably 70 nm to 120 nm. Of course, the core layer 2, buffer layer 3, channel layer 4, barrier layer 5 and p-GaN layer 61 can also be epitaxially grown sequentially on the substrate layer 1 by other methods, and the embodiments of the present invention do not limit this.

[0045] Specifically, in this embodiment, the thickness of the p-GaN layer 61 is 100 nm.

[0046] Step 2: Define the p-GaN gate region on the p-GaN layer, and etch the p-GaN layer outside the p-GaN gate region to a preset depth.

[0047] For example, see Figure 4 In sub-figure (b), a patterned photoresist mask is formed on the surface of p-GaN layer 61 using photolithography to define the p-GaN gate region. Then, inductively coupled plasma (ICP) etching is used to etch the p-GaN layer 61 outside the p-GaN gate region to a depth of 60 nm, ensuring that the remaining depth of the p-GaN layer 61 outside the p-GaN gate region is equal to the height of the p-GaN nanopillar. In this step, the etching gas can be selected from at least one of chlorine-based, fluorine-based, Ar, N2, or O2.

[0048] Step 3: Deposit a Si3N4 hard mask on the surface of the current sample, and form an etch mask on the hard mask through photolithography and etching processes.

[0049] For example, see Figure 4 In sub-image (c), a Si3N4 thin film with a thickness of approximately 100 nm was deposited as a hard mask on the sample surface after step two treatment using plasma chemical vapor deposition. Subsequently, photoresist was coated on this hard mask and photolithography was performed to form the patterns of p-GaN nanopillar array 7 and p-GaN gate 6. Next, using the photoresist as a mask, inductively coupled plasma etching was used to etch the hard mask to form the etching mask for subsequent etching of p-GaN nanopillar array 7 and p-GaN gate 6.

[0050] Step 4: Using an etching mask as a barrier layer, etch the p-GaN layer outside the p-GaN gate region to form a p-GaN gate directly below the p-GaN gate region, and form two rows of p-GaN nanopillars on one side of the p-GaN gate.

[0051] For example, see Figure 4In sub-figure (d), the p-GaN layer 61 is etched using inductively coupled plasma etching (ICP-ALT) with the etching mask formed in step three as a barrier layer. Specifically, the thinned region from step two (the remaining p-GaN layer 61 after etching to a depth of 60 nm) is further etched downwards by approximately 40 nm, completely removing the portion of this region not covered by the etching mask (exposing the surface of barrier layer 5). This forms the p-GaN gate 6 and two independent rows of p-GaN nanopillars located directly below the p-GaN gate region. Here, the two rows of p-GaN nanopillars are located on one side of the p-GaN gate 6, with a 1 μm gap between the p-GaN gate 6 and its nearest adjacent row of p-GaN nanopillars. Each p-GaN nanopillar is 200 nm long, 200 nm wide, and 40 nm high, with a spacing of approximately 1 μm between adjacent nanopillars.

[0052] After etching, the sample is immersed in an organic base tetramethylammonium hydroxide solution to modify the sidewall morphology of the p-GaN nanopillars and p-GaN gate 6 and remove etching damage. The etching gas used in this step can be at least one of chlorine-based, fluorine-based, Ar, N2, or O2.

[0053] Step 5: Remove the etching mask.

[0054] Specifically, N-methylpyrrolidone (NMP) solution is first used to remove the residual photoresist on the current sample surface, and then buffered oxide etchant (BOE) is used to remove the etch mask.

[0055] Step 6: Obtain patterned device mesa through photolithography and perform mesa isolation.

[0056] For example, see Figure 4 In sub-image (e), photoresist is coated on the sample surface, and the active region (i.e., mesa) of the device is defined by photolithography. Then, mesa isolation is achieved using inductively coupled plasma etching (ICP-E) technology, with the etching depth exceeding the sum of the thicknesses of the barrier layer 5 and the channel layer 4, to achieve electrical isolation between devices. The etching gas can be selected from at least one of chlorine-based, fluorine-based, Ar, N2, or O2. It should be noted that reactive ion etching (RIE) technology can also be used for mesa isolation; this embodiment of the invention does not limit this approach.

[0057] Step 7: Define the source and drain regions on the upper surface of the barrier layer using photolithography, and deposit metal stacks in the source and drain regions to form the source and drain.

[0058] For example, see Figure 4In sub-figure (f), the source 8 and drain 9 regions are defined on the upper surface of barrier layer 5 using photolithography. Subsequently, an ohmic contact metal stack, either Ti / Al / Ni / Au or Ti / Al / Ti / Au, is deposited in the source and drain regions. After deposition, metal lift-off is performed to form the source 8 and drain 9 metal electrodes. Then, high-temperature thermal annealing at above 800°C for 15-60 seconds in a nitrogen atmosphere alloys the metal with the semiconductor, thereby obtaining a low-resistance ohmic contact.

[0059] It should be noted that the source 8 is located near the p-GaN gate 6, and the drain 9 is located near the p-GaN nanopillar array 7.

[0060] Step 8: Deposit a passivation layer on the surface of the current sample.

[0061] For example, see Figure 4 In the (g) sub-image, a 100 nm thick Si3N4 thin film is deposited on the surface of the current sample as a passivation layer 10 using plasma chemical vapor deposition.

[0062] Step 9: Etch the passivation layer directly above the p-GaN gate to form a gate groove, with the bottom of the gate groove located within the passivation layer.

[0063] For example, see Figure 4 In the (h) sub-image, the gate 11 pattern is defined on the passivation layer 10 using photolithography. Then, inductively coupled plasma etching or reactive ion etching is used to etch the passivation layer 10 below the gate 11, controlling the etching depth to be less than the thickness of the passivation layer 10, so that a groove is formed directly above the p-GaN gate 6, and a passivation layer 10 of about 10 nm thickness is still retained below the bottom of the groove as the under-gate dielectric layer. The etching gas can be selected from at least one of chlorine-based, fluorine-based, Ar, N2, or O2.

[0064] Step 10: Obtain a patterned gate pattern through photolithography. Deposit gate metal on the gate groove, the p-GaN gate, and the two rows of p-GaN nanopillars, and then perform metal lift-off to form the gate.

[0065] For example, see [link to previous article] Figure 4 In the (h) sub-figure, photoresist is spin-coated onto the sample surface after step nine, and a patterned photoresist mask is formed by photolithography to cover the gate trench and its surrounding area (including the underlying p-GaN gate 6 and the two rows of p-GaN nanopillars). Subsequently, a gate metal layer is deposited, which is a Ni / Au or Ni / TiN stacked metal. Finally, metal lift-off is performed to form gate 11.

[0066] The fabrication method for enhanced GaN HEMT devices controlled by nanopillar arrays provided in this invention is compatible with the existing process flow for p-GaN gate HEMT devices. Neither material growth nor selective etching of the p-GaN material requires special process steps. While significantly improving the device's breakdown voltage performance, this technical solution ensures the feasibility and practicality of large-scale production.

[0067] Compared with existing technologies, the advantages of the enhanced GaN HEMT device regulated by the nanopillar array fabricated using this method are as follows: 1. The nanopillar array-controlled enhancement-mode GaN HEMT device provided by this invention effectively solves the p-GaN gate enhancement problem by introducing a p-GaN nanopillar array in the region adjacent to and close to the drain. The core issue in GaN gate-enhanced GaN HEMTs is the concentration of the electric field at the gate edge. This p-GaN nanopillar array utilizes p The depletion effect of GaN material on the two-dimensional electron gas of heterojunction actively modulates and homogenizes the electric field distribution in the region near the drain of the gate, significantly suppressing the electric field concentration phenomenon near the drain edge of the gate, thereby improving the breakdown voltage of the device and enhancing the reliability and long-term stability of the device under high-voltage operating conditions.

[0068] 2. This invention, through the spatial distribution and structural design of the p-GaN nanopillar array, effectively disperses and balances the peak electric field in the gate edge region, preventing excessive concentration of the electric field in a single area. This results in a smoother and more uniform electric field distribution across the entire gate edge, fundamentally enhancing the breakdown voltage. Furthermore, the optimized distribution of the nanopillar array, while achieving electric field modulation, avoids excessive depletion of the two-dimensional electron gas below the gate edge, minimizing adverse effects on key performance parameters such as the on-state saturation current and maintaining the device's excellent conduction characteristics.

[0069] In the description of this invention, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0070] In the description of this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0071] In the description of this invention, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0072] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.

[0073] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0074] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0075] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A nanopillar array-controlled enhancement-mode GaN HEMT device, characterized in that, It includes a substrate layer, an epitaxial structure, a p-GaN gate, a p-GaN nanopillar array, a source, a drain, a gate, and a passivation layer; among which, The epitaxial structure is located on the substrate layer; the epitaxial structure includes a nucleation layer, a buffer layer, a channel layer and a barrier layer stacked sequentially from bottom to top; The source electrode, the p-GaN gate, the p-GaN nanopillar array, and the drain electrode are sequentially spaced along a first direction on the barrier layer; the p-GaN nanopillar array includes two rows of p-GaN nanopillars spaced along the first direction; each row of p-GaN nanopillars includes multiple p-GaN nanopillars arranged along a second direction; the second direction is perpendicular to the first direction. The passivation layer covers the barrier layer between the source and the drain, and also covers the p-GaN gate and the p-GaN nanopillar array; the passivation layer above the p-GaN gate has a gate groove, and the bottom of the gate groove is located within the passivation layer; The gate covers the passivation layer directly above the p-GaN gate and the p-GaN nanopillar array, and fills the gate recess.

2. The enhanced GaN HEMT device regulated by a nanopillar array according to claim 1, characterized in that, The width of the p-GaN nanopillar array is less than or equal to the width of the p-GaN gate; The length of the p-GaN nanopillars is 0.1 μm to 2 μm, and the height of the p-GaN nanopillars is less than the thickness of the p-GaN gate; the spacing between adjacent p-GaN nanopillars is 1 μm to 2 μm.

3. The enhanced GaN HEMT device regulated by a nanopillar array according to claim 1, characterized in that, The thickness of the p-GaN gate is 70nm~120nm; the p-GaN gate is spaced 1μm~2μm apart from the nearest row of p-GaN nanopillars in the first direction.

4. The enhanced GaN HEMT device modulated by a nanopillar array according to claim 1, characterized in that, The substrate material is any one of silicon, sapphire, silicon carbide, gallium nitride, and diamond self-supporting substrate.

5. The enhanced GaN HEMT device regulated by a nanopillar array according to claim 1, characterized in that, The nucleation layer is made of AlN superlattice and has a thickness of 0.5 nm to 2 nm.

6. The enhanced GaN HEMT device modulated by a nanopillar array according to claim 1, characterized in that, The buffer layer is made of GaN or AlGaN and has a thickness of 0.2 μm to 1 μm.

7. The enhanced GaN HEMT device regulated by a nanopillar array according to claim 1, characterized in that, The channel layer is made of GaN and has a thickness of 100nm~300nm.

8. The enhanced GaN HEMT device regulated by a nanopillar array according to claim 1, characterized in that, The barrier layer is made of AlGaN, InAlN, AlN or InGaN, and has a thickness of 10nm to 30nm.

9. The enhanced GaN HEMT device regulated by a nanopillar array according to claim 1, characterized in that, The source and drain are both made of Ti / Al / Ni / Au or Ti / Al / Ti / Au stacked metal; the gate is made of Ni / Au or Ni / TiN stacked metal.

10. A method for fabricating an enhanced GaN HEMT device modulated by a nanopillar array, characterized in that, include: Step 1: Epitaxially grow a core layer, a buffer layer, a channel layer, a barrier layer, and a p-GaN layer sequentially on the substrate to form an epitaxial structure; Step 2: Define a p-GaN gate region on the p-GaN layer, and etch the p-GaN layer outside the p-GaN gate region to a preset depth; Step 3: Deposit a Si3N4 hard mask on the surface of the current sample, and form an etching mask on the hard mask through photolithography and etching processes; Step 4: Using the etching mask as a barrier layer, etch the p-GaN layer outside the p-GaN gate region to form a p-GaN gate directly below the p-GaN gate region, and form two rows of p-GaN nanopillars on one side of the p-GaN gate. Step 5: Remove the etching mask; Step 6: Obtain patterned device mesas using photolithography and perform mesas isolation; Step 7: Define the source and drain regions on the upper surface of the barrier layer using photolithography, and deposit metal stacks in the source and drain regions to form the source and drain. Step 8: Deposit a passivation layer on the surface of the current sample; Step 9: Etch the passivation layer directly above the p-GaN gate to form a gate recess, the bottom of which is located within the passivation layer; Step 10: Obtain a patterned gate pattern through photolithography. Deposit gate metal over the gate groove, the p-GaN gate, and the two rows of p-GaN nanopillars, and then perform metal stripping to form the gate.

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