Semiconductor structure

Abstract

A semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a dielectric layer stack. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The dielectric layer stack is disposed on the gate electrode. The dielectric layer stack includes layers having different etch rates. The overall reliability of the semiconductor structure can be improved.

Description

[0001] This application is a divisional application. The original application was filed on August 27, 2020; the application number is 202010875082.X; and the invention title is: Semiconductor Structure. Technical Field

[0002] This invention relates to semiconductor structures, and more particularly to semiconductor structures containing multiple dielectric layers with different etching rates. Background Technology

[0003] Gallium nitride (GaN) materials possess a variety of excellent properties, leading to their widespread application. For example, GaN exhibits a wide bandgap, high thermal resistance, and a high electron saturation velocity. In addition, GaN materials possess extremely strong polarization. Besides the spontaneous polarization effect caused by the crystal structure, lattice compression due to lattice mismatch further induces piezoelectric polarization. The simultaneous presence of these two polarization effects results in a large polarization charge at heterojunctions in GaN materials.

[0004] Given the aforementioned excellent properties of gallium nitride (GaN) materials, GaN semiconductors are now widely used in high electron mobility transistors (HEMTs) that incorporate heterojunction structures.

[0005] Generally, a dielectric layer is included in high electron mobility transistors. For example, the dielectric layer can be used as an interlayer dielectric layer, a gate insulating layer, and / or an insulating layer between circuits. However, existing dielectric layers are prone to plasma damage, ion damage, and / or seam-related damage, which leads to a decrease in the overall reliability of the high electron mobility transistor.

[0006] Therefore, although existing semiconductor structures have gradually met their intended applications, they are not yet completely satisfactory in all aspects. Consequently, there are still some issues to be overcome regarding semiconductor structures that can be further processed to serve as high-electron-mobility transistors. Summary of the Invention

[0007] In view of the above problems, the present invention improves the overall reliability of the semiconductor structure by further providing multiple dielectric layers, that is, by further providing multiple dielectric layers with different etching rates for wet etching or wet cleaning.

[0008] According to some embodiments, a semiconductor structure is provided. The semiconductor structure includes: a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a dielectric layer stack. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The dielectric layer stack is disposed on the gate electrode. The dielectric layer stack includes layers with different etching rates.

[0009] The semiconductor structure of the present invention can be applied to various types of semiconductor devices. To make the features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0010] The following detailed description, in conjunction with the accompanying drawings, will provide a better understanding of the embodiments of the present invention. It is worth noting that, according to industry standard practice, some features may not be drawn to scale. In fact, for clarity of discussion, the dimensions of different features may be increased or decreased.

[0011] Figures 1 to 6 This is a schematic cross-sectional view illustrating the formation of a semiconductor structure at various stages according to some embodiments of the present invention;

[0012] Figures 7A-7C Different states of dielectric layer stacking are illustrated according to some embodiments of the present invention; and

[0013] Figure 8 and Figure 9 The diagram illustrates cross-sectional views of the semiconductor structure being formed at various stages, according to some embodiments of the present invention.

[0014] Figure 10 This is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present invention.

[0015] [Symbol Explanation]

[0016] 100: substrate;

[0017] 200: Buffer layer;

[0018] 300: Channel layer;

[0019] 400: Barrier layer;

[0020] 410: Compound semiconductor layer;

[0021] 420: Metal nitride layer;

[0022] 500: Dielectric layer;

[0023] 600: Gate electrode;

[0024] 500A: Second dielectric layer stack

[0025] 700: First dielectric layer stack;

[0026] 510: Second bottom layer

[0027] 710: First bottom layer;

[0028] 520: Second Main Layer

[0029] 720: First main layer;

[0030] 530: Second Covering Layer

[0031] 730: Second overlay;

[0032] 810: Source electrode;

[0033] 820: Drain electrode;

[0034] CT: Contact Through Hole;

[0035] OP: Opening;

[0036] T: Total thickness;

[0037] T1: Thickness;

[0038] T2: Thickness;

[0039] T3: Thickness. Detailed Implementation

[0040] The following disclosure provides numerous different embodiments or examples for implementing various elements of the provided semiconductor structure. Specific examples of each element and its configuration are described below to simplify the embodiments of the invention. Of course, these are merely examples and are not intended to limit the invention. For instance, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in different examples of the embodiments of the invention. Such repetition is for brevity and clarity and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0041] The following describes some variations of the embodiments. In embodiments with different figures and descriptions, similar reference numerals are used to denote similar elements. It is understood that additional operations may be provided before, during, and after the method, and some described operations may be replaced or omitted for other embodiments of the method.

[0042] Furthermore, spatial terms such as "above," "below," "above," "below," and similar terms encompass not only the orientation shown in the diagram but also the different orientations of the device in use or operation. When the device is turned to another orientation (rotated 90 degrees or to another orientation), the spatial relative descriptions used here can also be interpreted according to the orientation after rotation.

[0043] Here, the terms "about," "approximately," and "roughly" generally indicate within 20% of a given value or range, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate; that is, even without specific mention of "about," "approximately," or "roughly," their meaning is implied.

[0044] Figures 1 to 6 These are cross-sectional schematic diagrams illustrating the semiconductor structure at various stages according to some embodiments of the present invention.

[0045] Reference Figure 1 A substrate 100 is provided, on which a buffer layer 200, a channel layer 300, and a barrier layer 400 are formed. The buffer layer 200 may be disposed on the substrate 100. The channel layer 300 may be disposed on the buffer layer 200 and the substrate 100, that is, the buffer layer 200 may be disposed between the substrate 100 and the channel layer 300. The barrier layer 400 may be disposed on the channel layer 300.

[0046] In one embodiment, substrate 100 may be or comprise a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or a similar substrate. Substrate 100 may be doped (e.g., using p-type or n-type dopants) or undoped. Generally, an SOI substrate comprises a film of semiconductor material formed on an insulator. For example, this insulating layer may be a silicon oxide layer, a silicon nitride layer, a polysilicon layer, or a stacked combination of the above films. Providing the insulating layer on the substrate is typically a silicon or aluminum nitride (AlN) substrate. Other substrates may also be used, such as multi-layered or gradient substrates. In some embodiments, the semiconductor material of substrate 100 may comprise silicon with different crystal planes, including Si (111) or Si (110). In some embodiments, substrate 100 may be a semiconductor substrate or a ceramic substrate, such as a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, an aluminum nitride substrate, or a sapphire substrate. In some embodiments, substrate 100 may include a thin film transistor (TFT) substrate.

[0047] In one embodiment, the mismatch between the channel layer 300 and the substrate 100 can cause strain. However, the buffer layer 200 can reduce and / or prevent strain on the channel layer 300 formed on the buffer layer 200, thereby preventing defects from forming in the channel layer 300. The material of the buffer layer 200 can comprise a III-V compound semiconductor material, such as a group III nitride. For example, the material of the buffer layer 200 can be or comprise gallium nitride, aluminum nitride, aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), the aforementioned single or multilayer combinations, or any other suitable material. In one embodiment, the buffer layer 200 may comprise aluminum gallium nitride. In some embodiments, the buffer layer 200 can be formed by a deposition process. The deposition process for forming the buffer layer 200 may be metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), a combination of the foregoing, or any other suitable process, but is not limited thereto.

[0048] In one embodiment, a nucleation layer (not shown) may be further disposed between the substrate 100 and the buffer layer 200. The material of the nucleation layer may be or include aluminum nitride, aluminum gallium nitride, combinations thereof, or any other suitable material. The nucleation layer may be formed by a deposition process. The deposition process for forming the nucleation layer may be metal-organic chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, combinations thereof, or any other suitable process, but is not limited thereto. The nucleation layer may reduce and / or prevent lattice differences between the substrate 100 and other layers disposed on the substrate 100, thereby improving crystal quality.

[0049] In one embodiment, the material of the channel layer 300 may comprise one or more III-V compound semiconductor materials, such as, but not limited to, group III nitrides. For example, the material of the channel layer 300 may be or may comprise gallium nitride, aluminum gallium nitride, indium aluminum nitride, indium gallium nitride (InGaN), indium aluminum gallium nitride (InAlGaN), combinations thereof, or any other suitable material, but not limited to. The channel layer 300 may be formed by a deposition process. The deposition process for forming the channel layer 300 may be metal-organic chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, combinations thereof, or any other suitable process, but not limited to. In one embodiment, the channel layer 300 may comprise gallium nitride.

[0050] In one embodiment, the material of the barrier layer 400 may comprise a III-V compound semiconductor material, such as a group III nitride. For example, the barrier layer 400 may be or comprise aluminum nitride, aluminum gallium nitride, aluminum indium nitride, indium aluminum gallium nitride, combinations thereof, or any other suitable material, but is not limited thereto. The barrier layer 400 may comprise a single-layer or multi-layer structure. The barrier layer 108 may be formed by a deposition process, such as metal-organic chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, combinations thereof, or any other suitable process, but is not limited thereto. In one embodiment, the barrier layer 400 may comprise aluminum gallium nitride.

[0051] For example, the different lattice constants between gallium nitride (GaN) as channel layer 300 and aluminum gallium nitride (AlGaN) as barrier layer 400 induce piezoelectric polarization and their respective spontaneous polarization effects. Therefore, two-dimensional electron gas (2DEG) channels (such as...) can be formed at the heterojunction between channel layer 300 and barrier layer 400. Figure 1(As shown by the dashed line). In some embodiments, the two-dimensional electron gas channel serves as a conductive carrier for the subsequently formed high electron mobility transistor, and thus can act as a current path. In some embodiments, the channel layer 300 and the barrier layer 400 are undoped. In some other embodiments, the channel layer 300 and the barrier layer 400 may be doped, for example, with n-type or p-type dopant.

[0052] Reference Figure 2 Next, a compound semiconductor layer 410 is formed on the barrier layer 400. The compound semiconductor layer 410 can be p-type doped or n-type doped gallium nitride. In one embodiment, the compound semiconductor layer 410 may contain p-type doped gallium nitride. The compound semiconductor layer 410 can suppress the underlying two-dimensional electron gas channels, thus overcoming the safety concerns of the conventional normally-on state and enabling the subsequently formed high electron mobility transistor to have a normally-off state. The compound semiconductor layer 410 may be positioned corresponding to the subsequently formed gate electrode.

[0053] Reference Figure 3 A metal nitride layer 420 is selectively disposed on the compound semiconductor layer 410. The metal nitride layer 420 may also correspond to a subsequently formed gate electrode. In one embodiment, the metal nitride layer 420 may comprise titanium nitride (TiN). The metal nitride layer 420 can improve the adhesion of the compound semiconductor layer 410 to other layers. The metal nitride layer 420 can improve leakage current. The metal nitride layer 420 can serve as an etch stop layer for subsequent aperture formation. The metal nitride layer 420 can also reduce and / or prevent the drain current from collapsing as the drain bias increases. In one embodiment, the metal nitride layer 420 may be omitted.

[0054] In one embodiment, the compound semiconductor layer 410 and the metal nitride layer 420 can be formed by a series of processes including deposition, photolithography, and etching. For example, a compound semiconductor material layer can be formed on the barrier layer 400 by deposition; then a patterned mask layer can be formed on the compound semiconductor material layer to expose a portion of the compound semiconductor material layer; then the aforementioned compound semiconductor material layer can be patterned, that is, the portion of the compound semiconductor material layer not covered by the patterned mask layer can be etched to form the compound semiconductor layer 410. Similarly, a metal nitride material layer can be formed on the compound semiconductor layer 410 by deposition; then a patterned mask layer can be formed on the metal nitride material layer to expose a portion of the metal nitride material layer; then the aforementioned metal nitride material layer can be patterned, that is, the portion of the metal nitride material layer not covered by the patterned mask layer can be etched to form the metal nitride layer 420. In one embodiment, the channel layer 300, the barrier layer 400, the compound semiconductor layer 410, and the metal nitride layer 420 can also be collectively referred to as epitaxial layers.

[0055] Reference Figure 4 A dielectric layer 500 is disposed on the barrier layer 400. The dielectric layer 500 may be disposed on a portion of the barrier layer 400, a portion of the compound semiconductor layer 410, and a portion of the metal nitride layer 420. The dielectric layer 500 may be disposed between the barrier layer 400 and a subsequently formed dielectric layer stack. In one embodiment, the dielectric layer 500 may have a flat surface. In one embodiment, the dielectric layer 500 may have a stepped surface. The shape of the stepped surface corresponds to the shape of the compound semiconductor layer 410 and the metal nitride layer 420, i.e., conformally, or customarily formed on the surfaces of the barrier layer 400, the compound semiconductor layer 410, and the metal nitride layer 420. It should be noted that, as Figure 4 The stepped surface of dielectric layer 500 shown is merely an example and not a limitation; that is, the shape of dielectric layer 500 is not limited to this. Figure 4 Limited to this. In one embodiment, the corners of the stepped surface of the dielectric layer 500 may be acute, right, rounded, obtuse, or any suitable shape. In one embodiment, the dielectric layer 500 may be any shape having a height difference corresponding to the surfaces of the barrier layer 400, the compound semiconductor layer 410, and the metal nitride layer 420, i.e., the dielectric layer 500 may have a shape corresponding to the step difference.

[0056] Reference Figure 5A portion of the dielectric layer 500 is selectively removed to form an opening OP. The opening OP can penetrate the dielectric layer 500, thus exposing a portion of the metal nitride layer 420. The location of the opening OP corresponds to the location of the subsequently formed gate electrode. The opening OP can be formed by photolithography and etching processes. The etching process can include dry etching, wet etching, or other etching methods (e.g., reactive ion etching). The etching process can also be purely chemical etching (plasma etching), purely physical etching (ion polishing), or a combination thereof. In one embodiment, the etching process for forming the opening OP can be a dry etching process. In one embodiment, when performing the etching process to form the opening OP, the metal nitride layer 420 is used as an etching stop layer, so the etching process stops at the metal nitride layer 420, thereby protecting the compound semiconductor layer 410 beneath the metal nitride layer 420 from damage.

[0057] Reference Figure 6 A gate electrode 600 is disposed in the opening OP and on the compound semiconductor layer 410. The gate electrode 600 may protrude from the dielectric layer 500. The material of the gate electrode 600 may be a conductive material, for example, including metals, metal nitrides, semiconductor materials, combinations thereof, or any other suitable conductive material, but not limited thereto. In some embodiments, the metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), the like, or combinations thereof, but not limited thereto. The semiconductor material may be polycrystalline silicon or polycrystalline germanium. The aforementioned conductive material may be formed in the opening OP by, for example, chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or other suitable deposition methods. Similarly, a conductive material layer may be formed on the metal nitride layer 420 first, and then the gate electrode 600 may be formed by a patterning process.

[0058] Reference Figures 7A to 7C The semiconductor structure shown is in Figure 6 On the semiconductor structure shown, first dielectric layer stacks 700 of different states are disposed. In one embodiment of the present invention, the first dielectric layer stack 700 is disposed on the gate electrode 600. Since the first dielectric layer stack 700 contains structures and / or components capable of resisting or reducing the etching ability of wet etching solution used in wet cleaning processes, the gate electrode 600 disposed under the first dielectric layer stack 700 is protected from erosion by wet etching solution, thus protecting the gate electrode 600 from damage.

[0059] First, it should be noted that wet cleaning can be considered a type of wet etching process. To remove particles, organic matter, contaminants, metals, and native oxides generated at each step in forming a semiconductor structure, multiple wet cleaning processes are required throughout the semiconductor structure formation process. For example, wet cleaning can occur during pre-cleaning, after any etching process, and / or after any deposition process. The etching rate of a layer in this article refers to the etching rate of a layer relative to a specific wet etchant during a wet cleaning process. However, during wet cleaning, because the layers in a semiconductor structure may contain seams, cracks, or defects, the wet etchant used in the wet cleaning process can seep into these seams, cracks, or defects, potentially damaging other components underneath. Wet cleaning processes can use acidic or alkaline wet etchants. The wet etching solution may include, but is not limited to, Standard Cleaning Solution 1 (SC-1, APM), Standard Cleaning Solution 2 (SC-2, HPM), sulfuric acid and hydrogen peroxide mixture (Piranha, SPM), combinations thereof, or any other suitable etching solution.

[0060] For example, the oxide layer, which serves as the dielectric layer, may contain oxide seams caused by the deposition process. When an acidic wet etchant is used in the wet cleaning process, the acidic wet etchant seeps into the oxide seams of the oxide layer, causing the acidic wet etchant to leak into components that should not be cleaned, resulting in acid leakage. This can damage any components containing metal components disposed beneath the oxide layer. If the first dielectric layer stack 700, on which the gate electrode 600 is disposed, has the aforementioned seams, cracks, or defects, it can even lead to damage to the gate electrode 600. Once the gate electrode 600 is damaged, it will have a significant negative impact on the overall electrical properties of the semiconductor structure. Therefore, one object of the present invention is to prevent damage to any metal components disposed beneath the first dielectric layer stack 700.

[0061] To further clarify, in high electron mobility transistors (HEMTs) containing heterojunction structures, the on-resistance (R) onThe resistance is mainly determined by the two-dimensional electron gas channel and the heterojunction between the source and drain and the channel layer 300. Since the resistance of the heterojunction between the source and drain and the channel layer 300 is extremely high, a heating process such as rapid thermal process (RTP) is typically used to diffuse a portion of the metal forming the source and drain into the two-dimensional electron gas channel, thereby forming a good ohmic contact. However, the metal forming the source and drain can also diffuse into other layers such as the first dielectric layer stack 700, leading to spiking and / or metal extrusion phenomena between the material forming the first dielectric layer stack 700 and the metal material forming the source and drain, causing a short circuit between the source / drain and the gate. Therefore, one object of the present invention is to improve the spiking phenomenon. A more detailed explanation follows regarding this object.

[0062] In one embodiment, a first dielectric layer stack 700 may be disposed on the gate electrode 600. For example, the first dielectric layer stack 700 may be compliantly disposed on the dielectric layer 500 and the gate electrode 600. Since the dielectric layer 500 may have a stepped surface, and the gate electrode 600 may protrude from the dielectric layer 500, the first dielectric layer stack 700 compliantly disposed on the dielectric layer 500 and the gate electrode 600 may also have a stepped surface. It should be noted that, as mentioned above, the dielectric layer 500 may have a stepped surface, but is not limited to this. Figures 7A to 7C The stepped surface of the first dielectric layer stack 700 shown is merely an example and not a limitation; that is, the shape of the first dielectric layer stack 700 is not limited to... Figures 7A to 7C Limited to this. In one embodiment, the corners of the stepped surface of the first dielectric layer stack 700 may be acute, right, rounded, obtuse, or any suitable shape. In one embodiment, the first dielectric layer stack 700 may be any shape having a height difference corresponding to the surfaces of the dielectric layer 500 and the gate electrode 600, that is, the first dielectric layer stack 700 may have a shape corresponding to the step difference.

[0063] In one embodiment, the first dielectric layer stack 700 comprises at least two layers with different etching rates. The semiconductor structure of the present invention, by providing a first dielectric layer stack 700 comprising at least two layers with different etching rates, reduces seams, cracks, or defects in single-layer dielectric layers, thereby improving the overall reliability of the semiconductor structure. Furthermore, because the first dielectric layer stack 700 comprises at least two layers with different etching rates, any underlying components containing metal components can be protected by the layer with the lower etching rate—that is, the layer with stronger resistance to wet etching solutions—preventing acid leakage during wet cleaning processes that could etch or damage the underlying metal, thus improving the overall reliability of the semiconductor structure. Moreover, since the first dielectric layer stack 700 may have a stepped surface, the first dielectric layer stack 700 of the present invention, when comprising at least two layers, can effectively reduce seams, cracks, or defects that are particularly prone to occur at the transitions of the stepped surface of the first dielectric layer stack 700.

[0064] In one embodiment, the overall thickness of the first dielectric layer stack 700 is 2400~3000 Å. Preferably, the overall thickness of the first dielectric layer stack 700 is 2500~2800 Å. It should be noted that in some embodiments, the overall thickness of the first dielectric layer stack 700 is the thickness of the optimal electric field distribution for a field plate design within the subsequently formed HEMT. However, the optimal value of the thickness of the first dielectric layer stack 700 will vary depending on the number, thickness, shape, arrangement, etc. of the field plates, and is not limited thereto.

[0065] In one embodiment, the first dielectric layer stack 700 comprises oxides, nitrides, oxynitrides, or any combination thereof. The first dielectric layer stack 700 may comprise aluminum oxide (Al2O3), silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS) derivatives, silane (SiH4) derivatives, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silica glass (FSG), hydrogensilsesquioxane (HSQ), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. For example, the first dielectric layer stack 700 can be formed using spin coating, chemical vapor deposition, physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), plasma-enhanced chemical vapor deposition (PECVD), a combination thereof, or any other suitable process.

[0066] In one embodiment, the first dielectric layer stack 700 may include aluminum oxide because aluminum oxide has good thermal stability, a dense structure, and does not easily affect the overall electrical properties of the semiconductor structure. In one embodiment, the first dielectric layer stack 700 may include at least two layers that are the same compound but have different etching rates. For example, the first dielectric layer stack 700 may simultaneously include silicon dioxide derived from tetraethoxysilane (TEOS) and silicon dioxide derived from silane (SiH4).

[0067] In one embodiment, in a wet etching solution, the etching rate difference between one of the at least two layers comprising the first dielectric layer stack 700 and the other layer can be 1.1 to 8.0 times. The etching rate difference between one of the at least two layers comprising the first dielectric layer stack 700 and the other layer can be 1.5 times, 2.0 times, 2.5 times, 3.0 times, 3.5 times, 4.0 times, 4.5 times, 5.0 times, 5.5 times, 6.0 times, 6.5 times, 7.0 times, 7.5 times, or any range of the above values.

[0068] In one embodiment, when the wet etching solution is hydrofluoric acid (HF), the etching rate difference between one of the at least two layers comprising the first dielectric layer stack 700 and the other layer can be 6 times. In one embodiment, when the wet etching solution is hydrofluoric acid, i.e., the volume ratio of HF:H2O is about 1:50, the etching rate difference between one of the at least two layers comprising the first dielectric layer stack 700 and the other layer can be greater than 2 times; and when the wet etching solution is buffered silicon oxide etchant (BOE), i.e., the volume ratio of NH4F:HF is about 10:1, the etching rate difference between one of the at least two layers comprising the first dielectric layer stack 700 and the other layer can be greater than 1.5 times. However, the present invention is not limited thereto, and those skilled in the art can make adjustments according to actual needs.

[0069] like Figure 7A As shown, the first dielectric layer stack 700 may include a first body layer 720 and a first capping layer 730. The first body layer 720 may be disposed on the gate electrode 600. The first capping layer 730 may be disposed on the first body layer 720. Compared to the first body layer 720, the first capping layer 730 may be further away from the gate electrode 600. The etching rate of the first capping layer 730 is lower than the etching rate of the first body layer 720. Because the first capping layer 730 can fill the oxide seams of the first body layer 720, the first capping layer 730 can protect the components containing metal components disposed under the first capping layer 730 from damage by wet etching solution. The first capping layer 730 can also prevent the inter-dissolution breakthrough phenomenon that occurs during RTP process. Figure 7AAs shown, the total thickness T of the first dielectric layer stack 700 can be approximately 2400~3000 Å. In one embodiment, the thickness T2 of the first host layer 720 can be approximately 2500 Å; and the thickness T3 of the first capping layer 730 can be approximately 1~500 Å, preferably approximately 50~100 Å. The thickness ratio of the first host layer 720 to the first capping layer 730 can be approximately 1:1 to 60:1. In one embodiment, the thickness of the first host layer 720 can be greater than that of the first capping layer 730, but is not limited thereto. In one embodiment, the thickness of the first host layer 720 can be substantially equal to or less than that of the first capping layer 730, and the thicknesses of the first host layer 720 and the first capping layer 730 can each be approximately 1000~2000 Å.

[0070] The term "body layer" as used herein does not limit the primary material of the first dielectric layer stack 700 to the material forming the body layer. In one embodiment, the first body layer 720 may be silicon oxide, and the first capping layer 730 may be aluminum oxide. In one embodiment, the first capping layer 730 may be aluminum oxide formed using an ALD process, to simultaneously achieve a thin, dense layer and fill the seams in the first body layer 720.

[0071] In one embodiment, the first host layer 720 may be silicon oxide formed using a CVD process with SiH4 as a precursor, while the first capping layer 730 may be silicon oxide formed using a thermal oxidation process with TEOS as a precursor. It should be noted that, in one embodiment, although both the first host layer 720 and the first capping layer 730 contain silicon oxide, silicon oxides formed by different processes and different precursors, although chemically identical, possess substantially different properties. For example, for some wet etching solutions, the etching rate for silicon oxide formed using a CVD process with SiH4 as a precursor is greater than that for silicon oxide formed using a thermal oxidation process with TEOS as a precursor. Therefore, as... Figure 7A As shown, the first dielectric layer stack 700, which includes a first cover layer 730 disposed on the first main body layer 720, can effectively protect the underlying components from the erosion of wet etching solution.

[0072] like Figure 7BAs shown, the first dielectric layer stack 700 may include a first bottom layer 710 and a first body layer 720. The first bottom layer 710 may be disposed on the gate electrode 600. The first body layer 720 may be disposed on the first bottom layer 710. Compared to the first bottom layer 710, the first body layer 720 may be further away from the gate electrode 600. The etching rate of the first bottom layer 710 is lower than the etching rate of the first body layer 720. Because the first bottom layer 710 is disposed on the gate electrode 600 first, a denser layer can be provided on the gate electrode 600. The first bottom layer 710 can protect the metal-containing components disposed beneath the first bottom layer 710 from damage by wet etching solution. The first bottom layer 710 can also avoid the inter-dissolution breakthrough phenomenon that occurs during RTP process. Figure 7B As shown, the total thickness T of the first dielectric layer stack 700 can be approximately 2400~3000 Å. In one embodiment, the thickness T2 of the first host layer 720 can be approximately 2500~2800 Å; and the thickness T1 of the first bottom layer 710 can be approximately 1~500 Å, preferably approximately 50~100 Å. In one embodiment, the thickness ratio of the first host layer 720 to the first bottom layer 710 can be approximately 1:1 to 60:1.

[0073] In one embodiment, the first host layer 720 may be silicon oxide, and the first bottom layer 710 may be aluminum oxide. In one embodiment, the first bottom layer 710 may be aluminum oxide formed using an ALD process to simultaneously achieve the goals of thinness and density. In another embodiment, the first host layer 720 may be silicon oxide formed using a CVD process with SiH4 as a precursor, and the first bottom layer 710 may be silicon oxide formed using a thermal oxidation process with TEOS as a precursor. The advantages of using different processes and precursors to form silicon oxide will not be elaborated upon here.

[0074] like Figure 7C As shown, the first dielectric layer stack 700 may include a first bottom layer 710, a first body layer 720, and a first capping layer 730. The first bottom layer 710 may be disposed on the gate electrode 600. The first body layer 720 may be disposed on the first bottom layer 710. The first capping layer 730 may be disposed on the first body layer 720. The etching rate of the first bottom layer 710 is lower than the etching rate of the first body layer 720, and the etching rate of the first capping layer 730 is lower than the etching rate of the first body layer 720. In other words, the first dielectric layer stack 700 has a sandwich-like structure, and the first bottom layer 710 and the first capping layer 730 are provided with layers having lower etching rates to protect the first body layer 720 sandwiched therein. Figure 7CAs shown, the total thickness T of the first dielectric layer stack 700 can be approximately 2400~3000 Å. In one embodiment, the thickness T1 of the first bottom layer 710 can be approximately 50~100 Å; the thickness T2 of the first main layer 720 can be approximately 2500~2800 Å; and the thickness T3 of the first capping layer 730 can be approximately 50~100 Å. The thickness ratio of the first bottom layer 710, the first main layer 720, and the first capping layer 730 can be 1:24:1 to 1:60:1.

[0075] In one embodiment, the first bottom layer 710 may be alumina, the first main layer 720 may be silicon oxide, and the first capping layer 730 may be alumina. In another embodiment, the first bottom layer 710 and the first capping layer 730 may both be alumina formed using an ALD process, so as to more effectively protect the metal components disposed under the first dielectric layer stack 700 while sandwiching the first main layer 720, and also to further improve the margin during wet cleaning processes. In another embodiment, the first bottom layer 710 and the first capping layer 730 may be silicon oxide formed using a thermal oxidation process with TEOS as a precursor, and the first main layer 720 may be silicon oxide formed using a CVD process with SiH4 as a precursor. The advantages of using silicon oxide formed by different processes and precursors will not be elaborated here.

[0076] Following the above, further processes can be performed to form high electron mobility transistors. As follows, based on... Figure 7C The illustrated examples are provided for illustrative purposes.

[0077] Reference Figure 8 A contact via CT is formed, penetrating the barrier layer 400, the dielectric layer 500, and the first dielectric layer stack 700. The contact via CT can be disposed on both sides of the gate electrode 600. The contact via CT is used to form the drain electrode and the source electrode.

[0078] Reference Figure 9 A conductive material is deposited in the contact via CT, and the deposited conductive material is patterned to form a source electrode 810 disposed on one side of the gate electrode 600 and in contact with the channel layer 300, and a drain electrode 820 disposed on the other side of the gate electrode 600 and in contact with the channel layer 300, thereby obtaining a high electron mobility transistor as an embodiment of the semiconductor structure of the present invention.

[0079] In one embodiment, a field plate may be further provided in the semiconductor structure of the present invention to improve charge balance. In one embodiment, the dielectric layer 500 in the semiconductor structure of the present invention may be replaced by a first dielectric layer stack 700. In one embodiment, during further processing, the first dielectric layer stack 700 may be disposed between the electrodes, between any wirings, or at any existing dielectric layer location to effectively protect the underlying metal components.

[0080] Reference Figure 10 This is a cross-sectional schematic diagram of a semiconductor structure according to some embodiments of the present invention. Figure 10 As shown, the dielectric layer disposed between the barrier layer 400 and the first dielectric layer stack 700 can be a second dielectric layer stack 500A. Similar to the first dielectric layer stack 700, the second dielectric layer stack 500A comprises at least two layers with different etching rates. The second dielectric layer stack 500A may have the same structure as the various structures of the first dielectric layer stack 700 in the foregoing embodiments. For example, as... Figure 10 As shown, the second dielectric layer stack 500A may include a second bottom layer 510, a second main layer 520 and a second cover layer 530, but is not limited thereto.

[0081] Furthermore, in one embodiment, a second dielectric layer stack may be further disposed beneath the first dielectric layer stack. The second dielectric layer stack comprises at least two layers with different etching rates. In other words, the semiconductor structure of the present invention may include a single dielectric layer stack or multiple dielectric layer stacks to protect components located beneath the first dielectric layer stack.

[0082] In summary, according to some embodiments of the present invention, the present invention reduces cracks in the dielectric layer by comprising a dielectric layer stack of at least two layers, thereby avoiding damage to underlying components containing metallic components during wet cleaning processes. Simultaneously, the inclusion of at least two dielectric layer stacks avoids inter-dissolution breakdown during RTP processes. In some embodiments, the dielectric layer stacks provided by the present invention can be disposed at any suitable dielectric layer location and replace any existing dielectric layer to overcome damage to conductive structures, such as metallic components, during wet cleaning processes in various types of semiconductor structures, thereby providing a more reliable semiconductor structure.

[0083] While the embodiments and advantages of the present invention have been disclosed above, it should be understood that any person skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of the invention. Furthermore, the scope of protection of the present invention is not limited to the processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps described in the specific embodiments of the specification. Any person skilled in the art can understand from the disclosure of some embodiments of the present invention that current or future developed processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps can be used according to some embodiments of the present invention as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein. Therefore, the scope of protection of the present invention includes the above-described processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of the present invention also includes combinations of the various claim scopes and embodiments.

[0084] The foregoing outlines several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they can be modified, substituted, and replaced in various ways without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure, characterized in that, Include: One substrate; A channel layer is disposed on the substrate; A barrier layer is disposed on the channel layer; A compound semiconductor layer is disposed on the barrier layer; A gate electrode is disposed on the compound semiconductor layer; A first dielectric layer is stacked and disposed on the gate electrode; The first dielectric layer stack includes: A first main body layer is disposed on the gate electrode; and A first cover layer is disposed on the first main body layer, and the etching rate of the first cover layer is less than the etching rate of the first main body layer; A source electrode is disposed on one side of the gate electrode and in contact with the channel layer; and A drain electrode is disposed on the other side of the gate electrode and in contact with the channel layer, and the source electrode and the drain electrode are stacked through the first dielectric layer.

2. The semiconductor structure according to claim 1, characterized in that, In a wet etching solution, the etching rate difference between the first host layer and the first capping layer is 1.1 to 8.0 times.

3. The semiconductor structure according to claim 1, characterized in that, The thickness of the first main body layer is greater than that of the first cover layer.

4. The semiconductor structure according to claim 1, characterized in that, The first dielectric layer stack further includes: A first bottom layer is disposed between the gate electrode and the first main layer; The etching rate of the first bottom layer is less than that of the first main layer.

5. The semiconductor structure according to claim 4, characterized in that, The thickness of the first bottom layer is less than that of the first main layer.

6. The semiconductor structure according to claim 4, characterized in that, The thickness ratio of the first bottom layer, the first main layer, and the first cover layer is 1:24:1 to 1:60:

1.

7. The semiconductor structure according to claim 1, characterized in that, The first host layer comprises oxides, nitrides, oxynitrides, or any combination thereof.

8. The semiconductor structure according to claim 1, characterized in that, The first covering layer contains aluminum oxide.

9. The semiconductor structure according to claim 4, characterized in that, The first dielectric layer stack consists of at least two layers containing the same compound.

10. The semiconductor structure according to claim 1, characterized in that, The thickness of the first dielectric layer stack is 2400~3000 Å.

11. The semiconductor structure according to claim 1, characterized in that, Also includes: A buffer layer is disposed on the substrate, and the buffer layer is disposed between the channel layer and the substrate.

12. The semiconductor structure according to claim 1, characterized in that, Also includes: A metal nitride layer is disposed between the compound semiconductor layer and the gate electrode.

13. The semiconductor structure according to claim 1, characterized in that, Also includes: A dielectric layer is disposed between the barrier layer and the first dielectric layer stack.

14. The semiconductor structure according to claim 13, characterized in that, The dielectric layer is a second dielectric layer stack comprising at least two layers with different etching rates.

15. The semiconductor structure according to claim 14, characterized in that, The second dielectric layer stack further includes: A second bottom layer covers the barrier layer and the compound semiconductor layer; A second main body layer, disposed on the second bottom layer; and A second cover layer is disposed on the second main body layer, and the etching rates of the second bottom layer and the second cover layer are less than the etching rate of the second main body layer; The first bottom layer directly contacts a top surface of the gate electrode, and the second bottom layer directly contacts a bottom surface of the gate electrode.

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