Semiconductor device and electronic equipment

Abstract

According to the semiconductor device and the electronic equipment provided by the invention, the plurality of P-type extension parts extending in sections are arranged on one side, close to the drain electrode, of the P-GaN cap layer, and the plurality of P-type extension parts form the comb-shaped structure, so that the concentration of 2DEG in a channel between a gate and a drain can be modulated in a selected area; off-state peak electric field distribution, located on the side, close to the drain electrode, of the P-GaN cap layer of the device under high-voltage bias is optimized, the parasitic capacitance and resistance effect introduced by the sectional P-type extension portion can be reduced, and the dynamic on-resistance characteristic of the device is improved; moreover, the P-type layer connected with the drain electrode is introduced, and the P-type layer is of a hole injection structure, so that the P-type layer connected with the drain electrode can realize effective hole injection for the drift region when the device bears higher drain electrode bias voltage, and the drift region can be effectively subjected to hole injection under the condition of not losing gate characteristics (low gate electric leakage and low transverse P-GaN parasitic effect). And the dynamic on-resistance of the device is further reduced, so that the current collapse effect of the device is effectively inhibited.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor device and electronic device. Background Technology

[0002] High Electron Mobility Transistors (HEMTs) based on AlGaN / GaN heterostructures can meet the requirements of power electronic systems in terms of high temperature, high voltage, high frequency, and miniaturization, and have become one of the best candidates for realizing next-generation high power density power systems. P-GaN gates, as the mainstream scheme for realizing enhancement-mode GaN HEMT power devices, have been a research hotspot in recent years.

[0003] To further improve the reliability of P-GaN gate enhancement-mode HEMT devices, it is necessary to further optimize the off-state peak electric field distribution, weaken the strong field electronic effect, and improve its dynamic on-resistance characteristics. Compared with silicon-based LDMOS (laterally diffused metal-oxide-semiconductor), current GaN HEMT devices in the industry typically employ source or gate field plate technology to mitigate the peak electric field on the lateral device surface, thereby shielding the high electric field from the drain port. However, the gate field plate increases the gate-drain feedback capacitance Cgd, and the source field plate increases the source-drain capacitance Cds, which may reduce switching speed and increase switching losses. Simultaneously, due to the high field stress in the off-state, the quality requirements for the passivation dielectric under the field plate are also very high.

[0004] Therefore, how to further optimize the dynamic on-resistance characteristics of enhanced GaN HEMT devices without compromising device performance is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] This disclosure provides a semiconductor device and electronic device that can significantly improve the dynamic on-resistance characteristics of the device and suppress the current collapse effect.

[0006] The specific plan disclosed herein is as follows: On one hand, embodiments of this disclosure provide a semiconductor device, including: A substrate, a channel layer, and a barrier layer are stacked sequentially. The source and drain are spaced apart on the side of the barrier layer and / or the channel layer away from the substrate; A P-GaN cap layer is located on the side of the barrier layer away from the substrate and between the source and the drain. The source, the P-GaN cap layer and the drain are arranged sequentially along a first direction, which is parallel to the substrate. The gate is located on the side of the P-GaN cap layer away from the substrate; Multiple P-type extensions are located on the side of the barrier layer away from the substrate and are spaced apart along a second direction, which is perpendicular to the first direction. Each P-type extension is located on the side of the P-GaN cap layer near the drain, and each P-type extension is connected to the P-GaN cap layer. A P-type layer is located on the side of the barrier layer away from the substrate, and on the side of the P-type extension away from the P-GaN cap layer. The P-type layer and the P-type extension are spaced apart. The drain covers the side of the P-type layer away from the P-GaN cap layer and the top surface of the P-type layer away from the substrate.

[0007] In some embodiments, in the semiconductor device provided in the present disclosure, the thickness of the P-type extension is less than the thickness of the P-GaN cap layer.

[0008] In some embodiments, in the semiconductor device provided in the present disclosure, the width of the gap between two adjacent P-type extensions along the second direction is the same as the width of the P-type extensions along the second direction.

[0009] In some embodiments, in the semiconductor device provided in the present disclosure, the orthogonal projection shape of the P-type extension on the substrate is square, and the width of the P-type extension along the second direction is greater than or equal to 50 nm.

[0010] In some embodiments, in the semiconductor device provided in the present disclosure, the P-type layer includes a plurality of P-type structures spaced apart along the second direction, the P-type structures and the P-type extensions are arranged alternately along the second direction, and the center line of the P-type structure along the first direction and the center line of the P-type extension along the first direction are not on the same straight line.

[0011] In some embodiments, in the semiconductor device provided in the present disclosure, the orthogonal projection shape of the P-type structure on the substrate is square; the width of the P-type structure along the second direction is the same as the width of the gap between two adjacent P-type extensions along the second direction, and the P-type structure is aligned with the gap between two adjacent P-type extensions.

[0012] In some embodiments, in the semiconductor device provided in the present disclosure, the P-type layer is a strip structure extending along the second direction.

[0013] In some embodiments, in the semiconductor device provided in this disclosure, the thickness of the P-type layer is the same as the thickness of the P-type extension.

[0014] In some embodiments, in the semiconductor device provided in the present disclosure, the thickness of the P-type layer is the same as the thickness of the P-GaN cap layer.

[0015] Accordingly, this disclosure also provides an electronic device, including any of the semiconductor devices described above in this disclosure.

[0016] The beneficial effects of this disclosure are as follows: This disclosure provides a semiconductor device and electronic device. By providing multiple segmented P-type extensions on the drain side of the P-GaN cap layer, forming a comb-like structure, the 2DEG concentration in the gate-drain channel can be selectively modulated. This optimizes the off-state peak electric field distribution of the device on the drain side of the P-GaN cap layer under high-voltage bias. Furthermore, the segmented P-type extensions can reduce the parasitic capacitance and resistance effects they introduce, improving the dynamic on-resistance characteristics of the device. In addition, by introducing a P-type layer connected to the drain, which is a hole injection structure, the P-type layer connected to the drain can effectively inject holes into the drift region when the semiconductor device is subjected to a high drain bias voltage. This further reduces the dynamic on-resistance of the device without compromising gate characteristics (low gate leakage current + low lateral P-GaN parasitic effect), thereby effectively suppressing the current collapse effect of the device. Therefore, by applying a segmented P-type extension on one side of the P-GaN cap layer and introducing a P-type layer connected to the drain, this disclosure can optimize the off-state peak electric field distribution and dynamic on-resistance characteristics of the device. Attached Figure Description

[0017] Figure 1 This is a three-dimensional schematic diagram of a semiconductor device provided in an embodiment of the present disclosure; Figure 2 for Figure 1 A cross-sectional schematic diagram; Figure 3 for Figure 1 A top-view plan view; Figure 4 A three-dimensional schematic diagram of another semiconductor device provided in the embodiments of this disclosure; Figure 5 for Figure 4 A cross-sectional schematic diagram; Figure 6 for Figure 4 A top-view plan view; Figure 7 A three-dimensional schematic diagram of another semiconductor device provided in the embodiments of this disclosure; Figure 8 for Figure 7 A cross-sectional schematic diagram; Figure 9 for Figure 7 A top-view plan view; Figure 10 A three-dimensional schematic diagram of another semiconductor device provided in the embodiments of this disclosure; Figure 11 for Figure 10 A cross-sectional schematic diagram; Figure 12 for Figure 10 A top-view plan view; Figure 13 These are schematic diagrams of P-type extension structures with the same area but different distribution densities in the semiconductor devices disclosed herein. Figure 14 They are respectively Figure 13 The corresponding simulation diagram shows the effect of optimizing the off-state peak electric field distribution; Figure 15 This is a schematic diagram of the semiconductor device during the fabrication process according to an embodiment of the present disclosure; Figure 16 This is another structural schematic diagram of the semiconductor device in the fabrication process according to an embodiment of the present disclosure; Figure 17 This is another structural schematic diagram of the semiconductor device in the fabrication process according to an embodiment of the present disclosure. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes do not represent the precise shape of the illustrated regions or reflect true proportions; they are only intended to illustrate the content of this disclosure. And throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0019] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0020] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, no intermediate elements or intermediate layers are present. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0021] This disclosure provides a semiconductor device, which can be a HEMT device, such as... Figures 1-3 As shown, Figure 1 This is a three-dimensional schematic diagram of a semiconductor device provided in an embodiment of the present disclosure. Figure 2 for Figure 1 A cross-sectional schematic diagram, Figure 3 for Figure 1 The schematic diagram is shown in the top view. The semiconductor device includes: a substrate 1, a channel layer 2, and a barrier layer 3 stacked sequentially. Specifically, the channel layer 2 and the barrier layer 3 form a heterojunction. The heterojunction forms a high-density two-dimensional electron gas (2DEG) at the heterojunction interface through spontaneous polarization and piezoelectric polarization effects, that is, a 2DEG channel is formed. The source electrode 4 and the drain electrode 5 are spaced apart and located on the side of the barrier layer 3 and / or the channel layer 2 away from the substrate. For example, the source electrode 4 and the drain electrode 5 may both be located on the side of the barrier layer 3 away from the substrate 1, or the source electrode 4 and the drain electrode 5 may both be in contact with the channel layer 2 through vias penetrating the barrier layer 3 (i.e., the source electrode 4 and the drain electrode 5 may both be located on the side of the channel layer 2 away from the substrate 1), or a portion of the source electrode 4 and the drain electrode 5 may be located on the side of the barrier layer 3 away from the substrate 1, and the other portion may be in contact with the channel layer 2 through vias penetrating the barrier layer 3. Specifically, the source electrode 4 and the drain electrode 5 form an ohmic contact with the barrier layer 3 and the channel layer 2. The P-GaN cap layer 6 is located on the side of the barrier layer 3 away from the substrate 1 and between the source 4 and the drain 5. The source 4, the P-GaN cap layer 6 and the drain 5 are arranged sequentially along the first direction X, which is parallel to the substrate 1. The P-GaN cap layer 6 is used to ensure the threshold stability of the device. Gate 7 is located on the side of the P-GaN cap layer 6 away from the substrate 1; Multiple P-type extensions 8 are located on the side of the barrier layer 3 away from the substrate 1 and are spaced apart along the second direction Y. The second direction Y is perpendicular to the first direction X. Each P-type extension 8 is located on the side of the P-GaN cap layer 6 near the drain 5 and is connected to the P-GaN cap layer 6. The P-type layer 9 is located on the side of the barrier layer 3 away from the substrate 1, and on the side of the P-type extension 8 away from the P-GaN cap layer 6. The P-type layer 9 and the P-type extension 8 are spaced apart. The drain 5 covers the side of the P-type layer 9 away from the P-GaN cap layer 6 and the top surface of the P-type layer 9 away from the substrate 1.

[0022] The semiconductor device provided in this disclosure, by providing multiple segmented P-type extensions on the drain side of the P-GaN cap layer, forming a comb-like structure, can selectively modulate the 2DEG concentration in the gate-drain channel, optimizing the off-state peak electric field distribution of the device on the drain side of the P-GaN cap layer under high-voltage bias. Furthermore, the segmented P-type extensions can reduce the introduced parasitic capacitance and resistance effects, improving the device's dynamic on-resistance characteristics. Moreover, by introducing a P-type layer connected to the drain, which is a hole injection structure, the P-type layer connected to the drain can effectively inject holes into the drift region when the semiconductor device is subjected to a high drain bias. This further reduces the device's dynamic on-resistance without compromising gate characteristics (low gate leakage current + low lateral P-GaN parasitic effect), thereby effectively suppressing the device's current collapse effect. Therefore, by applying a segmented P-type extension on one side of the P-GaN cap layer and introducing a P-type layer connected to the drain, this disclosure can optimize the off-state peak electric field distribution and dynamic on-resistance characteristics of the device.

[0023] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 1-3 As shown, the thickness of the P-type extension 8 is less than the thickness of the P-GaN cap layer 6. By setting a thin P-type extension 8 on the side of the P-GaN cap layer 6 near the drain 5, and since the P-type extension 8 is connected to the P-GaN cap layer 6, the potential of the P-type extension 8 is controlled by the gate 7. When the device is in the on state, the 2DEG concentration in the channel below the P-type extension 8 can be restored by the gate voltage control. Therefore, the P-type extension 8 can selectively modulate the 2DEG concentration in the channel between the gate and drain, which can optimize the distribution of the peak electric field in the off state of the device, suppress leakage current, and improve the breakdown voltage. Furthermore, the segmented structure can reduce the parasitic effect of the P-type extension 8 on the dynamic conduction characteristics and improve the dynamic on-resistance characteristics of the device.

[0024] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 1-3 As shown, the width w1 of the gap between two adjacent P-type extensions 8 along the second direction Y is the same as the width w2 of the P-type extension 8 along the second direction Y, i.e., w1 = w2. This improves the effect of optimizing the distribution of the peak electric field in the off-state of the device. Of course, w1 and w2 can also be different.

[0025] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 1-3 As shown, the orthographic projection shape of the P-type extension 8 on the substrate 1 is square, and the width of the P-type extension 8 along the second Y direction is greater than or equal to 50 nm. This can reduce the concentration of the fabrication process. Of course, the orthographic projection shape of the P-type extension 8 on the substrate 1 is not limited to square.

[0026] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 1-3As shown, the P-type layer 9 includes multiple P-type structures 91 arranged at intervals along the second direction Y, forming a comb-like structure. The P-type structures 91 and P-type extensions 8 are arranged alternately along the second direction Y, and the center lines of the P-type structures 91 and P-type extensions 8 along the first direction X are not on the same straight line. In this way, the multiple P-type structures 91 and multiple P-type extensions 8 are staggered to form a similar interdigital structure. Through the hole injection characteristics of the P-type structures 91, the electrons trapped between the gate 7 and the drain 5 under high pressure stress are rapidly released, thereby avoiding the accumulation of electrons in the channel or surface traps, preventing current collapse, and further optimizing the dynamic on-resistance of the device. In addition, under the off-state high-voltage bias condition, in addition to the peak electric field on the side of the P-GaN cap layer 6 near the drain 5, the peak electric field on the side of the drain 5 will also increase sharply as the voltage of the drain 5 continues to increase. Therefore, by setting the comb-shaped P-type extension 8 to complement the P-type structure 91, the overall peak electric field distribution of the device under high-voltage bias can be effectively balanced.

[0027] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 1-3 As shown, the orthographic projection shape of the P-type structure 91 on the substrate 1 is square, which can reduce the concentration of the fabrication process. Of course, the orthographic projection shape of the P-type structure 91 on the substrate 1 is not limited to square.

[0028] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 1-3 As shown, the width w3 of the P-type structure 91 along the second direction Y is the same as the width w1 of the gap between two adjacent P-type extensions 8 along the second direction Y, i.e., w3 = w1. The P-type structure 91 is aligned with the gap between two adjacent P-type extensions 8. This reduces the difference in device channel length caused by the P-type extensions 8, making the channel length the same and improving device performance.

[0029] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 1-3 As shown, the thickness of the P-type layer 9 can be the same as the thickness of the P-type extension 8, that is, the P-type layer 9 is formed at the same time as the P-type extension 8.

[0030] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 4-6 As shown, Figure 4 This is a three-dimensional schematic diagram of another semiconductor device provided in the embodiments of this disclosure. Figure 5 for Figure 4 A cross-sectional schematic diagram, Figure 6 for Figure 4 A top-view plan view showing the structure of the semiconductor device in this embodiment. Figures 1-3The structure is basically the same as that of the previous embodiment, except that the thickness of the P-type layer 9 is the same as the thickness of the P-GaN cap layer 6, that is, the P-type layer 9 is formed simultaneously with the formation of the P-GaN cap layer 6. This embodiment has the same structure as the previous embodiment. Figures 1-3 The same beneficial effects as in the embodiments are described above and will not be repeated here.

[0031] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 7-9 As shown, Figure 7 This is a three-dimensional schematic diagram of another semiconductor device provided in the embodiments of this disclosure. Figure 8 for Figure 7 A cross-sectional schematic diagram, Figure 9 for Figure 7 A top-view plan view showing the structure of the semiconductor device in this embodiment. Figures 1-3 The structure is basically the same as that of the previous one, the difference being that: in this embodiment, the P-type layer 9 is a strip structure extending along the second direction Y. This embodiment has the same... Figures 1-3 The same beneficial effects are described above for the embodiments, and the strip-shaped P-type layer 9 in this embodiment is more conducive to hole injection.

[0032] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 10-12 As shown, Figure 10 This is a three-dimensional schematic diagram of another semiconductor device provided in the embodiments of this disclosure. Figure 11 for Figure 10 A cross-sectional schematic diagram, Figure 12 for Figure 10 A top-view plan view showing the structure of the semiconductor device in this embodiment. Figures 7-9 The structure is basically the same as that of the previous embodiment, except that the thickness of the P-type layer 9 is the same as the thickness of the P-GaN cap layer 6, that is, the P-type layer 9 is formed simultaneously with the formation of the P-GaN cap layer 6. This embodiment has the same structure as the previous embodiment. Figures 1-3 The same beneficial effects are described above for the embodiments, and the strip-shaped P-type layer 9 in this embodiment is more conducive to hole injection.

[0033] In some embodiments, such as Figures 1-12 As shown, the dimensions of the P-type extension 8 on the side of the P-GaN cap layer 6 near the drain 5 can be adjusted through process and layout pattern control, including length, width, height, segment size / duty cycle, etc.; the P-type layer 9 can be defined with specific structure and thickness in the above process according to the implementation method to achieve the best improvement of the dynamic on-resistance characteristics of the device.

[0034] In some embodiments, such as Figures 1-12As shown, the P-type extension 8 of this disclosure can effectively suppress the electric field in the radiation-sensitive region, and has a radiation hardening effect compared with traditional P-type gate GaN devices.

[0035] In some embodiments, such as Figures 1-12 As shown, by setting multiple segmented P-type extensions 8 on the side of the P-GaN cap layer 6 near the drain 5, the multiple P-type extensions 8 form a comb-like structure. Under the action of P-type extensions 8 of the same area, the finer and denser the segmented structure, the more obvious the effect on electric field optimization. Figure 13 As shown, Figure 13 (a) to (d) are schematic diagrams of the P-type extension 8 with the same area but different distribution densities. From (a) to (d), the distribution density is denser. For example, w1 and w2 are both 2μm in (a), 1μm in (b), 0.5μm in (c), and 0.2μm in (d). Figure 14 (a) to (d) in the text are respectively Figure 13 The simulation diagrams (a) to (d) in the figure show the effect of optimizing the peak electric field distribution in the off-state. It can be seen that from (a) to (d), the maximum value (Max) of the peak electric field (represented by the Gate edge) on the side of the Gate 7 near the Drain 5 gradually decreases, and the maximum value (Max) of the peak electric field (represented by the Segmented-extended p-GaN edge) on the side of the P-type extension 8 near the Drain 5 gradually decreases. Therefore, under the action of the P-type extension 8 with the same area, the finer and denser the segmented structure, the more obvious the effect on electric field optimization.

[0036] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 1-12 As shown, the P-GaN cap layer 6, the P-type extension 8, and the P-type layer 9 can be made of the same material, that is, the doping concentration of the P-GaN cap layer 6, the P-type extension 8, and the P-type layer 9 can be the same, for example, 5 × 10⁻⁶. 18 ~5×10 19 cm -3 For example, 5×10 18 cm -3 6×10 18 cm -3 7×10 18 cm -3 8×10 18 cm -3 9×10 18 cm -3 1×10 19 cm -3 2×10 19 cm -3 3×1019 cm -3 4×10 19 cm -3 and 5×10 19 cm -3 Of course, the doping concentrations of the P-GaN cap layer 6, the P-type extension 8, and the P-type layer 9 can also be different.

[0037] In some embodiments, such as Figure 1 , Figure 2 , Figure 5 and Figure 6 As shown, the semiconductor device provided in this embodiment of the present disclosure further includes a dielectric layer (not shown in this disclosure) filled between the source, drain and gate, and the material of the dielectric layer may be SiO2, SiNx, AlN, etc.

[0038] In some embodiments, the substrate 1 of this disclosure may be a Si, SiC, GaN, sapphire, diamond, SOI, QST composite substrate, etc., and this disclosure does not limit it.

[0039] In some embodiments, the channel layer 2 of this disclosure may be made of GaN; the barrier layer 3 may be made of Al(In,Ga)N. For example, the barrier layer 3 may be an AlN binary alloy layer, an AlGaN, AlInN, or InGaN ternary alloy layer, or an AlInGaN quaternary alloy layer.

[0040] In some embodiments, the P-GaN cap layer 6 of this disclosure may be GaN doped with at least one of magnesium (Mg), iron (Fe), zinc (Zn) and carbon (C).

[0041] In some embodiments, the material of the source 4 of this disclosure may be one or more combinations of Ti, Al, TiN, and Au; the material of the drain 5 of this disclosure may be one or more combinations of Ti, Al, TiN, and Au; and the material of the gate 7 of this disclosure may be one or more combinations of Ti, Al, Ni, and Au.

[0042] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 1 , Figure 2 , Figure 5 and Figure 6 As shown, it also includes a buffer layer 10 located between the substrate 1 and the channel layer 2, and the material of the buffer layer 10 includes at least one of AlN, AlGaN and GaN.

[0043] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 1 , Figure 2 , Figure 5 and Figure 6 As shown, it may also include a nucleation layer 11 located between the substrate 1 and the buffer layer 10. The nucleation layer 11 can avoid the problem of cracks in the buffer layer 10 caused by lattice mismatch and thermal mismatch when the buffer layer 10 is formed directly on the substrate 1, which would lead to a decrease in crystal quality. The material of the nucleation layer 11 can be one or more combinations of AlN, GaN, and AlGaN.

[0044] To better understand the semiconductor devices provided in the embodiments of this disclosure, the fabrication process of the semiconductor devices is described in detail.

[0045] In some embodiments, the fabrication process of the semiconductor device disclosed herein may specifically include the following steps: (1) Using methods such as MOCVD, nucleation layer, buffer layer, channel layer, barrier and P-type material layer are grown on the substrate.

[0046] (2) Partially etch the P-type material layer, defining the width of the P-GaN cap layer and the thickness of the P-type extension; for Figures 1-6 It is necessary to retain the segmented P-type layer with drain coverage; for Figures 7-12 The P-type layer covering the drain needs to be retained without etching.

[0047] (3) Etch the remaining P-type material layer, and completely etch the remaining P-type material layer, except for the P-GaN cap layer, P-type extension, and drain-covered P-type layer, to the barrier layer.

[0048] (4) Source and drain electrodes are formed on the barrier layer and channel layer, and are in ohmic contact with the barrier layer; for Figures 1-6 The drain forms an ohmic contact with the segmented P-type layer; for Figures 7-12 The drain electrode forms an ohmic contact with the strip-shaped P-type layer.

[0049] (5) Form a gate on the P-GaN cap layer.

[0050] (6) A dielectric layer is formed above the barrier layer that is not covered by the source, drain, P-GaN cap layer, P-type extension and P-type layer.

[0051] In some embodiments, the fabrication process of the semiconductor device disclosed herein may further include the following steps: (1) Using methods such as MOCVD, nucleation layer, buffer layer, channel layer, barrier and P-type material layer are grown on the substrate.

[0052] (2) For example Figure 15 As shown, a photoresist pattern is formed on a P-type material layer (represented by P-GaN), and the P-type material layer near the source is etched (indicated by the arrow) to the barrier layer, defining the distance from the P-GaN cap layer to the source.

[0053] (3) such as Figure 16 As shown, a photoresist pattern is formed on a P-type material layer (represented by P-GaN), and the P-type material layer near the drain is partially etched (indicated by the arrow), defining the width of the P-GaN cap layer and the thickness of the P-type extension. For Figures 1-6 It requires partial etching while preserving the P-type layer covering the drain; for Figures 7-12 The P-type layer covering the drain needs to be retained without etching.

[0054] (4) such as Figure 17 As shown, a photoresist pattern is formed on the P-type material layer (represented by P-GaN). The remaining P-type material layer near the drain is etched (as indicated by the arrow) to the barrier layer. The remaining P-type material layer, except for the P-type extension and the P-type layer covered by the drain, is completely etched to the barrier layer, defining the pattern of the P-type extension.

[0055] (5) Source and drain electrodes are formed on the barrier layer and channel layer, and are in ohmic contact with the barrier layer; for Figures 1-6 The drain forms an ohmic contact with the segmented P-type layer; for Figures 7-12 The drain electrode forms an ohmic contact with the strip-shaped P-type layer.

[0056] (6) Form a gate on the P-GaN cap layer.

[0057] (7) A dielectric layer is formed above the barrier layer that is not covered by the source, drain, P-GaN cap layer, P-type extension and P-type layer.

[0058] Based on the same inventive concept, this disclosure provides an electronic device including the semiconductor device described above. Since the principle by which this electronic device solves the problem is similar to that of the semiconductor device described above, the implementation of the electronic device provided in this disclosure can refer to the implementation of the semiconductor device described above, and repeated details will not be elaborated further.

[0059] In some embodiments, the electronic device provided in this disclosure can be a power supply, a photovoltaic system, an industrial motor, or an electric vehicle, etc. The disclosed embodiments do not impose any special limitations on the specific form of the electronic device.

[0060] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0061] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A semiconductor device, characterized in that, include: A substrate, a channel layer, and a barrier layer are stacked sequentially. The source and drain are spaced apart on the side of the barrier layer and / or the channel layer away from the substrate; A P-GaN cap layer is located on the side of the barrier layer away from the substrate and between the source and the drain. The source, the P-GaN cap layer and the drain are arranged sequentially along a first direction, which is parallel to the substrate. The gate is located on the side of the P-GaN cap layer away from the substrate; Multiple P-type extensions are located on the side of the barrier layer away from the substrate and are spaced apart along a second direction, which is perpendicular to the first direction. Each P-type extension is located on the side of the P-GaN cap layer near the drain, and each P-type extension is connected to the P-GaN cap layer. A P-type layer is located on the side of the barrier layer away from the substrate, and on the side of the P-type extension away from the P-GaN cap layer. The P-type layer and the P-type extension are spaced apart. The drain covers the side of the P-type layer away from the P-GaN cap layer and the top surface of the P-type layer away from the substrate.

2. The semiconductor device as claimed in claim 1, characterized in that, The thickness of the P-type extension is less than the thickness of the P-GaN cap layer.

3. The semiconductor device as described in claim 1, characterized in that, The width of the gap between two adjacent P-shaped extensions along the second direction is the same as the width of the P-shaped extensions along the second direction.

4. The semiconductor device as described in claim 3, characterized in that, The orthographic projection of the P-type extension on the substrate is square, and the width of the P-type extension along the second direction is greater than or equal to 50 nm.

5. The semiconductor device as claimed in claim 1, characterized in that, The P-type layer includes a plurality of P-type structures spaced apart along the second direction. The P-type structures and the P-type extensions are arranged alternately along the second direction. The center lines of the P-type structures along the first direction and the center lines of the P-type extensions along the first direction are not on the same straight line.

6. The semiconductor device as claimed in claim 5, characterized in that, The orthographic projection of the P-type structure onto the substrate is square; the width of the P-type structure along the second direction is the same as the width of the gap between two adjacent P-type extensions along the second direction, and the P-type structure is aligned with the gap between two adjacent P-type extensions.

7. The semiconductor device as claimed in claim 1, characterized in that, The P-type layer is a strip-shaped structure extending along the second direction.

8. The semiconductor device as claimed in claim 1, characterized in that, The thickness of the P-type layer is the same as the thickness of the P-type extension.

9. The semiconductor device as claimed in claim 1, characterized in that, The thickness of the P-type layer is the same as the thickness of the P-GaN cap layer.

10. An electronic device, characterized in that, Includes the semiconductor device as described in any one of claims 1-9.

Images