Method of manufacturing a semiconductor structure and semiconductor device

Abstract

The application discloses a semiconductor structure manufacturing method and a semiconductor device. The semiconductor structure manufacturing method according to the embodiment of the application comprises the following steps: providing a substrate, and forming a polysilicon layer on the substrate; performing patterning on the polysilicon layer to form a dummy gate; injecting germanium ions on the sidewall surface of the dummy gate to form a modified layer; removing the dummy gate and the modified layer; and forming a metal gate to replace the dummy gate. The semiconductor structure manufacturing method and the semiconductor device according to the embodiment of the application can reduce the polysilicon residue when the dummy gate is removed, thereby improving the filling quality of the metal gate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure and a semiconductor device. Background Technology

[0002] In advanced integrated circuit manufacturing processes, high-kmetal gate (HKMG) technology is widely used. The process involves first forming a polysilicon dummy gate, then forming nitride sidewalls. The dummy gate is exposed through chemical mechanical polishing (CMP), followed by dry / wet etching to remove it and form trenches. Finally, a metal gate is filled into the trenches.

[0003] Figure 1 A schematic cross-sectional view of the semiconductor structure before dummy gate removal is shown according to the prior art; Figure 2 A schematic cross-sectional view of a semiconductor structure after dummy gate removal according to the prior art is shown. Figure 3 A schematic diagram illustrating the pseudo-gate removal effect according to existing techniques is shown. Combined with... Figures 1 to 3 As shown, in the existing high dielectric constant gate dielectric-metal gate process, when the dummy gate 210 is removed by dry / wet etching, there will be polysilicon residue on the sidewalls and bottom, which affects the formation of the metal gate and ultimately affects the semiconductor performance and yield.

[0004] Therefore, there is a need for a new method for manufacturing semiconductor structures and semiconductor devices that can overcome at least one of the above problems. Summary of the Invention

[0005] In view of the above problems, the purpose of the present invention is to provide a method for manufacturing a semiconductor structure and a semiconductor device, particularly a semiconductor manufacturing method for improving the polysilicon residue of dummy gates, thereby reducing polysilicon residue during dummy gate removal and improving the filling quality of metal gates.

[0006] According to one aspect of the present invention, a method for manufacturing a semiconductor structure is provided, comprising:

[0007] A substrate is provided, and a polycrystalline silicon layer is formed on the substrate;

[0008] The polysilicon layer is patterned to form a pseudo-gate;

[0009] Germanium ions are implanted into the sidewall surface of the dummy gate to form a modified layer;

[0010] Remove the dummy gate and the modified layer; and

[0011] A metal gate is formed to replace the dummy gate.

[0012] Optionally, the implantation of germanium ions into the sidewall surface of the dummy gate to form a modified layer includes:

[0013] Germanium ions are injected into the sidewall surface of the dummy gate using a high-temperature diffusion method to enrich the exposed sidewall surface of the dummy gate with germanium ions, thereby forming the modified layer.

[0014] Optionally, the temperature of the high-temperature diffusion is between 700°C and 1000°C.

[0015] Optionally, removing the dummy gate and the modified layer includes:

[0016] The dummy gate and the modified layer are removed using a first wet etching process;

[0017] After the first wet etching is used, the remaining modified layer is removed by the second wet etching.

[0018] Optionally, the implantation of germanium ions into the sidewall surface of the dummy gate to form a modified layer includes:

[0019] Germanium ions are injected along the first incident direction to form a first modified layer in the lower region of the pseudo-gate sidewall;

[0020] Boron ions are implanted along the second incident direction to form a second modified layer in the upper region of the pseudo-gate sidewall.

[0021] The first modified layer and the second modified layer are connected to form a continuous modified layer; the modified layer covers the entire sidewall of the pseudo gate.

[0022] Optionally, the method for manufacturing the semiconductor structure further includes:

[0023] A high-k dielectric layer is formed on the substrate, and the high-k dielectric layer covers the active region;

[0024] A titanium nitride layer is formed on the high-k dielectric layer, and the titanium nitride layer covers the active region;

[0025] The polycrystalline silicon layer is formed on the titanium nitride layer.

[0026] During the implantation of germanium ions on the sidewall surface of the pseudo-gate, a high-k dielectric layer and a titanium nitride layer are retained at the corresponding location of the active region.

[0027] Optionally, after the modified layer is formed, the titanium nitride layer and the high-k dielectric layer are removed except at the location corresponding to the dummy gate.

[0028] Optionally, the thickness of the titanium nitride layer covering the active region is between 30 Å and 100 Å.

[0029] Optionally, the method for manufacturing the semiconductor structure further includes:

[0030] A silicon nitride layer and a second oxide layer are sequentially deposited on the polycrystalline silicon layer;

[0031] The step of patterning the polysilicon layer to form a pseudo-gate includes patterning the second oxide layer, the silicon nitride layer, and the polysilicon layer through photolithography and etching processes;

[0032] After removing the titanium nitride layer and high-k dielectric layer except at the location corresponding to the pseudo gate, sidewalls are deposited and etched to form a lightly doped drain region, and source and drain electrodes are formed.

[0033] After exposing the top surface of the dummy gate by chemical mechanical polishing, the dummy gate and the modified layer are removed.

[0034] According to another aspect of the present invention, a semiconductor device is provided. This semiconductor device is manufactured based on the semiconductor structure manufacturing method described above.

[0035] The unexpected technical effects of this invention are:

[0036] The semiconductor structure manufacturing method and semiconductor device provided in this application, after forming a dummy gate, implant germanium ions into the sidewall surface of the dummy gate to form a modification layer; the presence of the modification layer can prevent ions from being introduced into the dummy gate as impurities in the subsequent ion implantation process; the dummy gate without introduced impurity ions is easier to control and the removal effect is better, avoiding the residue of polysilicon in the dummy gate, thereby improving the filling quality of the subsequent metal gate and thus improving the quality of the semiconductor device.

[0037] Furthermore, implanting germanium ions into the dummy gate can significantly improve the wet etching rate of the dummy gate. By combining the first wet etching and the second wet etching, especially the use of a mixture of high-temperature phosphoric acid and ammonia-hydrogen peroxide in the second wet etching, the modified layer can be removed more effectively, greatly improving the residual problem of polysilicon.

[0038] Furthermore, the polysilicon residue of the spurious gate mainly occurs in the lower region. Since the introduction of germanium ions will improve the removal efficiency of the spurious gate, and the introduction of germanium ions in the upper region of the spurious gate sidewall is not necessary, germanium ions are injected along the first incident direction to form a first modified layer in the lower region of the spurious gate sidewall, and boron ions are injected along the second incident direction to form a second modified layer in the upper region of the spurious gate sidewall. By controlling the incident angle, the implantation position and concentration distribution of germanium and boron ions can be controlled, and the removal efficiency at different positions can be adjusted, thereby achieving controllable overall removal rate of the spurious gate and improving the flexibility of process control.

[0039] Furthermore, a high-k dielectric layer and a titanium nitride layer are covered on the active region. After the dummy gate is formed, the high-k dielectric layer and titanium nitride layer above the active region are retained, thereby avoiding the contamination of the active region by implanted ions when the modified layer is formed, ensuring that the electrical performance of the active region is not affected, and thus ensuring that the performance of the semiconductor device is not affected. Attached Figure Description

[0040] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0041] Figure 1 A schematic cross-sectional view of the semiconductor structure before dummy gate removal is shown according to the prior art;

[0042] Figure 2 A schematic cross-sectional view of a semiconductor structure after dummy gate removal according to the prior art is shown;

[0043] Figure 3 A schematic diagram illustrating the pseudo-gate removal effect according to the prior art is shown;

[0044] Figure 4 A flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of the present invention is shown;

[0045] Figures 5a to 5f A schematic cross-sectional view of some steps in a method for manufacturing a semiconductor structure according to a specific embodiment of the present invention is shown;

[0046] Figures 6a to 6c A schematic cross-sectional view of some steps in a method for manufacturing a semiconductor structure according to another specific embodiment of the present invention is shown;

[0047] Figure 7 This diagram shows a schematic cross-sectional view of a semiconductor structure manufacturing method according to another specific embodiment of the present invention after the formation of the modified layer;

[0048] Figure 8 A schematic diagram showing the parameter comparison for pseudo-gate removal according to an embodiment of the present invention is shown;

[0049] Figure 9 A schematic diagram illustrating the effect of dummy gate removal in a semiconductor structure manufacturing method according to an embodiment of the present invention is shown.

[0050] Explanation of reference numerals in the attached figures:

[0051] 100 - Substrate; 200 - Polysilicon layer; 210 - Pseudo-gate; 211 - First modified layer; 212 - Second modified layer; 300 - High-k dielectric layer; 400 - Titanium nitride layer; 500 - First oxide layer; 600 - Silicon nitride layer; 700 - Second oxide layer. Detailed Implementation

[0052] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown in the drawings.

[0053] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. Many specific details of the invention, such as the structure, materials, dimensions, processing techniques, and methods of the components, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0054] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0055] As the feature size of semiconductor devices continues to decrease according to Moore's Law, below the 28nm process node, the gate of semiconductor devices typically employs a high-dielectric-constant gate dielectric-metal gate process. High-dielectric-constant gate dielectric-metal gates are primarily used to replace traditional silicon dioxide gate dielectrics and polysilicon gate structures. Replacing silicon dioxide with a high-dielectric-constant material as the gate dielectric allows for a greater physical thickness to be used for the same capacitance, thus significantly suppressing tunneling leakage current. Replacing polysilicon gates with metal gates fundamentally eliminates the polysilicon depletion effect.

[0056] In high-k dielectric-metal gate processes, the dummy gate (usually made of polysilicon) is a temporary gate structure formed in early process steps to support subsequent high-temperature process steps such as source / drain formation, sidewall (spacer) fabrication, and stress engineering. After the high-temperature processes are completed, the dummy gate needs to be removed by etching, and metal gate material is deposited at the location of the dummy gate to form the final gate structure.

[0057] The inventors discovered that during ion implantation, dummy gates introduce impurity ions (such as B ions). The introduction of impurity ions significantly reduces the etching rate during dummy gate removal, making it difficult for polysilicon to be completely removed during etching, especially leaving residues on the gate sidewalls and bottom. This affects the filling quality and interface characteristics of the metal gate, ultimately impacting the electrical performance and product yield of semiconductor devices.

[0058] Figure 4A flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of the present invention is shown. Figure 4 As shown, a method for manufacturing a semiconductor structure according to an embodiment of the present invention includes the following steps:

[0059] In step S101, a substrate is provided, and a polycrystalline silicon layer is formed on the substrate;

[0060] A substrate is provided, such as a silicon substrate. A polycrystalline silicon layer is deposited on the substrate. Optionally, a sacrificial gate oxide layer is also formed between the substrate and the polycrystalline silicon layer. The sacrificial gate oxide layer serves as a temporary dielectric to prevent direct contact between the polycrystalline silicon layer and the substrate. The sacrificial gate oxide layer is, for example, silicon oxide.

[0061] In step S102, the polysilicon layer is patterned to form a pseudo-gate;

[0062] For example, a mask layer (silicon nitride layer) is formed on a polysilicon layer, and the polysilicon layer is patterned by photolithography / etching to form a strip-shaped pseudo-gate structure.

[0063] In step S103, germanium ions are implanted into the sidewall surface of the dummy gate to form a modified layer;

[0064] Germanium (Ge) ions are implanted into the sidewall surface of the dummy gate, thereby forming a germanium-rich modified layer on the dummy gate sidewall.

[0065] In step S104, the dummy gate and the modified layer are removed;

[0066] The dummy gate and the modified layer on the dummy gate sidewall surface are removed by etching. Optionally, a first wet etching process is used to remove the dummy gate and the modified layer. The first wet etching process is mainly used to remove the dummy gate. After using the first wet etching process, a second wet etching process is used to remove the remaining modified layer. The second wet etching process is mainly used to remove the modified layer, and the second wet etching process can selectively use reagents that are effective at removing germanium-containing polycrystalline silicon.

[0067] In step S105, a metal gate is formed to replace the dummy gate.

[0068] A metal gate is formed at the original pseudo-gate location.

[0069] In an optional embodiment of the present invention, the method for manufacturing the semiconductor structure further includes: forming a high-k dielectric layer on a substrate, the high-k dielectric layer covering the active area (AA region); forming a titanium nitride layer on the high-k dielectric layer, the titanium nitride layer covering the active area; and forming a polycrystalline silicon layer on the titanium nitride layer. During the implantation of germanium ions on the sidewall surface of the dummy gate, the high-k dielectric layer and the titanium nitride layer are retained at the corresponding location of the active area. Optionally, the thickness of the titanium nitride layer covering the active area is between 30 Å and 100 Å. Optionally, after forming the modified layer, the titanium nitride layer and the high-k dielectric layer are removed except at the corresponding location of the dummy gate.

[0070] Figures 5a to 5f A schematic cross-sectional view of some steps in a method for manufacturing a semiconductor structure according to a specific embodiment of the present invention is shown below. Figures 5a-5f This embodiment will be described in detail:

[0071] like Figure 5a As shown, a high-k dielectric layer 300 and a titanium nitride (TIN) layer 400 are formed on the substrate 100. A polycrystalline silicon layer 200 is deposited on the titanium nitride layer 400. A silicon nitride (SIN) layer 600 and a second oxide layer 700 are sequentially deposited on the polycrystalline silicon layer 200. The high-k dielectric layer is, for example, an HfO2 layer.

[0072] The second oxide layer 700, silicon nitride layer 600, and polysilicon layer 200 are patterned using photolithography and etching processes to form a pseudo-gate structure (pseudo-gate 210), such as... Figure 5b As shown. Optionally, during the formation of the dummy gate 210, the high-k dielectric layer 300 and the titanium nitride layer 400 at the corresponding positions of the active region are retained to avoid introducing Ge elements into the active region and causing contamination during subsequent germanium ion implantation. Optionally, the thickness of the retained titanium nitride layer 400 is between 30 Å and 100 Å to ensure that it can effectively block the diffusion of germanium elements into the active region in subsequent processes.

[0073] Germanium (Ge) ions are implanted into the sidewall surface of the dummy gate 210 to form a modified layer (first modified layer 211), such as... Figure 5c As shown. Optionally, germanium ions are implanted into the dummy gate surface using high-temperature diffusion, thereby enriching germanium ions on the exposed dummy gate sidewalls to form a first modified layer 211. Optionally, the high-temperature diffusion temperature is between 700 and 1000°C. In this embodiment, during the high-temperature diffusion process, germanium elements are enriched on the dummy gate sidewall surface and form a stable modified layer, which can effectively enhance the selectivity and rate of subsequent wet etching.

[0074] The exposed titanium nitride layer 400 and the underlying high-k dielectric layer 300 are removed by etching (the titanium nitride layer 400 and the high-k dielectric layer 300 at the corresponding position (directly below) of the pseudo gate 210 are retained), resulting in the following... Figure 5d The structure shown.

[0075] Following this, steps such as deposition and etching to form the spacer (sidewall), formation of the LDD (lightly doped drain region), formation of the S / D (source / drain), and formation of the first oxide layer 500 are performed, until the dummy gate 210 is drained through a chemical mechanical polishing (CMP) process, resulting in the desired product. Figure 5e The structure shown is illustrated. Ion implantation is typically involved in the formation of sidewalls, source electrodes, and drain electrodes. The presence of the modified layer effectively prevents impurities from being introduced into the dummy gate during ion implantation, thus ensuring the removal effect during subsequent dummy gate removal. It should be noted that the above steps can all be completed using conventional processes, and the structures involved can also be conventional structures, which does not constitute a limitation on the scheme of this application.

[0076] After completing the chemical mechanical polishing and exposing the top surface of the dummy gate 210, the dummy gate 210 and the first modified layer 211 on the surface of the dummy gate 210 are etched away (the titanium nitride layer 400 and the high-k dielectric layer 300 below the dummy gate 210 are retained), resulting in the following: Figure 5f The structure shown.

[0077] Optionally, a combination of first and second wet etching is used to remove the dummy gate 210 and the first modified layer 211. First, a first wet etching process is used, for example, using TMAH (Tetramethyl ammonium hydroxide). This first wet etching effectively removes the polysilicon material from the dummy gate 210. After the first wet etching, a second wet etching process is used, for example, using a combination of high-temperature phosphoric acid and APM. This combination effectively removes the germanium-containing dummy gate (first modified layer 211). High-temperature phosphoric acid refers to a high-concentration phosphoric acid solution heated to a specific temperature, between 150°C and 180°C. APM (Ammonium Hydrogen Peroxide Mixture) is a mixture of ammonia and hydrogen peroxide. Optionally, the etching temperature of the second wet etching is between 50°C and 150°C, and the etching time is between 2 minutes and 10 minutes. Optionally, a dry etching step may be performed before the first wet etching and the second wet etching.

[0078] After removing the dummy gate 210 and the first modified layer 211, a metal gate material is redeposited to fill the space previously occupied by the dummy gate, forming a metal gate and completing the gate replacement process.

[0079] Figures 6a to 6c A schematic cross-sectional view of some steps in a method for manufacturing a semiconductor structure according to another specific embodiment of the present invention is shown. Figures 6a-6c The illustrated embodiments and Figures 5a-5f The difference in the illustrated embodiment lies in the structure and formation method of the modified layer; the remaining structures and process steps are basically the same. The following is in conjunction with... Figures 6a-6c This embodiment will be described in detail:

[0080] After the dummy gate 210 is formed, germanium (Ge) ions and boron (B) ions are implanted at different locations on the sidewall surface of the dummy gate 210 to form a first modified layer 211 and a second modified layer 212, respectively. Optionally, germanium ions are implanted / diffused in the lower region (the portion closer to the substrate) of the sidewall surface of the dummy gate 210 to form the first modified layer 211. Boron ions are implanted in the upper region (the portion farther from the substrate) of the sidewall surface of the dummy gate 210 to form the second modified layer 212. The first modified layer 211 and the second modified layer 212 are connected to form a continuous modified layer structure that covers the entire sidewall of the dummy gate 210 and extends to the substrate surface.

[0081] Next, the exposed titanium nitride layer 400 and the underlying high-k dielectric layer 300 are etched away (retaining the titanium nitride layer 400 and the high-k dielectric layer 300 directly below the dummy gate 210). Then, steps such as deposition and etching to form sidewalls, lightly doped drain regions, and source / drain electrodes are performed until the dummy gate 210 is drained through a chemical mechanical polishing (CMP) process, resulting in the desired appearance. Figure 6b The structure shown.

[0082] After completing the chemical mechanical polishing and exposing the top surface of the dummy gate 210, the dummy gate 210 and the first modified layer 211 and the second modified layer 212 on the surface of the dummy gate 210 are etched away (the titanium nitride layer 400 and the high-k dielectric layer 300 below the dummy gate 210 are retained), resulting in the following: Figure 6c The structure shown.

[0083] After removing the dummy gate 210, the first modified layer 211, and the second modified layer 212, a metal gate material is redeposited to fill the space previously occupied by the dummy gate, forming a metal gate and completing the gate replacement process.

[0084] Figure 7 This diagram shows a schematic cross-sectional view of a semiconductor structure manufacturing method according to another specific embodiment of the present invention after the formation of the modified layer. Figure 7 The illustrated embodiments and Figure 6a The difference between the embodiments shown lies in the structure of the modified layer; the remaining structures and process steps are basically the same. The following section will discuss this further. Figure 7 This embodiment will be described in detail:

[0085] After the dummy gate 210 is formed, germanium (Ge) ions and boron (B) ions are implanted at different locations on the sidewall surface of the dummy gate 210 to form a first modified layer 211 and a second modified layer 212, respectively. The first modified layer 211 is located in the lower region of the sidewall of the dummy gate 210 (the part close to the substrate), and the second modified layer 212 is located in the upper-middle region of the sidewall of the dummy gate 210 (the part far from the substrate); the thickness of the first modified layer 211 is less than the thickness of the second modified layer 212. Figure 6a In the embodiment shown, the thickness of the first modified layer 211 is greater than the thickness of the second modified layer 212.

[0086] exist Figure 7 In the illustrated scheme, germanium ions are implanted along the first incident (angle) direction to form a first modified layer 211 in the lower region of the sidewall of the dummy gate 210; boron ions are implanted along the second incident (angle) direction to form a second modified layer 212 in the upper region of the sidewall of the dummy gate 210. In this embodiment, the implantation concentration distribution (formation location) of germanium ions and boron ions is controlled by different incident angles using the shielding effect.

[0087] As discussed above, the introduction of germanium ions improves the removal efficiency of dummy gates. However, if germanium ions are implanted across the entire sidewall of the dummy gate, the removal rate will be too fast and difficult to control. Furthermore, since the polysilicon residue from the dummy gate mainly occurs in the lower region, introducing germanium ions into the upper region of the dummy gate sidewall is not necessary. Figures 6a to 6c as well as Figure 7 In the embodiments shown, a first modified layer implanted with germanium ions is formed in the lower region of the dummy gate sidewall, and a second modified layer implanted with boron ions is formed above the first modified layer. The implantation of germanium ions in the first modified layer can avoid polysilicon residue, and the implantation of boron ions in the second modified layer can adjust (reduce) the removal efficiency of the dummy gate, thereby achieving controllable overall removal rate of the dummy gate and improving the flexibility of process control. Furthermore, by controlling the incident angle, the implantation position and concentration distribution of germanium and boron ions can be controlled, thereby achieving process control simply and conveniently.

[0088] Figure 8 A schematic diagram showing parameter comparisons for pseudo-gate removal according to an embodiment of the present invention is illustrated. For example... Figure 8 As shown, a combination of high-temperature phosphoric acid and APM was used to remove boron-containing substances of 1×10⁻⁶. 20 Taking a pseudo-gate of atoms / cm³ as an example, according to Figure 8 The experimental data shown demonstrates that introducing germanium ions significantly improves the wet etching rate of dummy gate polysilicon, especially under high-temperature conditions. The wet etching rate increases dramatically when the amount of germanium ions introduced is large.

[0089] Figure 9A schematic diagram illustrating the effect of dummy gate removal in a semiconductor structure manufacturing method according to an embodiment of the present invention is shown. (Comparison) Figure 3 and Figure 9 It is known that existing dummy gate removal methods suffer from difficulties in controlling the polysilicon critical dimension (Poly CD), resulting in abnormal morphology (polysilicon residue) after removal. The semiconductor structure manufacturing method provided in this application significantly reduces polysilicon residue on the bottom and sidewalls after dummy gate removal, resulting in a clearer and smoother interface. The quality of the replaced metal gate is significantly improved, effectively enhancing the performance of the semiconductor device.

[0090] According to another aspect of the present invention, a semiconductor device is provided. This semiconductor device is manufactured based on the semiconductor structure manufacturing method described above.

[0091] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0092] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor structure, comprising: A substrate is provided, and a polycrystalline silicon layer is formed on the substrate; The polysilicon layer is patterned to form a pseudo-gate; Germanium ions are implanted into the sidewall surface of the dummy gate to form a modified layer; Remove the dummy gate and the modified layer; as well as Form a metal gate to replace the dummy gate. Among these, after the modified layer is formed, a sidewall is formed; The step of implanting germanium ions into the sidewall surface of the dummy gate to form a modified layer includes: Germanium ions are injected along the first incident direction to form a first modified layer in the lower region of the pseudo-gate sidewall; Boron ions are injected along the second incident direction to form a second modified layer in the upper region of the pseudo-gate sidewall; The first modified layer and the second modified layer are connected to form a continuous modified layer; the modified layer covers the entire sidewall of the pseudo gate.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein, The step of implanting germanium ions into the sidewall surface of the dummy gate to form a modified layer includes: Germanium ions are injected into the sidewall surface of the dummy gate using a high-temperature diffusion method to enrich the exposed sidewall surface of the dummy gate with germanium ions, thereby forming the modified layer.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein, The temperature of the high-temperature diffusion is between 700°C and 1000°C.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein, The removal of the dummy gate and the modified layer includes: The dummy gate and the modified layer are removed using a first wet etching process; After the first wet etching is used, the remaining modified layer is removed by the second wet etching.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein, The method for manufacturing the semiconductor structure further includes: A high-k dielectric layer is formed on the substrate, and the high-k dielectric layer covers the active region; A titanium nitride layer is formed on the high-k dielectric layer, and the titanium nitride layer covers the active region; The polycrystalline silicon layer is formed on the titanium nitride layer. During the implantation of germanium ions on the sidewall surface of the pseudo-gate, a high-k dielectric layer and a titanium nitride layer are retained at the corresponding location of the active region.

6. The method for manufacturing a semiconductor structure according to claim 5, wherein, After forming the modified layer, the titanium nitride layer and the high-k dielectric layer are removed except at the location corresponding to the pseudo gate.

7. The method for manufacturing a semiconductor structure according to claim 5, wherein, The thickness of the titanium nitride layer covering the active region is between 30 Å and 100 Å.

8. The method for manufacturing a semiconductor structure according to claim 5, wherein, The method for manufacturing the semiconductor structure further includes: A silicon nitride layer and a second oxide layer are sequentially deposited on the polycrystalline silicon layer; The step of patterning the polysilicon layer to form a pseudo-gate includes patterning the second oxide layer, the silicon nitride layer, and the polysilicon layer through photolithography and etching processes; After removing the titanium nitride layer and high-k dielectric layer except at the location corresponding to the pseudo gate, sidewalls are deposited and etched to form a lightly doped drain region, and source and drain electrodes are formed. After exposing the top surface of the dummy gate by chemical mechanical polishing, the dummy gate and the modified layer are removed.

9. A semiconductor device manufactured based on a method for manufacturing a semiconductor structure as described in any one of claims 1-8.

Images