Integrated circuit device

Abstract

An integrated circuit device includes: a first nanosheet stack; a first source / drain connected to the first nanosheet stack; a first contact on the first source / drain; a second nanosheet stack; a second source / drain connected to the second nanosheet stack; a second contact on the second source / drain; and an insulating layer between the first nanosheet stack and the second nanosheet stack. Wherein the first contact comprises a first contact main body extending in a first direction and a first contact protrusion protruding from the first contact main body, and the second contact comprises a second contact main body extending in the first direction and a second contact protrusion protruding from the second contact main body, and the first contact protrusion and the second contact protrusion are spaced apart from each other in the first direction by an insulating layer therebetween, and each of the first contact protrusion and the second contact protrusion has an asymmetric shape in the first direction.

Description

Technical Field

[0001] The present invention relates to integrated circuit devices, and more specifically, to integrated circuit devices including contact plugs. Background Technology

[0002] As the integration density of integrated circuit devices increases, their size decreases, and scaling becomes increasingly challenging. Therefore, new approaches involving structural modifications are needed to improve the performance of integrated circuit devices, and integrated circuit devices equipped with transistors featuring novel structures, such as multi-gate transistors, have been proposed. Summary of the Invention

[0003] The present invention can provide integrated circuit devices with a reduced standard cell area.

[0004] According to one aspect of the present invention, an integrated circuit device is provided, comprising: a first standard cell, the first standard cell including a first nanosheet stack, a first source / drain electrically connected to the first nanosheet stack, and a first contact located on the first source / drain; a second standard cell, the second standard cell including a second nanosheet stack, a second source / drain electrically connected to the second nanosheet stack, and a second contact located on the second source / drain, wherein the second standard cell is adjacent to the first standard cell in a first direction; and an insulating layer extending in a vertical direction and overlapping a cell boundary in the vertical direction, the cell boundary being located between the first standard cell and the second standard cell in the first direction. Wherein, the vertical direction intersects the first direction, wherein the first contact includes: a first contact body extending in the first direction, and a first contact protrusion protruding from the upper surface of the first contact body in the vertical direction, wherein the second contact includes: a second contact body extending in the first direction, and a second contact protrusion protruding from the upper surface of the second contact body in the vertical direction, and wherein the first contact protrusion and the second contact protrusion are spaced apart from each other in the first direction by the insulating layer therebetween, and each of the first contact protrusion and the second contact protrusion is asymmetrical in the first direction.

[0005] According to another aspect of the present invention, an integrated circuit device is provided, comprising: a first standard cell, the first standard cell including a first nanosheet stack, a first source / drain electrically connected to the first nanosheet stack, and a first gate electrode extending around the first nanosheet stack; a second standard cell, the second standard cell including a second nanosheet stack, a second source / drain electrically connected to the second nanosheet stack, and a second gate electrode extending around the second nanosheet stack, wherein the second standard cell is adjacent to the first standard cell in a first direction; and an insulating layer extending in a vertical direction and overlapping a cell boundary in the vertical direction, the cell boundary being located in the first direction. Between the first standard unit and the second standard unit, wherein the vertical direction intersects the first direction, wherein the first gate electrode includes: a first electrode body extending in the first direction, and a first electrode protrusion protruding from the upper surface of the first electrode body in the vertical direction, wherein the second gate electrode includes: a second electrode body extending in the first direction, and a second electrode protrusion protruding from the upper surface of the second electrode body in the vertical direction, and wherein the first electrode protrusion and the second electrode protrusion are spaced apart from each other in the first direction by the insulating layer located therebetween, and each of the first electrode protrusion and the second electrode protrusion is asymmetrical in the first direction.

[0006] According to another aspect of the present invention, an integrated circuit device is provided, comprising: a first nanosheet stack and a second nanosheet stack, the first nanosheet stack and the second nanosheet stack being located on an active region of a substrate, wherein the first nanosheet stack and the second nanosheet stack are spaced apart from each other in a first direction parallel to the upper surface of the substrate; a first source / drain and a second source / drain, the first source / drain and the second source / drain being electrically connected to the first nanosheet stack and the second nanosheet stack, respectively; a first gate electrode and a second gate electrode, the first gate electrode and the second gate electrode extending in the first direction, wherein the first gate electrode and the second gate electrode are respectively Extending around the first nanosheet stack and the second nanosheet stack; a first metal layer, the first metal layer being located above the first gate electrode and the second gate electrode; a first contact, the first contact being located on the first source / drain electrode, wherein the first contact includes a first contact body extending in the first direction and a first contact protrusion protruding from the upper surface of the first contact body in a vertical direction perpendicular to the upper surface of the substrate; and a second contact, the second contact being located on the second source / drain electrode, wherein the second contact includes a second contact body extending in the first direction and a second contact protrusion protruding from the upper surface of the second contact body in the vertical direction. The first contact protrusion and the second contact protrusion are spaced apart from each other in the first direction, and each of the first contact protrusion and the second contact protrusion is asymmetrical in the first direction. Attached Figure Description

[0007] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This illustrates the layout of an integrated circuit device according to some embodiments; Figure 2 It is according to some embodiments along Figure 1 Example of a cross-sectional view taken by line X1-X1'; Figure 3 It is according to some embodiments along Figure 1 Example of a cross-sectional view taken by line X2-X2'; Figure 4A , Figure 4B , Figure 4C and Figure 4D This illustrates the manufacture according to some embodiments. Figure 1 A cross-sectional view of the method for the integrated circuit device shown; Figure 5 It is according to some embodiments along Figure 1 Example of a cross-sectional view taken by line X1-X1'; Figure 6 This illustrates the layout of an integrated circuit device according to some embodiments; Figure 7 It is according to some embodiments along Figure 6 A cross-sectional view taken from line X3-X3'; Figure 8 It is according to some embodiments along Figure 6 A cross-sectional view taken from line X4-X4'; Figure 9 This illustrates the layout of an integrated circuit device according to some embodiments; Figure 10 It is according to some embodiments along Figure 9 A cross-sectional view taken from line X5-X5'; Figure 11 This illustrates the layout of an integrated circuit device according to some embodiments; Figure 12 It is according to some embodiments along Figure 11 A cross-sectional view taken from line X6-X6'; Figure 13A , Figure 13B , Figure 13C and Figure 13D This illustrates the manufacture according to some embodiments. Figure 11 A cross-sectional view of the method for the integrated circuit device shown; Figure 14 It is according to some embodiments along Figure 11 Example of a cross-sectional view taken by line X6-X6'; Figure 15 This illustrates the layout of an integrated circuit device according to some embodiments; Figure 16 This illustrates the layout of an integrated circuit device according to some embodiments; Figure 17 This illustrates the layout of an integrated circuit device according to some embodiments; Figure 18 This is a flowchart illustrating a method for manufacturing an integrated circuit according to some embodiments. Detailed Implementation

[0008] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the drawings, unless otherwise described, the same reference numerals may denote the same elements, and repeated descriptions thereof may be omitted. The terms “first,” “second,” etc., may be used herein only to distinguish one component, layer, orientation, etc., from another component, layer, orientation, etc. The term “connection” may be used herein to refer to a physical and / or electrical connection. When a component or layer is referred to herein as being “directly” on, “directly in contact with,” or “directly connected,” there is no intermediate component or layer. When viewed in a particular direction or along a line extending in a plane perpendicular to the particular direction, components or layers described with reference to “overlapping” in the particular direction may at least partially obscure each other. The terms “encircle,” “cover,” or “fill,” as may be used herein, do not necessarily need to completely encircle, cover, or fill the described element or layer, but may refer, for example, to partially encircle, cover, or fill the described element or layer, for example, where there are widespread gaps, spaces, or other discontinuities. Spatial relative terms such as “above,” “upper,” “upper part,” “upper surface,” “lower,” “below,” “lower part,” “lower surface,” “side surface,” etc., may be indicated by reference to the accompanying drawings, unless otherwise stated. It will be understood that such spatial relative terms are intended to include not only the orientations shown in the drawings but also different orientations of the device in use or operation.

[0009] In this specification, the X-axis direction may be referred to as the first direction, the Y-axis direction may be referred to as the second direction, and the Z-axis direction may be referred to as the vertical direction. The plane formed by the X-axis and Y-axis may be referred to as the horizontal plane. Elements arranged relative to other elements in the positive (+) Z-axis direction may be referred to as being above other elements, and elements arranged relative to other elements in the negative (-) Z-axis direction may be referred to as being below other elements.

[0010] Integrated circuits can be designed by arranging multiple standard cells. The term "standard cell" refers to a unit in the layout of an integrated circuit, and in some embodiments may also be referred to as a "cell". Standard cells can be designed such that they can include multiple transistors performing predefined functions. This standard cell methodology can involve pre-preparing standard cells with various functions and combining these standard cells to design application-specific large-scale integrated circuits customized to customer or user specifications. Standard cells can be pre-designed and verified before being registered to a standard cell library, and integrated circuits can be designed using standard cells through computer-aided design (CAD), logic design, placement, and routing.

[0011] Figure 1 This illustrates the layout of an integrated circuit device 10 according to some embodiments.

[0012] refer to Figure 1The integrated circuit device 10 may include logic cells or standard cells, and each standard cell may include a transistor. For example, the integrated circuit device 10 may include a first standard cell 11 and a second standard cell 12 that are adjacent to each other in a first direction. Both the first standard cell 11 and the second standard cell 12 may be defined by a boundary BD. In this specification, the boundary BD located between the first standard cell 11 and the second standard cell 12 and extending along a second direction (in the first direction) is referred to as a "cell boundary CBD". The first direction and the second direction may intersect each other (e.g., cross). For example, the first standard cell 11 and the second standard cell 12 may form AND gates, NAND gates, OR gates, NOR gates, XOR gates, XNOR gates, inverters, OAI gates, AOI gates, adders, buffers, multiplexers, flip-flops, latches, etc.

[0013] Both the first standard unit 11 and the second standard unit 12 may include a gate-all-around (GAA) field-effect transistor. A GAA transistor may include a channel or active region in the shape of a nanowire or nanosheet, and a gate extending around (e.g., surrounding) the active region. For example, the integrated circuit device 10 may include a nanosheet stack NSS, a contact CA, a via VA, a gate electrode GT, and a first metal layer M1 to implement a GAA transistor. In some embodiments, each of the first standard unit 11 and the second standard unit 12 may include various transistors, such as a FinFET or a planar transistor, and the embodiments described below can be applied to GAA transistors, FinFETs, planar transistors, etc.

[0014] Each nanosheet stack NSS may include multiple nanosheets, which are separated from each other in a vertical direction and extend in a second direction. The integrated circuit device 10 may also include an insulating layer 130 that overlaps with the cell boundary CBD in the vertical direction and extends in the second direction. In this case, the insulating layer 130 may extend in the vertical direction and therefore may be referred to as an insulating wall or a sheet separator wall. Hereinafter, the insulating layer 130 may be referred to as insulating wall 130. Furthermore, the integrated circuit device 10 may also include insulating walls 130a and 130b, where insulating wall 130a (in the vertical direction) overlaps with the left boundary BD of the first standard cell 11 and extends in the second direction, and insulating wall 130b (in the vertical direction) overlaps with the right boundary BD of the second standard cell 12 and extends in the second direction. The left boundary BD of the first standard cell 11 may be opposite to the cell boundary CBD in the first direction with respect to the first standard cell 11. The right boundary BD of the second standard cell 12 may be opposite to the cell boundary CBD in the first direction with respect to the second standard cell 12. The cell boundary CBD can be located in the first direction between the left boundary BD of the first standard cell 11 and the right boundary BD of the second standard cell 12.

[0015] According to the current embodiment, insulating walls 130, 130a, and 130b can be used to implement forksheet transistors from nanosheet stacked NSSs. As described above, insulating wall 130 can form spacers between the nanosheet stacked NSSs, thereby reducing the area of ​​the transistor and the area of ​​the first standard cell 11 and the second standard cell 12. Furthermore, insulating wall 130 can be formed along the cell boundary CBD, with the nanosheet stacked NSSs located on both sides of insulating wall 130 (e.g., opposite sides in the first direction), thereby reducing the distance between the nanosheet stacked NSSs and achieving area reduction.

[0016] Contacts CA can all extend in a first direction. For example, first standard unit 11 may include a first contact 110, and second standard unit 12 may include a second contact 120. The first contact 110 and the second contact 120 may be separated from each other in the first direction. The first contact 110 may overlap with the second contact 120 in the first direction. For example, the first contact 110 and the second contact 120 may be arranged as a line. Passages VA may be arranged above the first contact 110 and the second contact 120, respectively. In an embodiment, each of the first contact 110 and the second contact 120 may include: a contact body extending in the first direction, and a contact protrusion extending from the contact body and corresponding to the passage VA. The contact pattern may be selectively recessed to form the contact body and contact protrusion as described above. This can improve the short margin between contact plugs adjacent to the contact protrusion corresponding to the passage VA, for example, the short margin between a gate contact and a source / drain contact. Reference Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 4C and Figure 4D The corresponding implementation is described below.

[0017] The gate electrode GT may include a first gate electrode GT1 and a second gate electrode GT2, both extending in a first direction. For example, the first standard unit 11 may include the first gate electrode GT1, and the second standard unit 12 may include the second gate electrode GT2. The first gate electrode GT1 and the second gate electrode GT2 may be separated from each other in the first direction. The first gate electrode GT1 may overlap with the second gate electrode GT2 in the first direction. For example, the first gate electrode GT1 and the second gate electrode GT2 may be arranged in a line.

[0018] A first metal layer M1 can be disposed on (above) the first standard unit 11 and the second standard unit 12. The first metal layer M1 may include first metal lines M1a, M1b, M1c, and M1d, which are separated from each other in a first direction and extend in a second direction, and second metal lines M1e, M1f, M1g, and M1h. The first metal lines M1a, M1b, M1c, and M1d can be arranged on (above) the first standard unit 11, thus the first standard unit 11 can have a 4-track structure. The second metal lines M1e, M1f, M1g, and M1h can be arranged on (above) the second standard unit 12, thus the second standard unit 12 can have a 4-track structure.

[0019] The first metal wires M1a, M1b, M1c, and M1d can be arranged as inbound metal wires within the boundary BD of the first standard element 11, and can (in the vertical direction) not overlap with the element boundary CBD. The second metal wires M1e, M1f, M1g, and M1h can be arranged as inbound metal wires within the boundary BD of the second standard element 12, and can (in the vertical direction) not overlap with the element boundary CBD.

[0020] According to the current embodiment, the via VA can be formed by an etching process using a first hard mask or a first mask pattern HM1. For example, the first mask pattern HM1 can be implemented as a bar-shaped rectangle extending in a first direction, but the inventive concept is not limited thereto. The first mask pattern HM1 can be implemented in any shape as long as its length in the first direction is greater than its length in the second direction. The first mask pattern HM1 can overlap (in the vertical direction) with the cell boundary CBD, and the via VA adjacent to the cell boundary CBD can be formed by an etching process using the first mask pattern HM1. Therefore, the via VA can be etched asymmetrically relative to the cell boundary CBD, and thus, the via VA can have an asymmetrical shape in the first direction. Reference Figure 2 and Figure 3 The asymmetric shape of pathway VA is further described.

[0021] Figure 2 It is according to some embodiments along Figure 1 Example of a cross-sectional view taken by line X1-X1'. Figure 3 It is according to some embodiments along Figure 1 Example of a cross-sectional view taken by line X2-X2'.

[0022] refer to Figures 1 to 3 The integrated circuit device 10 may include a substrate 100 and active regions 105. Each active region 105 may extend in a second direction and may be defined by a device isolation layer (e.g., shallow trench isolation (STI)). Each active region 105 may be adjacent to at least one device isolation layer. As described above, an active region 105 that is part of the substrate 100 may correspond to a vertically protruding portion of the substrate 100 and may therefore be referred to as a finned active region.

[0023] The nanosheet stack NSS1 may include a first nanosheet NS1, a second nanosheet NS2, and a third nanosheet NS3 overlapping the active region 105 in a vertical direction. However, the inventive concept is not limited thereto, and the number of nanosheets included in the nanosheet stack NSS1 may vary depending on the embodiment. The first gate electrode GT1 may extend around (e.g., surround) the nanosheet stack NSS1 and extend in a first direction. The first gate electrode GT1 may include a metal, a metal nitride, a metal carbide, and / or a combination thereof.

[0024] The gate dielectric layer GI can be disposed between the nanosheet stack NSS1 and the first gate electrode GT1. Alternatively, the gate dielectric layer GI can be disposed between the substrate 100 and the first gate electrode GT1. For example, the gate dielectric layer GI can have a stacked structure of an interface layer and a high-k dielectric layer. The interlayer insulating layer ILD can be disposed on (above) the first gate electrode GT1.

[0025] The first standard unit 11 may further include a first source / drain SD1a located on (above) the active region 105, and the second standard unit 12 may further include a second source / drain SD2a located on (above) the active region 105. A first contact 110 may be disposed between the first source / drain SD1a and at least one first metal line (e.g., first metal line M1d), and may electrically connect the first source / drain SD1a and at least one first metal line (e.g., first metal line M1d) to each other. A second contact 120 may be disposed between the second source / drain SD2a and at least one second metal line (e.g., second metal line M1e), and may electrically connect the second source / drain SD2a and at least one second metal line (e.g., second metal line M1e) to each other. The first interlayer insulating layer ILD1 can be disposed on the substrate 100 and the first source / drain SD1a and the second source / drain SD2a (above), and the second interlayer insulating layer ILD2 can be disposed on the first contact 110 and the second contact 120 (above).

[0026] The first contact 110 may include a first contact body 110a extending in a first direction above the first source / drain SD1a, and a first contact protrusion 110b protruding from the upper surface of the first contact body 110a in a vertical direction. For example, the first contact body 110a and the first contact protrusion 110b may form a single body without an interface therebetween. In other words, the first contact body 110a and the first contact protrusion 110b may be portions of a single body comprising the same material. The second contact 120 may include a second contact body 120a extending in a first direction above the second source / drain SD2a, and a second contact protrusion 120b protruding from the upper surface of the second contact body 120a in a vertical direction. For example, the second contact body 120a and the second contact protrusion 120b may form a single body without an interface therebetween. In other words, the second contact body 120a and the second contact protrusion 120b may be portions of a single body comprising the same material.

[0027] The first contact protrusion 110b and the second contact protrusion 120b can be separated from each other by the insulating wall 130, and both can be asymmetrical in the first direction. For example, an etching process can be performed using a first mask pattern HM1 (described in detail later) to asymmetrically form the first contact protrusion 110b and the second contact protrusion 120b based on the cell boundary CBD, so that both the first contact protrusion 110b and the second contact protrusion 120b can be asymmetrical in the first direction.

[0028] For example, the first angle between the left side of the first contact protrusion 110b (the side farther from the cell boundary CBD in the first direction) and the horizontal plane of the substrate 100 may be smaller than the second angle between the right side of the first contact protrusion 110b (the side closer to the cell boundary CBD in the first direction) and the horizontal plane of the substrate 100. For example, the first angle may be in the range of (about) 0° to less than (about) 90°, and the second angle may be (about) 90° and / or greater than the first angle. For example, the third angle between the right side of the second contact protrusion 120b (the side farther from the cell boundary CBD in the first direction) and the horizontal plane of the substrate 100 may be smaller than the fourth angle between the left side of the second contact protrusion 120b (the side closer to the cell boundary CBD in the first direction) and the horizontal plane of the substrate 100. For example, the third angle may be in the range of (about) 0° to less than (about) 90°, and the fourth angle may be (about) 90° and / or greater than the third angle.

[0029] At least one first metal line (e.g., first metal line M1d) may be disposed on (above) the first contact protrusion 110b, and the first source / drain SD1a may be electrically connected to at least one first metal line (e.g., first metal line M1d) via the first contact 110 (first contact body 110a and / or first contact protrusion 110b). For example, the first contact protrusion 110b may correspond to the passage VA. The upper surface of the first contact protrusion 110b may directly contact the lower surface of at least one first metal line (e.g., first metal line M1d), thus the first contact 110 may be directly connected to at least one first metal line (e.g., first metal line M1d) without any additional structure in between. Because the first contact protrusion 110b and at least one first metal line (e.g., first metal line M1d) are connected to each other as described above, the interface resistance between the first contact protrusion 110b and the adjacent contact plug can be reduced.

[0030] At least one second metal line (e.g., second metal line M1e) may be disposed on (above) the second contact protrusion 120b, and the second source / drain SD2a may be electrically connected to at least one second metal line (e.g., second metal line M1e) via the second contact 120 (second contact body 120a and / or second contact protrusion 120b). For example, the second contact protrusion 120b may correspond to the passage VA. The upper surface of the second contact protrusion 120b may directly contact the lower surface of at least one second metal line (e.g., second metal line M1e), thus the second contact 120 may be directly connected to at least one second metal line (e.g., second metal line M1e) without any additional structure in between. Because the second contact protrusion 120b and at least one second metal line (e.g., second metal line M1e) are connected to each other as described above, the interface resistance between the second contact protrusion 120b and the adjacent contact plug can be reduced.

[0031] In related technologies, etching processes can be performed using multiple mask patterns, each corresponding to a pathway VA, to form two pathways VA facing each other across the cell boundary CBD. In this case, to ensure the distance between contacts and / or contact plugs defined by design rules, the wiring metal lines can be designed to be separate from the cell boundary CBD. Additional metal lines overlapping the cell boundary CBD are provided to maintain the metal spacing and the distance between contacts and contact plugs. Therefore, five metal lines are arranged above each standard cell (exceeding the actual required number of wiring metal lines). Thus, each standard cell has a 5-track structure, resulting in an increase in the area of ​​each standard cell and an increase in the area of ​​the integrated circuit device.

[0032] According to the current embodiment, the first contact body 110a and the second contact body 120a can first be separated from each other based on the insulating wall 130 formed for device isolation. Then, the two pathways VA adjacent to the cell boundary CBD can be etched at once using a mask pattern (i.e., the first mask pattern HM1 (described in detail later)) to form the first contact bump 110b and the second contact bump 120b. When the pathways VA face each other across the cell boundary CBD as described above, since the first contact body 110a and the second contact body 120a have been separated from each other by the insulating wall 130, the node separation between cells can be achieved by forming the first contact bump 110b and the second contact bump 120b based on a mask pattern (i.e., the first mask pattern HM1).

[0033] Therefore, compared to related technologies, the distance between the paths VA facing each other across the cell boundary CBD can be reduced, thus eliminating the need to increase the metal lines overlapping with the cell boundary CBD. Consequently, the metal spacing of the first metal layer M1 can be increased, thereby reducing the resistance or capacitance of the first metal layer M1. Furthermore, since no metal lines overlapping with the cell boundary CBD are required, the first metal layer M1 of each standard cell can have a 4-track structure. Therefore, the area of ​​each standard cell can be reduced, and the area of ​​the integrated circuit device 10 can also be reduced.

[0034] Figure 4A , Figure 4B , Figure 4C and Figure 4D This illustrates the manufacture according to some embodiments. Figure 1 A cross-sectional view of the method of the integrated circuit device 10 shown. Here, Figure 4A , Figure 4B , Figure 4C and Figure 4D Corresponding to along Figure 1 The cross-sectional view taken by line X1-X1'.

[0035] refer to Figure 1 and Figure 4A The substrate 100 may have an upper surface extending in a first direction and a second direction. The substrate 100 may include, for example, semiconductor materials, such as group IV semiconductors, group III-V compound semiconductors, and / or group II-VI compound semiconductors. For example, group IV semiconductors may include silicon, germanium, and / or silicon-germanium. The substrate 100 may be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, etc.

[0036] A device isolation layer STI may define an active region 105 in a substrate 100. For example, the active region 105 of the substrate 100 may be adjacent to the device isolation layer STI in the substrate 100. In some embodiments, the device isolation layer STI may further include regions that extend in a stepped manner to a deeper portion of the lower part of the substrate 100. The device isolation layer STI may expose the upper surface of the active region 105. In some embodiments, the device isolation layer STI may partially expose the upper portion of the active region 105. In an embodiment, the device isolation layer STI may have a curved upper surface such that the horizontal height of the upper surface increases in the direction toward the active region 105. The device isolation layer STI may include an insulating material. For example, the device isolation layer STI may include oxides, nitrides, and / or combinations thereof.

[0037] Active regions 105 may be defined within the substrate 100 by a device isolation layer STI and may extend in a second direction. Active regions 105 may have a structure that protrudes (in the vertical direction) from the substrate 100. In some embodiments, the upper portion of the active region 105 may protrude to a specific height above the upper surface of the device isolation layer STI. Active regions 105 may be part of the substrate 100 or may include an epitaxial layer grown from the substrate 100. However, active regions 105 may be located at the gate electrode GT (reference...). Figure 1 The two sides of the electrode are partially recessed to form a recessed region, and the source / drain S / D can be located in the recessed region.

[0038] In this embodiment, the active region 105 may include a doped region. The doped region may correspond to the well region of a transistor. In a P-type field-effect transistor (PFET), the doped region may include an N-type dopant, such as phosphorus (P), arsenic (As), and / or antimony (Sb). In an N-type field-effect transistor (NFET), the doped region may include a P-type dopant, such as boron (B), gallium (Ga), and / or aluminum (Al). The doped region may be located at a specific depth from the active region 105 and the upper surface of the substrate 100.

[0039] A first source / drain SD1a and a second source / drain SD2a can be disposed on (above) the active region 105. For example, the first source / drain SD1a and the second source / drain SD2a can be disposed in a recessed region formed by partially recessing the upper part of the active region 105. The first source / drain SD1a and the second source / drain SD2a can contact multiple nanosheets of the nanosheet stack NSS, while overlapping (e.g., covering) the side surfaces of the nanosheets. A first interlayer insulating layer ILD1 can be formed on (above) the first source / drain SD1a and the second source / drain SD2a.

[0040] Conductive patterns 110A and 120A can be formed on (above) the first source / drain SD1a, the second source / drain SD2a, and the first interlayer insulating layer ILD1. An insulating wall 130 can be formed between the conductive patterns 110A and 120A. In some embodiments, a barrier pattern can also be formed between the region including the first source / drain SD1a, the second source / drain SD2a, and the first interlayer insulating layer ILD1 and the region including the conductive patterns 110A and 120A. For example, the barrier pattern may include a metal layer / metal nitride layer. The conductive patterns 110A and 120A may include, for example, aluminum, copper, tungsten, molybdenum, and / or cobalt. A first mask pattern HM1 can be formed on (above) the conductive patterns 110A and 120A and the insulating wall 130. The first mask pattern HM1 may include, for example, photoresist, silicon nitride, and / or silicon oxynitride.

[0041] refer to Figure 4B The recessed region can be formed by etching the upper portions of the conductive patterns 110A and 120A exposed through the first mask pattern HM1. Therefore, a first contact protrusion 110b can be formed in the upper portion of the conductive pattern 110A, and the lower portion of the conductive pattern 110A can be defined as a first contact body 110a. In this case, the first contact body 110a and the first contact protrusion 110b can form a first contact 110. Furthermore, a second contact protrusion 120b can be formed in the upper portion of the conductive pattern 120A, and the lower portion of the conductive pattern 120A can be defined as a second contact body 120a. In this case, the second contact body 120a and the second contact protrusion 120b can form a second contact 120. The recessed region can be formed by a dry etching process and / or a wet etching process.

[0042] In related technologies, two pathways are formed by performing an etching process using two mask patterns. In this case, each of the two pathways can be (substantially) symmetrical in a first direction. For example, the two mask patterns can be formed as square-type pillars, so both pathways can be etched into (substantially) symmetrical shapes. However, according to the current embodiment, the first contact protrusion 110b and the second contact protrusion 120b can be formed by performing an etching process using a single mask pattern (i.e., the first mask pattern HM1). For example, the first mask pattern HM1 can be formed as a bar pillar, so each of the first contact protrusion 110b and the second contact protrusion 120b can be etched into an asymmetrical shape.

[0043] refer to Figure 4CThe first mask pattern HM1 can be removed, and then a second interlayer insulating layer ILD2 is formed by forming an interlayer insulating layer that (at least partially) fills the recessed area and performing a planarization process. The upper surface of the second interlayer insulating layer ILD2 can be at the same horizontal level (can be coplanar) with the upper surfaces of the first contact protrusion 110b and the second contact protrusion 120b. The second interlayer insulating layer ILD2 can include, for example, SiO2, SiN, SiC, SiOC and / or AlO. x . refer to Figure 4D A metal layer can be formed on (above) the second interlayer insulating layer ILD2, and then patterned to form a metal layer M1 including, for example, first metal lines M1c and M1d and second metal lines M1e and M1f.

[0044] Figure 5 It is according to some embodiments along Figure 1 An example of a cross-sectional view taken by line X1-X1'. Here, the terms "horizontal height," "vertical horizontal height," "height," etc., can refer to the relative position with respect to the reference element in the vertical direction. Horizontal height, vertical horizontal height, height, etc., can be distances from the lower surface of substrate 100 in the vertical direction. For example, a higher horizontal height can mean a greater distance from the lower surface of substrate 100 in the vertical direction, while a lower horizontal height can mean a closer distance from the lower surface of substrate 100 in the vertical direction.

[0045] refer to Figure 5 Integrated circuit device 10' can correspond to reference Figure 2 A modified example of the described integrated circuit device 10. For example, a first contact 110' may be disposed on (above) a first source / drain SD1a, and a first pass 115 may be disposed on (above) the first contact 110'. The first source / drain SD1a may be (electrically) connected to at least one first metal line (e.g., first metal line M1d) via the first contact 110' and the first pass 115. A second contact 120' may be disposed on (above) a second source / drain SD2a, and a second pass 125 may be disposed on (above) the second contact 120'. The second source / drain SD2a may be (electrically) connected to at least one second metal line (e.g., second metal line M1e) via the second contact 120' and the second pass 125.

[0046] An interface may exist between the first contact 110' and the first passage 115, and an interface may exist between the second contact 120' and the second passage 125. As described above, the inventive concept is not limited to embodiments in which the source / drain is connected to a metal line via a single contact (i.e., via a contact body and a contact protrusion), but includes embodiments in which the source / drain is connected to a metal line via contacts and passages.

[0047] The first pathway 115 and the second pathway 125 can correspond to Figure 1 The path VA is shown, and can be accessed by using the first mask pattern HM1 (reference). Figure 1 The first channel 115 and the second channel 125 are formed by an etching process. Therefore, both the first channel 115 and the second channel 125 can have an asymmetric shape based on the cell boundary CBD. In other words, both the first channel 115 and the second channel 125 can be asymmetric in a first direction. According to the present embodiment, the first channel 115 and the second channel 125 can be formed by an etching process using a single mask pattern (i.e., the first mask pattern HM1). For example, the first mask pattern HM1 can be formed as a bar pillar; therefore, both the first channel 115 and the second channel 125 can be etched into an asymmetric shape.

[0048] Figure 6 This illustrates the layout of an integrated circuit device 10a according to some embodiments. Figure 7 It is according to some embodiments along Figure 6 The cross-sectional view taken by line X3-X3'. Figure 8 It is according to some embodiments along Figure 6 The cross-sectional view taken from line X4-X4'.

[0049] refer to Figures 6 to 8 The integrated circuit device 10a may include a first standard cell 11a and a second standard cell 12a that are adjacent to each other in a first direction. In the current embodiment, each of the first standard cell 11a and the second standard cell 12a may include a GAA transistor, such as a multi-bridge channel field-effect transistor (MBCFET). The integrated circuit device 10a may correspond to Figure 1 The example of a modified integrated circuit device 10 shown is illustrated, and reference is made to... Figures 1 to 5 The provided description can also be applied to the current embodiment.

[0050] For example, the first standard unit 11a may include a pair of nanosheet stacked NSSs extending in the second direction, and the second standard unit 12a may include a pair of nanosheet stacked NSSs extending in the second direction. For example, the nanosheet stacked NSS1a may include a first nanosheet NS1a, a second nanosheet NS2a, and a third nanosheet NS3a overlapping the active region 105 in the vertical direction. However, the inventive concept is not limited thereto, and the number of nanosheets included in the nanosheet stacked NSS1a may vary depending on the embodiment.

[0051] The first contact protrusion 110b and the second contact protrusion 120b can be separated from each other by an insulating layer 140, and both can be asymmetrical in a first direction. For example, the insulating layer 140 can correspond to a contact cut pattern that separates the first contact 110b and the second contact 120b from each other. For example, the first contact protrusion 110b and the second contact protrusion 120b can be asymmetrically etched based on the cell boundary CBD using an etching process using a first mask pattern HM1, so both the first contact protrusion 110b and the second contact protrusion 120b can be asymmetrical in shape. According to the present embodiment, the first contact protrusion 110b and the second contact protrusion 120b can be formed by an etching process using a single mask pattern (i.e., the first mask pattern HM1). For example, the first mask pattern HM1 can be formed as a bar pillar, so both the first contact protrusion 110b and the second contact protrusion 120b can be etched into asymmetrical shapes.

[0052] Figure 9 This illustrates the layout of an integrated circuit device 20 according to some embodiments. Figure 10 It is according to some embodiments along Figure 9 The cross-sectional view taken from line X5-X5'.

[0053] Let's refer to each other. Figure 9 and Figure 10 The integrated circuit device 20 may include a first standard unit 21 and a second standard unit 22 that are adjacent to each other in a first direction. For example, the first standard unit 21 and the second standard unit 22 may respectively correspond to Figure 1 The examples shown are modified versions of the first standard unit 11 and the second standard unit 12, and both can include a forked transistor. For example, the first standard unit 21 and the second standard unit 22 can respectively correspond to... Figure 6 The examples shown are modified versions of the first standard unit 11a and the second standard unit 12a, and both can include GAA transistors, such as MBCFETs. (See reference...) Figures 1 to 8 The provided description can also be applied to the current embodiment.

[0054] The integrated circuit device 20 may include a front wiring layer (such as a first metal layer M1) and a back wiring layer (such as a first back metal layer BM1), and a power distribution network (PDN) can be implemented using the front wiring layer and the back wiring layer. In this case, the first metal layer M1 may be disposed vertically on the upper surface of the substrate 200 (above), and the first back metal layer BM1 may be disposed vertically on the lower surface of the substrate 200 (below). Therefore, signals and / or power applied to the integrated circuit device 20 can be transmitted through the first metal layer M1 (i.e., the front PDN (FSPDN)) and / or through the first back metal layer BM1 (i.e., the back PDN (BSPDN)). Therefore, compared to a structure in which wiring is arranged only on the front side of the substrate, the present embodiment can reduce wiring complexity and can reduce the length of each wire or path, thereby improving the performance of the integrated circuit device 20.

[0055] In this embodiment, the first metal layer M1 can be used for signal wiring, and the first back metal layer BM1 can be used for power wiring. As described above, supplying power through the first back metal layer BM1 can reduce the number of metal lines included in the first metal layer M1, thereby further reducing the area of ​​each standard cell and achieving area reduction.

[0056] The first back-side metal layer BM1 may include a first back-side wiring pattern BM1a extending in a second direction and overlapping (in the vertical direction) with the cell boundary CBD. The first back-side wiring pattern BM1a may be electrically connected to a first source / drain SD1b and a second source / drain SD2b via a back-side contact BCA. The back-side contact BCA may be disposed on (above) the first back-side metal layer BM1 and may extend vertically into (through) the substrate 200. For example, the first source / drain SD1b and the second source / drain SD2b may correspond to source regions that receive power supply voltage or ground voltage through the first back-side wiring pattern BM1a.

[0057] The first standard unit 21 may include contacts 210 and 220, both extending in a first direction, and the second standard unit 22 may include contacts 230 and 240, both extending in the first direction. Contacts 210 and 230 may be aligned with a reference... Figure 1Contacts 110 and 120 are implemented in the same (or similar) manner. That is, contact 210 may include a first contact body and a first contact protrusion located on (above) the first contact body, and contact 230 may include a second contact body and a second contact protrusion located on (above) the second contact body. The first and second contact protrusions can be formed using an etching process using a first mask pattern HM1, and therefore can both be asymmetrical in shape based on the cell boundary CBD. For example, both the first and second contact protrusions can be asymmetrical in a first direction.

[0058] The first standard cell 21 may include a first source / drain SD1b located on (above) the active region 205, and the second standard cell 22 may include a second source / drain SD2b located on (above) the active region 205. A contact 220 may be disposed on (above) the first source / drain SD1b, and a contact 240 may be disposed on (above) the second source / drain SD2b. A first interlayer insulating layer ILD1 may be disposed on (above) the substrate 200 and the first source / drain SD1b and the second source / drain SD2b, and a second interlayer insulating layer ILD2 may be disposed on (above) contacts 220 and 240.

[0059] In one embodiment, the first source / drain SD1b and the second source / drain SD2b can receive power supply voltage or ground voltage from the first back-side wiring pattern BM1a via the back-side contact BCA. Therefore, contacts 220 and 240 may not be electrically connected to the first metal layer M1. However, the inventive concept is not limited thereto, and in some embodiments, contacts 220 and 240 may be electrically connected to the first metal layer M1 and receive power supply voltage or ground voltage from both the first back-side wiring pattern BM1a and the first metal layer M1 to further improve the performance of the integrated circuit device 20.

[0060] Figure 11 This illustrates the layout of an integrated circuit device 30 according to some embodiments.

[0061] refer to Figure 11The integrated circuit device 30 may include a first standard cell 31 and a second standard cell 32 that are adjacent to each other in a first direction. For example, both the first standard cell 31 and the second standard cell 32 may include a GAA transistor, such as a forked transistor or an MBCFET. The first standard cell 31 may include a contact CA extending in the first direction and a first gate electrode 310, and first metal lines M1a, M1b, M1c, and M1d may be disposed on (above) the first standard cell 31. The second standard cell 32 may include a contact CA extending in the first direction and a second gate electrode 320, and second metal lines M1e, M1f, M1g, and M1h may be disposed on (above) the second standard cell 32.

[0062] The first gate electrode 310 and the second gate electrode 320 may be separated from each other in a first direction. The first gate electrode 310 and the second gate electrode 320 may overlap in the first direction. For example, the first gate electrode 310 and the second gate electrode 320 may be arranged in a line. Gate contacts CB may be disposed on (above) the first gate electrode 310 and the second gate electrode 320, respectively. In an embodiment, each of the first gate electrode 310 and the second gate electrode 320 may include: an electrode body extending in the first direction, and an electrode protrusion (in the vertical direction) protruding from the electrode body and corresponding to the gate contact CB. The electrode body and the electrode protrusion may be formed by selectively recessing the gate pattern as described above, thus improving the short-circuit margin between contact plugs adjacent to the electrode protrusion corresponding to the gate contact CB, for example, the short-circuit margin between the gate contact or the source / drain. Reference is made below. Figure 13A , Figure 13B , Figure 13C and Figure 13D Describe relevant embodiments.

[0063] According to the current embodiment, the gate contact CB can be formed by an etching process using a second hard mask or a second mask pattern HM2. For example, the second mask pattern HM2 can be implemented as a strip-shaped rectangle extending in the first direction, but the inventive concept is not limited thereto. The second mask pattern HM2 can be implemented in any shape as long as the length of the shape in the first direction is greater than the length of the shape in the second direction. The second mask pattern HM2 can overlap (in the vertical direction) with the cell boundary CBD, and the gate contact CB adjacent to the cell boundary CBD can be formed by an etching process using the second mask pattern HM2. Therefore, the gate contact CB can be etched asymmetrically based on the cell boundary CBD, and thus, all gate contacts CB can have an asymmetrical shape in the first direction. See below for reference. Figure 12 The asymmetric shape of the gate contact CB is further described.

[0064] Figure 12 It is according to some embodiments along Figure 11 The cross-sectional view taken from line X6-X6'.

[0065] Let's refer to each other. Figure 11 and Figure 12 The integrated circuit device 30 may include a substrate 300 and active regions 305. The active regions 305 may extend in a second direction and may be defined by a device isolation layer (STI). A first standard cell 31 may include a first nanosheet stack NSS10, and a second standard cell 32 may include a second nanosheet stack NSS20. The first nanosheet stack NSS10 and the second nanosheet stack NSS20 may be separated from each other by a partition wall or insulating wall 330. In this way, the integrated circuit device 30 may include a forked transistor.

[0066] The first nanosheet stack NSS10 may include a first nanosheet NS11, a second nanosheet NS12, and a third nanosheet NS13 overlapping the active region 305 in the vertical direction. The second nanosheet stack NSS20 may include a first nanosheet NS21, a second nanosheet NS22, and a third nanosheet NS23 overlapping the active region 305 in the vertical direction. However, the inventive concept is not limited thereto, and the number of nanosheets included in each of the first nanosheet stack NSS10 and the second nanosheet stack NSS20 may vary depending on the embodiment.

[0067] The first gate electrode 310 may include a first electrode body 310a extending in a first direction, and a first electrode protrusion 310b protruding from the upper surface of the first electrode body 310a (in the vertical direction). For example, the first electrode body 310a and the first electrode protrusion 310b may be formed as a single body without an interface therebetween. That is, the first electrode body 310a and the first electrode protrusion 310b may be portions of a single body comprising the same material. The second gate electrode 320 may include a second electrode body 320a extending in a first direction, and a second electrode protrusion 320b protruding from the upper surface of the second electrode body 320a (in the vertical direction). For example, the second electrode body 320a and the second electrode protrusion 320b may be formed as a single body without an interface therebetween. That is, the second electrode body 320a and the second electrode protrusion 320b may be portions of a single body comprising the same material.

[0068] The first electrode body 310a may extend around (e.g., surround) the first nanosheet stack NSS10 and extend in a first direction. The second electrode body 320a may extend around (e.g., surround) the second nanosheet stack NSS20 and extend in the first direction. The first gate electrode 310 and the second gate electrode 320 may, for example, comprise a metal, a metal nitride, a metal carbide, and / or a combination thereof. A gate dielectric layer GI may be disposed between the first nanosheet stack NSS10 and the first electrode body 310a, and the gate dielectric layer GI may be disposed between the second nanosheet stack NSS20 and the second electrode body 320a. Furthermore, the gate dielectric layer GI may also be disposed between the substrate 300 and the first electrode body 310a and the second electrode body 320a. For example, the gate dielectric layer GI may each have a stacked structure of an interface layer and a high-k dielectric layer. An interlayer insulating layer ILD may be disposed on (above) the first gate electrode 310 and the second gate electrode 320.

[0069] The first electrode protrusion 310b and the second electrode protrusion 320b can be separated from each other by the insulating wall 330, and both can be asymmetrical in the first direction. For example, the first electrode protrusion 310b and the second electrode protrusion 320b can be asymmetrically etched based on the cell boundary CBD using an etching process using the second mask pattern HM2. Therefore, both the first electrode protrusion 310a and the second electrode protrusion 310b can be asymmetrical in the first direction.

[0070] For example, the first angle between the left side of the first electrode protrusion 310b (the side farther from the insulating wall 330 in the first direction) and the horizontal plane of the substrate 300 may be smaller than the second angle between the right side of the first electrode protrusion 310b (the side closer to the insulating wall 330 in the first direction) and the horizontal plane of the substrate 300. For example, the first angle may be in the range of (about) 0° to less than (about) 90°, and the second angle may be (about) 90° and / or greater than the first angle. The third angle between the right side of the second electrode protrusion 320b (the side farther from the insulating wall 330 in the first direction) and the horizontal plane of the substrate 300 may be smaller than the fourth angle between the left side of the second electrode protrusion 320b (the side closer to the insulating wall 330 in the first direction) and the horizontal plane of the substrate 300. For example, the third angle may be in the range of (about) 0° to less than (about) 90°, and the fourth angle may be (about) 90° and / or greater than the third angle.

[0071] At least one first metal line (e.g., first metal line M1d) may be disposed on (above) the first electrode protrusion 310b, and the first electrode body 310a may be electrically connected to at least one first metal line (e.g., first metal line M1d) through the first electrode protrusion 310b. For example, the first electrode protrusion 310b may correspond to the gate contact CB. The upper surface of the first electrode protrusion 310b may directly contact the lower surface of at least one first metal line (e.g., first metal line M1d), therefore, the first gate electrode 310 may be directly connected to at least one first metal line (e.g., first metal line M1d) without any additional structure in between. Because the first electrode protrusion 310b and at least one first metal line (e.g., first metal line M1d) are (electrically) connected to each other as described above, the interface resistance between the first electrode protrusion 310b and the adjacent contact plug can be reduced.

[0072] At least one second metal line (e.g., second metal line M1e) may be disposed on (above) the second electrode protrusion 320b, and the second electrode body 320a may be electrically connected to at least one second metal line (e.g., second metal line M1e) through the second electrode protrusion 320b. For example, the second electrode protrusion 320b may correspond to the gate contact CB. The upper surface of the second electrode protrusion 320b may directly contact the lower surface of at least one second metal line (e.g., second metal line M1e), therefore, the second gate electrode 320 may be directly connected to at least one second metal line (e.g., second metal line M1e) without any additional structure in between. Because the second electrode protrusion 320b and at least one second metal line (e.g., second metal line M1e) are (electrically) connected to each other as described above, the interface resistance between the second electrode protrusion 320b and the adjacent contact plug can be reduced.

[0073] In related technologies, an etching process is performed using multiple mask patterns corresponding to the gate contacts CB, thus forming two gate contacts CB facing each other across the cell boundary CBD. However, according to the current embodiment, the first electrode body 310a and the second electrode body 320a can first be separated from each other based on an insulating wall 330 formed for device isolation. The first electrode bump 310b and the second electrode bump 320b can be formed by etching the two gate contacts CB adjacent to the cell boundary CBD in one step using a single mask pattern (i.e., the second mask pattern HM2). When the gate contacts CB face each other across the cell boundary CBD as described above, since the first electrode body 310a and the second electrode body 320a are already separated from each other by the insulating wall 330, node separation between cells can be achieved by forming the first electrode bump 310b and the second electrode bump 320b based on a single mask pattern (i.e., the second mask pattern HM2).

[0074] Therefore, compared to related technologies, the distance between gate contacts CB that face each other across the cell boundary CBD can be reduced, thus eliminating the need for metal lines overlapping with the cell boundary CBD (in the vertical direction). Consequently, the metal spacing of the first metal layer M1 can be increased, thereby reducing the resistance or capacitance of the first metal layer M1. Furthermore, because metal lines overlapping with the cell boundary CBD are not required, the first metal layer M1 of each standard cell can have a 4-track structure. Therefore, the area of ​​each standard cell can be reduced, and the area of ​​the integrated circuit device 30 can also be reduced.

[0075] Figure 13A , Figure 13B , Figure 13C and Figure 13D This illustrates the manufacture according to some embodiments. Figure 11 A cross-sectional view of the method using the integrated circuit device 30 shown. (Refer to...) Figure 4A , Figure 4B , Figure 4C and Figure 4D The provided description can also be applied to the current embodiment.

[0076] refer to Figure 11 and Figure 13A The substrate 300 may have an upper surface extending in a first direction and a second direction. The substrate 300 may be (substantially) aligned with a reference. Figure 2 The substrate 100 described is implemented in a similar or identical manner. A device isolation layer STI may define an active region 305 within the substrate 300. The active region 305 may be defined within the substrate 300 by the device isolation layer STI, and both may extend in the second direction. The active region 305 may be (substantially) similar to the reference... Figure 2 The active region 105 described is implemented in a similar or identical manner.

[0077] A first nanosheet stack NSS10 and a second nanosheet stack NSS20 can be formed on (above) the active region 305, and the first nanosheet stack NSS10 and the second nanosheet stack NSS20 can be separated from each other (in a first direction) by an insulating wall 330. A gate dielectric layer GI can be formed on the upper surface of the active region 305 and the device isolation layer STI, and the gate dielectric layer GI can be formed on the first nanosheet stack NSS10 and the second nanosheet stack NSS20. Gate patterns 310A and 320A can be formed on the gate dielectric layer GI. A second mask pattern HM2 can be formed on (above) the gate patterns 310A and 320A and the insulating wall 330. The second mask pattern HM2 may include, for example, photoresist, silicon nitride and / or silicon oxynitride.

[0078] refer to Figure 13BThe recessed region can be formed by etching the upper portions of the gate patterns 310A and 320A exposed through the second mask pattern HM2. Therefore, a first electrode bump 310b can be formed in the upper portion of the gate pattern 310A, and the lower portion of the gate pattern 310A can be defined as a first electrode body 310a. In this case, the first electrode body 310a and the first electrode bump 310b can form a first gate electrode 310. A second electrode bump 320b can be formed in the upper portion of the gate pattern 320A, and the lower portion of the gate pattern 320A can be defined as a second electrode body 320a. In this case, the second electrode body 320a and the second electrode bump 320b can form a second gate electrode 320. The recessed region can be formed by a dry etching process and / or a wet etching process.

[0079] In related technologies, two gate contacts are formed using an etching process with two mask patterns. In this case, each of the two gate contacts can be (substantially) symmetrical in a first direction. For example, the two mask patterns can be formed as square pillars, resulting in both gate contacts being etched into (substantially) symmetrical shapes. However, according to the present embodiment, the first electrode protrusion 310b and the second electrode protrusion 320b can be formed using an etching process with a single mask pattern (i.e., the second mask pattern HM2). For example, the second mask pattern HM2 can be formed as a strip pillar, resulting in both the first electrode protrusion 310b and the second electrode protrusion 320b being etched into asymmetrical shapes (in the first direction).

[0080] refer to Figure 13C The second mask pattern HM2 can be removed, and then an interlayer insulating layer (ILD) is formed by forming an interlayer insulating layer that (at least partially) fills the recessed region and performing a planarization process. The upper surface of the ILD can be at the same horizontal level (coplanar) as the upper surfaces of the first electrode protrusion 310b and the second electrode protrusion 320b. The ILD can comprise materials such as SiO2, SiN, SiC, SiOC, and / or AlOx. (Reference) Figure 13D A metal layer can be formed on (above) the interlayer insulating layer (ILD) and then patterned to form a first metal layer M1 including first metal lines M1c and M1d and second metal lines M1e and M1f.

[0081] Figure 14 It is according to some embodiments along Figure 11 Example of a cross-sectional view taken from line X6-X6'.

[0082] refer to Figure 14The integrated circuit device 30a may include a GAA transistor, such as an MBCFET. For example, the first standard unit 31 may include a first nanosheet stack NSS10a, and the second standard unit 32 may include a second nanosheet stack NSS20a. For example, the first nanosheet stack NSS10a may include a first nanosheet NS11a, a second nanosheet NS12a, and a third nanosheet NS13a overlapping the active region 305 in the vertical direction. The second nanosheet stack NSS20a may include a first nanosheet NS21a, a second nanosheet NS22a, and a third nanosheet NS23a overlapping the active region 305 in the vertical direction Z. However, the inventive concept is not limited thereto, and the number of nanosheets included in each of the first nanosheet stack NSS10a and the second nanosheet stack NSS20a may vary depending on the embodiment.

[0083] The first electrode protrusion 310b and the second electrode protrusion 320b can be separated from each other by an insulating layer 340, and both can be asymmetrical in the first direction. For example, the insulating layer 340 can correspond to a gate dicing pattern (e.g., a CT pattern) that separates the first gate electrode 310 and the second gate electrode 320 from each other. For example, the first electrode protrusion 310b and the second electrode protrusion 320b can be separated by using a second mask pattern HM2 (see reference). Figure 11 The etching process is based on the asymmetric etching of the cell boundary CBD, therefore, each of the first electrode protrusion 310b and the second electrode protrusion 320b can be asymmetrical in shape (in the first direction). According to the present embodiment, the first electrode protrusion 310b and the second electrode protrusion 320b can be formed by an etching process using a single mask pattern (i.e., the second mask pattern HM2). For example, the second mask pattern HM2 can be formed as a bar pillar, resulting in both the first electrode protrusion 310b and the second electrode protrusion 320b being etched into asymmetrical shapes (in the first direction).

[0084] Figure 15 This illustrates the layout of an integrated circuit device 40 according to some embodiments.

[0085] refer to Figure 15 The integrated circuit device 40 may include a first standard unit 41 and a second standard unit 42 that are adjacent to each other in a first direction. For example, the first standard unit 41 and the second standard unit 42 may correspond to a reference. Figure 11 The description includes modified examples of the first standard unit 31 and the second standard unit 32. Each of the first standard unit 41 and the second standard unit 42 may include a GAA transistor, such as a forked transistor or an MBCFET. Reference Figure 11 , Figure 12 , Figure 13A , Figure 13B , Figure 13C , Figure 13D and Figure 14 The provided description can also be applied to the current embodiment.

[0086] The integrated circuit device 40 may include a front wiring layer (such as a first metal layer M1) and a back wiring layer (such as a first back metal layer BM1), and the PDN may be implemented using the front wiring layer and / or the back wiring layer. Some signals and / or power applied to the integrated circuit device 40 may be transmitted through the first metal layer M1 (i.e., FSPDN) and / or through the first back metal layer BM1 (i.e., BSPDN). Therefore, compared to a structure that provides wiring only on the front side of the substrate, the current embodiment can significantly reduce wiring complexity and the length of each wire or path, thereby improving the performance of the integrated circuit device 40.

[0087] The first back metal layer BM1 may include a first back wiring pattern BM1a extending in the second direction and overlapping (in the vertical direction) with the cell boundary CBD. The first back wiring pattern BM1a may be electrically connected to the source / drain included in the first standard cell 41 and the second standard cell 42 via a back contact BCA. The back contact BCA may be disposed on (above) the first back metal layer BM1 and may extend in the vertical direction into the substrate (extending through the substrate).

[0088] The first standard unit 41 may include a first gate electrode 410 extending in a first direction, and the second standard unit 42 may include a second gate electrode 420 extending in the first direction. The first gate electrode 410 and the second gate electrode 420 may be aligned with a reference. Figure 11 The first gate electrode 310 and the second gate electrode 320 are implemented in a similar (or identical) manner. That is, the first gate electrode 410 may include a first electrode body and a first electrode protrusion located on (above) the first electrode body, and the second gate electrode 420 may include a second electrode body and a second electrode protrusion located on (above) the second electrode body. The first electrode protrusion and the second electrode protrusion can be formed by an etching process using a second mask pattern HM2, and therefore can be asymmetrical in shape based on the cell boundary CBD (in the first direction).

[0089] Figure 16 This illustrates the layout of an integrated circuit device 50 according to some embodiments.

[0090] refer to Figure 16The integrated circuit device 50 may include a first standard cell 51 and a second standard cell 52 adjacent to each other in a first direction. For example, both the first standard cell 51 and the second standard cell 52 may include a GAA transistor, such as a forked transistor or an MBCFET. The integrated circuit device 50 may include a gate electrode GT, a contact CA, a path VA, a gate contact CB, and a first metal layer M1. The first metal layer M1 may include first metal lines M1a, M1b, M1c, and M1d, all extending in a second direction on (above) the first standard cell 51, and second metal lines M1e, M1f, M1g, and M1h, all extending in a second direction on (above) the second standard cell 52. Therefore, each of the first standard cell 51 and the second standard cell 52 may have a 4-track structure.

[0091] Each of the first standard unit 51 and the second standard unit 52 may include a contact CA extending in a first direction. For example, the first standard unit 51 may include a first contact 510, and the second standard unit 52 may include a second contact 520. The first contact 510 and the second contact 520 may be separate from each other in the first direction. For example, each of the first contact 510 and the second contact 520 may be aligned with a reference. Figure 1 The first contact 110 and the second contact 120 are implemented in a similar (or identical) manner.

[0092] The first contact 510 may include a first contact body extending in a first direction and a first contact protrusion protruding from the upper surface of the first contact body. The second contact 520 may include a second contact body extending in the first direction and a second contact protrusion protruding from the upper surface of the second contact body. The first contact protrusion and the second contact protrusion may correspond to the via VA and may be formed using an etching process of a first mask pattern HM1. Therefore, the first contact protrusion and the second contact protrusion may be etched asymmetrically based on the cell boundary CBD and may both be asymmetrical in shape in the first direction.

[0093] The first standard unit 51 may include first gate electrodes 530 and 540 extending in a first direction and spaced apart from each other in a second direction, and the second standard unit 52 may include second gate electrodes 550 and 560 extending in a first direction and spaced apart from each other in a second direction. The first gate electrode 530 and the second gate electrode 550 may be spaced apart from each other in the first direction, and the first gate electrode 540 and the second gate electrode 560 may also be spaced apart from each other in the first direction. For example, the first gate electrode 540 and the second gate electrode 560 may be aligned with a reference... Figure 11 The first gate electrode 310 and the second gate electrode 320 are implemented in a similar (or identical) manner.

[0094] The first gate electrode 540 may include a first electrode body extending in a first direction and a first electrode protrusion protruding from the upper surface of the first electrode body, and the second gate electrode 560 may include a second electrode body extending in the first direction and a second electrode protrusion protruding from the upper surface of the second electrode body. The first electrode protrusion and the second electrode protrusion may correspond to the gate contact CB and may be formed by an etching process using a second mask pattern HM2. Therefore, the first electrode protrusion and the second electrode protrusion may be etched asymmetrically based on the cell boundary CBD, and both may be asymmetrical in shape in the first direction. In an embodiment, the upper surfaces of the first contact protrusion and the second contact protrusion may be at the same horizontal height (may be coplanar) with the upper surfaces of the first electrode protrusion and the second electrode protrusion.

[0095] Figure 17 This illustrates the layout of an integrated circuit device 60 according to some embodiments.

[0096] refer to Figure 17 The integrated circuit device 60 may include a first standard cell 61 and a second standard cell 62 adjacent to each other in a first direction. For example, each of the first standard cell 61 and the second standard cell 62 may include a GAA transistor, such as a forked transistor or an MBCFET. The integrated circuit device 60 may include a gate electrode GT, a contact CA, a path VA, a gate contact CB, a first metal layer M1, a back contact BCA, and a first back wiring layer BM1. The first metal layer M1 may include: first metal lines M1a, M1b, M1c, and M1d, all extending in a second direction on (above) the first standard cell 61, and second metal lines M1e, M1f, M1g, and M1h, all extending in a second direction on (above) the second standard cell 62. Therefore, each of the first standard cell 61 and the second standard cell 62 may have a 4-track structure.

[0097] The first standard unit 61 may include first contacts 610 and 620, and the second standard unit 62 may include second contacts 630 and 640. For example, the first contact 610 and the second contact 630 may be separated from each other in a first direction. For example, the first contact 610 and the second contact 630 may be aligned with a reference. Figure 1 The first contact 110 and the second contact 120 described are implemented in a similar (or identical) manner. For example, the first contact 620 and the second contact 640 can be implemented in the same manner as the referenced Figure 9 The described contacts 220 and 240 are implemented in a similar (or identical) manner.

[0098] For example, the first contact 610 may include a first contact body extending in the first direction and a first contact protrusion protruding from the upper surface of the first contact body, and the second contact 630 may include a second contact body extending in the first direction and a second contact protrusion protruding from the upper surface of the second contact body. The first contact protrusion and the second contact protrusion may correspond to the via VA and may be formed using an etching process of the first mask pattern HM1. Therefore, the first contact protrusion and the second contact protrusion may be etched asymmetrically based on the cell boundary CBD, and both may have an asymmetrical shape in the first direction.

[0099] In an embodiment, the first standard unit 61 may include (e.g., reference) located below the first contact 620. Figure 10 The first source / drain shown is SD1b), and the second standard cell 62 may include a second source / drain located below the second contact 640 (e.g., reference). Figure 10 The second source / drain (SD2b) is shown. The first source / drain and the second source / drain can receive power supply voltage or ground voltage from the first back-side wiring pattern BM1a through the back-side contact BCA. Therefore, the first contact 620 and the second contact 640 may not be electrically connected to the first metal layer M1. However, the inventive concept is not limited thereto, and in some embodiments, the first contact 620 and the second contact 640 may be electrically connected to the first metal layer M1 and may simultaneously receive power supply voltage and / or ground voltage from both the first back-side wiring pattern BM1a and the first metal layer M1, thereby further improving the performance of the integrated circuit device 60.

[0100] In an embodiment, the first standard unit 61 may include a third source / drain located below the first contact 610, and the second standard unit 62 may include a fourth source / drain located below the second contact 630. The third and fourth source / drains can receive power supply voltage or ground voltage from the first back-side wiring pattern BM1a via the back-side contact BCA. As described above, because the first contact 610 and the second contact 630 can simultaneously receive power supply voltage and / or ground voltage from both the first back-side wiring pattern BM1a and the first metal layer M1, the performance of the integrated circuit device 60 can be further improved.

[0101] The first standard unit 61 may include first gate electrodes 650 and 660 extending in a first direction and spaced apart from each other in a second direction, and the second standard unit 62 may include second gate electrodes 670 and 680 extending in a first direction and spaced apart from each other in a second direction. The first gate electrode 650 and the second gate electrode 670 may be spaced apart from each other in the first direction, and the first gate electrode 660 and the second gate electrode 680 may also be spaced apart from each other in the first direction. For example, the first gate electrode 660 and the second gate electrode 680 may be aligned with a reference... Figure 11 The first gate electrode 310 and the second gate electrode 320 are implemented in a similar (or identical) manner.

[0102] The first gate electrode 660 may include a first electrode body extending in a first direction and a first electrode protrusion protruding from the upper surface of the first electrode body, and the second gate electrode 680 may include a second electrode body extending in the first direction and a second electrode protrusion protruding from the upper surface of the second electrode body. The first electrode protrusion and the second electrode protrusion may correspond to the gate contact CB and may be formed using an etching process of a second mask pattern HM2. Therefore, the first electrode protrusion and the second electrode protrusion may be etched asymmetrically based on the cell boundary CBD, and both may be asymmetrical in shape in the first direction. In an embodiment, the upper surfaces of the first contact protrusion and the second contact protrusion may be at the same horizontal height as the upper surfaces of the first electrode protrusion and the second electrode protrusion (may be coplanar).

[0103] Figure 18 This is a flowchart illustrating a method for manufacturing an integrated circuit device according to some embodiments.

[0104] refer to Figure 18 The method of the current embodiment is used to manufacture an integrated circuit IC including standard cells, and may include multiple operations S10, S30, S50, S70, and S90. The cell library (or standard cell library) D12 may include information about the standard cells, such as information about the function, characteristics, and layout of the standard cells. In embodiments, the cell library D12 may define functional cells that generate output signals from input signals, and may also define tap cells, fill cells, and dummy cells. Design rules D14 may include requirements that the layout of the integrated circuit IC can comply with. For example, design rules D14 may include requirements for the spacing between patterns in the same layer, minimum pattern width, and routing direction of wiring layers.

[0105] In operation S10, a logic synthesis operation can be performed to generate netlist data D13 from register-transfer-level (RTL) data D11. For example, a semiconductor design tool (e.g., a logic synthesis tool) can perform logic synthesis based on RTL data D11 written in a hardware description language (HDL) (such as VHSIC Hardware Description Language (VHDL) or Verilog) using a reference cell library D12, and can generate netlist data D13 including bit streams or netlists. Netlist data D13 can correspond to the layout and routing inputs described below.

[0106] In operation S30, standard cells can be arranged. For example, a semiconductor design tool (e.g., a placement and routing (P&R) tool) can arrange the standard cells used in netlist data D13 by referring to cell library D12. In operation S50, the pins of the standard cells can be routed. For example, the semiconductor design tool can generate interconnects that electrically connect the output pins and input pins of the arranged standard cells, and can generate placement data D15 that defines the arranged standard cells and the generated interconnects. The interconnects may include vias of a via layer and / or patterns of a routing layer. The routing layer may include a front routing layer disposed above the front side of the substrate and a back routing layer disposed on the back side of the substrate. The placement data D15 may be in a format such as Graphical Design System II (GDSII) and may include geometric information about the standard cells and interconnects. The semiconductor design tool can refer to design rule D14 when routing the pins of the standard cells. The placement data D15 may correspond to the output of placement and routing. Operation S50 alone, or a combination of operations S30 and S50, may be referred to as a method for designing integrated circuits.

[0107] like Figures 1 to 3 , Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figures 5 to 12 , Figure 13A , Figure 13B , Figure 13C , Figure 13D and Figures 14 to 17 As shown, an integrated circuit device may include multiple standard cells, and multiple metal lines or wiring lines may be disposed above the standard cells. Each standard cell may include a contact plug that contacts the lower surface of the metal line. For example, the contact plug may include a passage located above the source / drain contact (e.g., reference...). Figure 1 The illustrated path VA), or may include source / drain contacts. For example, the contact plug may include a gate contact located above the gate electrode (e.g., reference VA). Figure 11The gate contact CB is shown. According to an embodiment, the contact plug may be referred to as a pick-up structure or a wire pick-up structure.

[0108] In some embodiments, the first standard cell and the second standard cell may be adjacent to each other in a first direction, wherein the first standard cell includes a first contact plug adjacent to a cell boundary, and the second standard cell includes a second contact plug adjacent to a cell boundary. In this case, the first contact plug and the second contact plug may be formed by an etching process using a single strip mask pattern overlapping the first contact plug and the second contact plug. For example, the source / drain contacts included in the first standard cell and the second standard cell may be separated from each other and have an asymmetrical shape due to insulating walls or insulating layers overlapping with the cell boundaries. For example, the gate electrodes included in the first standard cell and the second standard cell may be separated from each other and have an asymmetrical shape due to insulating walls or insulating layers overlapping with the cell boundaries.

[0109] In operation S70, a mask can be fabricated. For example, optical proximity correction (OPC) can be applied to layout data D15 to correct distortions caused by optical properties such as refraction in photolithography. Based on layer data D15 with OPC applied, patterns can be defined on the mask to form patterns on multiple layers. At least one mask (or photomask) can be fabricated for forming patterns on multiple layers.

[0110] In operation S90, an integrated circuit (IC) can be manufactured. For example, an IC can be manufactured by patterning multiple layers using at least one mask manufactured in operation S70. Front-end processes (FEOL) may include operations such as planarizing and cleaning the wafer, forming trenches, forming wells, forming gate electrodes, and forming source and drain regions. Through FEOL, individual devices such as transistors, capacitors, and resistors can be formed on the substrate. Furthermore, back-end processes (BEOL) may include operations such as siliconizing the gate, source, and drain regions, adding dielectrics, planarizing, forming vias, adding metal layers, forming vias, and forming passivation layers. Through BEOL, individual devices such as transistors, capacitors, and resistors can be interconnected. In some embodiments, a middle-end process (MOL) may be performed between FEOL and BEOL, and contacts may be formed over individual devices. Subsequently, the IC can be packaged in a semiconductor package and used as a component in various applications.

[0111] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the scope of the appended claims.

Claims

1. An integrated circuit device, the integrated circuit device comprising: The first standard unit includes a first nanosheet stack, a first source / drain electrically connected to the first nanosheet stack, and a first contact located on the first source / drain. The second standard unit includes a second nanosheet stack, a second source / drain electrically connected to the second nanosheet stack, and a second contact located on the second source / drain, wherein the second standard unit is adjacent to the first standard unit in a first direction; and An insulating layer extending in a vertical direction and overlapping with a cell boundary in that vertical direction, the cell boundary being located between the first standard cell and the second standard cell in the first direction. Wherein, the vertical direction intersects with the first direction. The first contact includes: a first contact body extending in the first direction, and a first contact protrusion protruding from the upper surface of the first contact body in the vertical direction. The second contact includes: a second contact body extending in the first direction, and a second contact protrusion protruding from the upper surface of the second contact body in the vertical direction. The first contact protrusion and the second contact protrusion are spaced apart from each other in the first direction by the insulating layer located therebetween, and each of the first contact protrusion and the second contact protrusion is asymmetrical in the first direction.

2. The integrated circuit device according to claim 1, wherein, The first contact is a single entity, and there is no interface between the first contact body and the first contact protrusion.

3. The integrated circuit device according to claim 1, wherein, The first standard cell also includes a first gate electrode extending around the first nanosheet stack. The second standard unit further includes a second gate electrode extending around the stack of the second nanosheets. The first gate electrode includes: a first electrode body extending in the first direction, and a first electrode protrusion protruding from the upper surface of the first electrode body in the vertical direction. The second gate electrode includes: a second electrode body extending in the first direction, and a second electrode protrusion protruding from the upper surface of the second electrode body in the vertical direction. The first electrode protrusion and the second electrode protrusion are spaced apart from each other in the first direction by the insulating layer located therebetween, and each of the first electrode protrusion and the second electrode protrusion is asymmetrical in the first direction.

4. The integrated circuit device according to claim 3, wherein, The first gate electrode is a single body, and there is no interface between the first electrode body and the first electrode protrusion.

5. The integrated circuit device according to claim 3, wherein, The upper surfaces of the first contact protrusion, the second contact protrusion, the first electrode protrusion, and the second electrode protrusion are coplanar with each other.

6. The integrated circuit device according to claim 1, further comprising a first metal layer located above the first standard cell and the second standard cell. in, The first metal layer includes: First metal lines, each of which extends above the first standard unit along a second direction intersecting the first direction and the vertical direction; and The second metal wires, all of which extend above the second standard unit along the second direction, and The first number of the first metal wires is equal to the second number of the second metal wires.

7. The integrated circuit device according to claim 6, wherein, Each of the first quantity and the second quantity is four.

8. The integrated circuit device according to claim 6, wherein, The first metal wire and the second metal wire do not overlap with the unit boundary in the vertical direction.

9. An integrated circuit device, the integrated circuit device comprising: The first standard unit includes a first nanosheet stack, a first source / drain electrically connected to the first nanosheet stack, and a first gate electrode extending around the first nanosheet stack. The second standard unit includes a second nanosheet stack, a second source / drain electrically connected to the second nanosheet stack, and a second gate electrode extending around the second nanosheet stack, wherein the second standard unit is adjacent to the first standard unit in a first direction; and An insulating layer extending in a vertical direction and overlapping with a cell boundary in that vertical direction, the cell boundary being located between the first standard cell and the second standard cell in the first direction. Wherein, the vertical direction intersects with the first direction. The first gate electrode includes: a first electrode body extending in the first direction, and a first electrode protrusion protruding from the upper surface of the first electrode body in the vertical direction. The second gate electrode includes: a second electrode body extending in the first direction, and a second electrode protrusion protruding from the upper surface of the second electrode body in the vertical direction. The first electrode protrusion and the second electrode protrusion are spaced apart from each other in the first direction by the insulating layer located therebetween, and each of the first electrode protrusion and the second electrode protrusion is asymmetrical in the first direction.

10. The integrated circuit device according to claim 9, wherein, The first gate electrode is a single body, and there is no interface between the first electrode body and the first electrode protrusion.

11. The integrated circuit device according to claim 9, wherein, The first standard cell also includes a first contact located on the first source / drain. The second standard cell further includes a second contact located on the second source / drain. The first contact includes: a first contact body extending in the first direction, and a first contact protrusion protruding from the upper surface of the first contact body in the vertical direction. The second contact includes: a second contact body extending in the first direction, and a second contact protrusion protruding from the upper surface of the second contact body in the vertical direction. The first contact protrusion and the second contact protrusion are spaced apart from each other in the first direction by the insulating layer located therebetween, and each of the first contact protrusion and the second contact protrusion is asymmetrical in the first direction.

12. The integrated circuit device according to claim 11, wherein, The first contact is a single entity, and there is no interface between the first contact body and the first contact protrusion.

13. The integrated circuit device according to claim 11, wherein, The upper surfaces of the first contact protrusion, the second contact protrusion, the first electrode protrusion, and the second electrode protrusion are coplanar with each other.

14. The integrated circuit device of claim 9, further comprising a first metal layer located above the first standard cell and the second standard cell. in, The first metal layer includes: First metal lines, each of which extends above the first standard unit along a second direction intersecting the first direction and the vertical direction; and The second metal wires, all of which extend above the second standard unit along the second direction, and The first number of the first metal wires is equal to the second number of the second metal wires.

15. The integrated circuit device according to claim 14, wherein, Each of the first quantity and the second quantity is four.

16. The integrated circuit device according to claim 14, wherein, The first metal wire and the second metal wire do not overlap with the unit boundary in the vertical direction.

17. An integrated circuit device, the integrated circuit device comprising: A first nanosheet stack and a second nanosheet stack are located on an active region of a substrate, wherein the first nanosheet stack and the second nanosheet stack are spaced apart from each other in a first direction parallel to the upper surface of the substrate. First source / drain and second source / drain, the first source / drain and the second source / drain are electrically connected to the first nanosheet stack and the second nanosheet stack, respectively; A first gate electrode and a second gate electrode, the first gate electrode and the second gate electrode extending in the first direction, wherein the first gate electrode and the second gate electrode extend around the first nanosheet stack and the second nanosheet stack, respectively; A first metal layer is located above the first gate electrode and the second gate electrode; A first contact, located on the first source / drain electrode, wherein the first contact includes a first contact body extending in the first direction and a first contact protrusion protruding from the upper surface of the first contact body in a direction perpendicular to the upper surface of the substrate; and The second contact, located on the second source / drain, includes a second contact body extending in the first direction and a second contact protrusion protruding from the upper surface of the second contact body in the vertical direction. The first contact protrusion and the second contact protrusion are spaced apart from each other in the first direction, and each of the first contact protrusion and the second contact protrusion is asymmetrical in the first direction.

18. The integrated circuit device according to claim 17, wherein, The first gate electrode includes: a first electrode body extending in the first direction, and a first electrode protrusion protruding from the upper surface of the first electrode body in the vertical direction. The second gate electrode includes: a second electrode body extending in the first direction, and a second electrode protrusion protruding from the upper surface of the second electrode body in the vertical direction. The first electrode protrusion and the second electrode protrusion are spaced apart from each other in the first direction, and each of the first electrode protrusion and the second electrode protrusion is asymmetrical in the first direction.

19. The integrated circuit device according to claim 17, further comprising: The third source / drain and the fourth source / drain are electrically connected to the first nanosheet stack and the second nanosheet stack, respectively; A back-side wiring layer, wherein the back-side wiring layer is located on the lower surface of the substrate; as well as A back contact is located on the back wiring layer, wherein the back contact extends into the substrate in the vertical direction. The third source / drain and the fourth source / drain are electrically connected to the back wiring layer via the back contact.

20. The integrated circuit device of claim 17, further comprising: A back-side wiring layer, wherein the back-side wiring layer is located on the lower surface of the substrate; as well as Back contact, the back contact being located on the back wiring layer. The back contact extends into the substrate in the vertical direction. The first source / drain and the second source / drain are electrically connected to the back wiring layer via the back contact.

Images