Metal interconnect layer and method of making the same
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2026-03-25
- Publication Date
- 2026-07-21
AI Technical Summary
Existing technologies for fabricating metal interconnect layers involve complex, costly, and difficult-to-control processes for air gap structures, which cannot meet the demands for improved semiconductor device performance.
By forming protrusions on the sidewalls of metal wires and using their shielding effect to selectively surface treat specific areas within the grooves, the density of dangling bonds is increased, enabling self-aligned growth and highly controllable manufacturing of air gap structures, eliminating the need for specialized photolithography and etching steps.
The fabrication process of the air gap structure is simplified, the dielectric constant of the interconnect layer is reduced, the RC delay is reduced, the chip performance is improved, and the manufacturing cost is reduced.
Smart Images
Figure CN121908875B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a metal interconnect layer and a method for fabricating the same. Background Technology
[0002] As semiconductor devices rapidly advance towards miniaturization and chip integration continues to increase, the parasitic capacitance between internal metal interconnect structures increases accordingly. This leads to increasingly prominent resistance-capacitance (RC) delay issues, severely restricting further improvements in semiconductor device performance.
[0003] Therefore, in the fabrication process of the metal interconnect layer in the back-end process, the RC delay of the interconnect is usually reduced by using dielectric materials with lower dielectric constants, introducing copper interconnect technology, and air gaps. However, the process of introducing air (K~1) into the interconnect structure in related technologies is complex and costly, and the position and size of the air gap structure cannot be controlled, which can easily lead to structural damage and can no longer meet the ever-evolving fabrication needs. Summary of the Invention
[0004] Therefore, it is necessary to provide a metal interconnect layer and its preparation method to address the technical problems in the prior art, which can at least simplify the process flow of the air gap structure in the metal interconnect layer.
[0005] In a first aspect, this application provides a method for fabricating a metal interconnect layer, comprising:
[0006] Provide a substrate;
[0007] A dielectric stack and an initial metal wire are alternately arranged on a substrate along a first direction parallel to a first surface of the substrate; the sidewall of the initial metal wire includes a protrusion, which is embedded in the dielectric stack along the first direction.
[0008] After forming a groove between adjacent initial metal conductors by stacking etching media, a pad oxide layer is formed covering the inner surface of the groove and the top surface of the initial metal conductor; the bottom surface of the groove is lower than the bottom surface of the protrusion.
[0009] The exposed surface of the liner oxide layer is subjected to a surface treatment process, which at least increases the target suspension key for increasing the coating rate on the inner surface of the groove of the protrusion.
[0010] After forming an oxide layer in the groove, the remaining film layer with the top surface higher than the top surface of the protrusion is removed to obtain the target metal wire; the oxide layer has an air gap structure.
[0011] In some embodiments, the width of the air gap structure within the oxide layer is related to the spacing between adjacent protrusions;
[0012] The height ratio of the air gap structure within the oxide layer is related to the height difference between the protrusion and the remaining dielectric stack.
[0013] In the above embodiments, through process design, the sidewall of the initial metal wire naturally forms a protrusion. With the shielding effect of the protrusion, a specific area (with a height not lower than the protrusion) in the groove can be surface treated to increase the number of dangling bonds in the area. This makes the growth rate of the subsequently deposited oxide in this area significantly faster than that in the lower and bottom areas of the groove with weak or no surface treatment, thereby naturally forming an air gap structure under the protrusion.
[0014] Meanwhile, by adjusting the formation position of the protrusions and controlling the sealing rate during the oxide filling process, the volume ratio of the air gap structure can be effectively controlled. Compared with related technologies, the preparation method provided in this application can achieve self-alignment, self-growth, and highly controllable manufacturing of the air gap structure without the need for photolithography and etching steps specifically used to define the air gap position. This effectively solves the core problems of complex traditional air gap processes, high manufacturing costs, and poor structural controllability.
[0015] In some embodiments, the dielectric stack includes a diffusion barrier layer, a dielectric layer, a sacrificial dielectric layer, and a sacrificial stack stacked sequentially along the direction away from the substrate.
[0016] The materials of the dielectric layer and sacrificial stack include dielectric materials with a dielectric constant less than 2.4;
[0017] The oxide layer material includes porous carbon-doped silicon oxide, non-porous carbon-doped silicon oxide, or silicon oxide;
[0018] The material of the sacrificial dielectric layer is configured to have an etching rate greater than that of the other layers in the dielectric stack.
[0019] In some embodiments, forming the protrusion includes:
[0020] A dielectric stack is formed on the substrate;
[0021] The dielectric stack is etched to form trenches spaced apart along a first direction; wherein the etching rate of the sacrificial dielectric layer is greater than the etching rate of the other film layers, so that the width of the sacrificial dielectric layer is smaller than that of the diffusion barrier layer, the dielectric layer, and the sacrificial stack, forming an inward shrinkage;
[0022] The initial metal wires that fill the grooves are formed, and the initial metal wires located at the inwards form the protrusions.
[0023] In some embodiments, the surface treatment process includes:
[0024] A plasma treatment process is performed on the exposed surface of the liner oxide layer to add -H or -OH dangling bonds to the inner surface of the groove at least below the protrusion and the top surface of the metal wire.
[0025] In some embodiments, a plasma processing process is performed using a mixture of inert gas and oxygen-containing gas, hydrogen-containing gas, or ammonia-containing gas.
[0026] In some embodiments, the surface treatment process includes:
[0027] An ion implantation process is performed on the exposed surface of the liner oxide layer to add -H or -OH dangling bonds to the inner surface of the groove at least below the protrusion and the top surface of the metal wire.
[0028] In some embodiments, the surface treatment process includes:
[0029] The exposed surface of the liner oxide layer is subjected to alkaline wet cleaning, which adds -H or -OH dangling bonds to the inner surface of the groove at least below the protrusion and the top surface of the metal wire.
[0030] In some embodiments, the target metal wire, oxide layer and remaining dielectric stack constitute an interconnect structure;
[0031] After forming the interconnect structure, the process further includes repeating the steps of forming target metal wires on the substrate and forming an oxide layer to form a multilayer interconnect structure, constituting a metal interconnect layer.
[0032] In some embodiments, the target metal wire, oxide layer and remaining dielectric stack constitute an interconnect structure;
[0033] After forming the interconnect structure, the process further includes repeating the steps of forming target metal wires on the substrate and forming an oxide layer to form a multilayer metal interconnect layer.
[0034] The self-aligned air gap structure design employed in this metal interconnect layer helps reduce the interconnect dielectric constant, thereby reducing RC delay and improving chip performance. Furthermore, by adjusting the formation position of the protrusions, the shape and position of the air gap can be controlled to a certain extent, providing greater design flexibility for interconnect performance optimization.
[0035] Secondly, this application also provides a metal interconnect layer, including a metal interconnect layer prepared by the preparation method described in any of the above embodiments.
[0036] The metal interconnect layer and its fabrication method provided in this application have the following unexpected technical effects:
[0037] By designing the process to create protrusions on the sidewalls of the metal wires, and using their shielding effect to selectively surface treat specific areas within the grooves to increase the density of the dangling bonds, an air gap structure with relatively controllable position and size is naturally formed under the protrusions without the need for complex additional patterning steps.
[0038] This approach helps reduce the overall dielectric constant of interconnect layers and decrease RC delay, while simplifying the process flow and reducing manufacturing costs, providing a new solution to alleviate RC delay problems in advanced processes. Attached Figure Description
[0039] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0040] Figure 1 This is a flowchart of a method for fabricating a metal interconnect layer provided in one embodiment of this application;
[0041] Figure 2 This is a schematic diagram of the structure obtained after forming the dielectric stack in step S1042 of the preparation method provided in one embodiment of this application;
[0042] Figure 3 This is a schematic diagram of the structure obtained after forming the trench in step S1044 of the preparation method provided in one embodiment of this application;
[0043] Figure 4 This is a schematic diagram of the structure obtained after forming the initial metal wire in step S1046 of the preparation method provided in one embodiment of this application;
[0044] Figure 5 This is a schematic diagram of the structure obtained after forming the groove in step S106 of the preparation method provided in one embodiment of this application;
[0045] Figure 6 for Figure 5 A schematic diagram of the structure obtained after the pad oxide layer is formed in the structure shown;
[0046] Figure 7 This is a schematic diagram of the structure obtained after performing a surface treatment process in step S108 of the preparation method provided in one embodiment of this application;
[0047] Figure 8 This is a schematic diagram of the structure obtained after forming the air gap structure in step S110 of the preparation method provided in one embodiment of this application;
[0048] Figure 9 for Figure 8 A schematic diagram of the structure obtained after the target metal wire is formed in the structure shown;
[0049] Figure 10 This is a magnified view of the local morphology of the structure prepared using the preparation method provided in this application.
[0050] Explanation of reference numerals in the attached figures:
[0051] 1. Substrate; 2. Metal layer; 10. Substrate; 20. Dielectric stack; 21. Diffusion barrier layer; 22. Dielectric layer; 23. Sacrificial dielectric layer; 24. Sacrificial stack; 241. Dielectric material layer; 242. Oxide material layer; 243. Titanium nitride layer; 301. Trench; 30. Initial metal conductor; 31. Protrusion; 32. Target metal conductor; 401. Groove; 41. Pad oxide layer; 42. Oxide layer; 43. Air gap structure. Detailed Implementation
[0052] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0054] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0055] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0056] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0057] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of this application, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of this application.
[0058] As mentioned in the background section, in metal interconnect structures, due to the continuous shrinkage of dimensions, the parasitic capacitance of the dielectric layer formed by low dielectric constant materials is increasing, affecting semiconductor performance. Conventional copper / air gap integration schemes using sacrificial dielectrics require the introduction of air into the interconnect structure through photolithography and etching. Although compatible with existing copper interconnect processes, the additional photolithography and etching processes increase the use of consumables such as photoresist and etching gases, while also extending the overall process cycle, thus increasing manufacturing costs to some extent and impacting process yield and production efficiency.
[0059] Example 1
[0060] Based on this, please refer to the following: Figure 1 This application provides an exemplary method for fabricating a metal interconnect layer, including steps S102-S110. It should be noted beforehand that each step in the following process may integrate conventional semiconductor manufacturing processes such as photolithography, thin film deposition, etching, and cleaning. Describing all of these processes would be extremely cumbersome, and those skilled in the art can readily understand how to implement them without any creative effort. Therefore, conventional processes will not be described in detail here.
[0061] Step S102: Provide a substrate;
[0062] Step S104: A dielectric stack and an initial metal wire are alternately arranged on the substrate along a first direction parallel to the first surface of the substrate; the sidewall of the initial metal wire includes a protrusion, which is embedded in the dielectric stack along the first direction.
[0063] Step S106: Etching the dielectric stack, after forming a groove between adjacent initial metal conductors, forming a pad oxide layer covering the inner surface of the groove and the top surface of the initial metal conductor; the bottom surface of the groove is lower than the bottom surface of the protrusion.
[0064] Step S108: Perform a surface treatment process on the exposed surface of the pad oxide layer, such that at least a target suspension key is added to the inner surface of the groove of the protrusion to increase the coating rate.
[0065] Step S110: After forming an oxide layer in the groove, remove the remaining film layer whose top surface is higher than the top surface of the protrusion to obtain the target metal wire; the oxide layer has an air gap structure.
[0066] For ease of understanding, the substrate in this application embodiment may include a first surface located on the front side and a back surface, i.e., a second surface, opposite to the front side. Ignoring the flatness of the first and second surfaces, a first direction parallel to the first surface is defined, and the direction toward the substrate includes a second direction perpendicular to the first surface of the substrate. The first and second directions are perpendicular to each other. In this application embodiment, the first direction is defined as the Y-axis direction, and the second direction is defined as the Z-axis direction.
[0067] The following is in conjunction with the appendix Figure 2 -Appendix Figure 9 The steps of the metal interconnect layer fabrication method provided in this embodiment will be described in detail. It should be noted that the films shown in the figures as rectangles or other shapes are for illustrative purposes only and are not drawn to the actual scale of the device; they are merely illustrative examples.
[0068] In the extended step of S102, the substrate 10 includes a base 1 and a metal layer 2 located on the base 1. The material of the base 1 can be any suitable base material known in the art, and one or more active / passive semiconductor devices such as transistors, diodes, resistors, capacitors, sensors, memory cells, and logic operation units can be formed within the base 1, without being specifically limited herein. The material of the metal layer 2 is copper.
[0069] In some embodiments, step S104 further includes:
[0070] Please see Figure 2 Step S1042: A diffusion barrier layer 21, a dielectric layer 22, a sacrificial dielectric layer 23, and a sacrificial stack 24 are sequentially formed on the metal layer 2. The diffusion barrier layer 21 includes, but is not limited to, silicon carbide nitride; the dielectric layer 22 includes a dielectric material with a low dielectric constant (2.2 < ε < 3); the material of the sacrificial dielectric layer 23 is configured such that its etching rate is greater than that of other films in the dielectric stack 20. In this embodiment, the sacrificial dielectric layer 23 is a carbon-doped oxide layer with a carbon content lower than that of the other films in the dielectric stack 20; the sacrificial stack 24 includes a dielectric material layer 241 with a low dielectric constant (Low k), an oxide material layer 242, and a titanium nitride layer 243 (TiN) arranged along the ZO direction. The methods for forming the dielectric stack 20 include, but are not limited to, one or more of chemical vapor deposition (CVD), atomic layer deposition (ALD), evaporation, and reactive sputtering processes.
[0071] Please see Figure 3 Step S1044: Part of the dielectric stack 20 is removed by photolithography and dry etching. In this embodiment, because the carbon content of the sacrificial dielectric layer 23 is relatively small, the etching rate is greater than that of the other film layers, causing the sidewalls of the remaining dielectric stack 20 to show an inward shrinkage phenomenon. In addition to the recess of the sacrificial dielectric layer 23, the top of the trench 301 has more sufficient contact with the etching gas during the etching process, the reaction efficiency is higher, and the etching amount is relatively larger, making the lower width of the trench 301 generally smaller than the upper width.
[0072] Please see Figure 4 Step S1046: Fill the trench with metal material, and after completing the trench filling, perform chemical mechanical polishing (CMP) to the stop layer (such as TiN). The metal originally filled in the recessed area of the sacrificial dielectric layer 23 is retained, thereby forming the desired protrusion 31 on the sidewall of the initial metal wire 30.
[0073] Specifically, the location of the protrusion 31 can be flexibly set by adjusting the physical thickness of the sacrificial dielectric layer 23 and its position in the dielectric stack 20, and can be determined according to the dielectric and structural requirements of the device.
[0074] In the extended step of step S106, the sacrificial stack, sacrificial dielectric layer, and part of the dielectric layer 22 are etched away to obtain a groove 401 located between adjacent initial metal wires 30, resulting in a structure as shown. Figure 5 As shown; subsequently, utilizing the conformability of ALD, a low-temperature ALD process is used to form a uniform, dense, and conformally conformal pad oxide layer 41 on the inner surface of the groove 401 and the exposed top surface of the initial metal wire 30, as shown in the specific structure. Figure 6 This process can be performed at lower temperatures (e.g., below 400°C), which helps avoid thermal damage or metal diffusion to thermally sensitive metal conductors (such as copper) and surrounding low-k dielectric materials formed in previous processes.
[0075] Please see Figure 7 In the extension step of step S108, a plasma treatment process is performed on the exposed surface of the liner oxide layer 41. Because the protrusions obstruct the view, it is difficult to reach the deep part of the groove. Therefore, -H or -OH dangling bonds are added at and above the protrusions of the initial metal wire. For example, the plasma treatment process is performed using a mixture of an inert gas and any one of an oxygen-containing (O2 / O3) gas, a hydrogen-containing (H2) gas, or an ammonia-containing (NH3) gas. Specifically, in this embodiment, NH3 plasma treatment is used, with a power of 70W-400W, a treatment temperature range of 300℃-400℃, a pressure of 4 Torr-10 Torr, an NH3 gas flow rate of 300 sccm-2000 sccm, and a nitrogen (N2) gas flow rate of 1000 sccm-15000 sccm.
[0076] In the extended step of S110, an oxide layer 42 is filled into the groove using any one of sub-atmospheric pressure chemical vapor deposition (SACVD), high-density plasma chemical vapor deposition (HDPCVD), or plasma-enhanced chemical vapor deposition (PECVD). Under the combined action of the protrusion 31 and the dangling bonds, the oxide preferentially grows rapidly and densely on the upper sidewalls of the groove with dangling bonds, gradually converging towards the center; while in the lower part and bottom of the groove where the treatment is weaker or untreated, the oxide growth rate is slower. Within the groove, the opening at the protrusion 31 closes first, causing the oxide layer 42 in the lower space to enclose and form an air gap structure 43, the specific structure of which is as follows... Figure 8 As shown; CMP is performed again to remove all excess film layers (oxide layer 42, pad oxide layer 41, or metal materials, etc.) above the top surface of the protrusion, yielding the target metal conductor 32. Of course, if precise grinding stop cannot be achieved in the actual process, it is sufficient to ensure that the protrusion 31 is exposed after the CMP process ends. This increases the effective contact area between the target metal conductor 32 and the subsequently deposited dielectric layer or upper interconnect structure, as shown in the specific structure. Figure 9 As shown.
[0077] In the above embodiments, the volume ratio of the air gap structure is mainly determined by the position and size of the protrusions. Specifically, the width of the air gap structure is controlled by the spacing between adjacent protrusions: the smaller the spacing, the earlier the upper oxides close, and the wider the resulting air gap is usually; the height of the air gap mainly depends on the height difference between the bottom surface of the groove and the bottom surface of the protrusion, and the greater this height difference, the greater the vertical dimension of the air gap. Furthermore, by adjusting the parameters of the surface treatment process (such as plasma power and treatment time), the growth rate of the oxides in different regions can be controlled, thereby further achieving fine adjustment of the air gap morphology and size.
[0078] For example, the material of the oxide layer includes low-k porous carbon-doped silicon oxide (SICOH), non-porous carbon-doped silicon oxide (SICO), or silicon oxide (SiO2).
[0079] Figure 10 This paper presents magnified images of the local morphology of the structure prepared using the method provided in this application, corresponding to... Figure 9 At the location indicated by the dashed box, compared to the dielectric constant of traditional porous low-dielectric-constant materials (approximately 2.6 ± 0.1), the air gap structure introduced by this method has a vertical height that accounts for approximately 70% of the total height of the dielectric region and a horizontal width that accounts for approximately 50% of the spacing between adjacent conductors. The dielectric composite (mainly composed of air and Low-k materials or silicon oxide) can have its dielectric constant reduced to below 2.1, effectively reducing RC delay and improving device speed and reliability.
[0080] The target metal wire, oxide layer, air gap structure and remaining dielectric stack form an interconnect structure. After step S110, steps S102-S110 are repeated to form a multilayer interconnect structure constituting a metal interconnect layer.
[0081] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.
[0082] Example 2
[0083] Example 2 is basically the same as Example 1, and the similarities will not be described in detail here. The main difference between Example 2 and Example 1 is that:
[0084] In the extended step of S108, an ion implantation process is used to treat the exposed surface of the liner oxide layer. By implanting specific ions (such as hydrogen ions or oxygen-containing ions) with a certain energy and angle, the density of dangling bonds such as -OH or -H can be increased in the inner wall region of the groove, which is at least as high as the height of the protrusion. Because ion implantation has a certain directionality and adjustable energy, it can precisely concentrate the modification effect on the exposed sidewall region of the protrusion, while significantly reducing the impact on the deeper groove region below. This creates a spatially differentiated distribution of dangling bonds, laying the foundation for differential growth during subsequent oxide deposition.
[0085] Example 3
[0086] Example 3 is basically the same as Example 1, and the similarities will not be described in detail here. The main difference between Example 3 and Example 1 is that:
[0087] In the extended step of step S108, alkaline wet cleaning of the exposed surface of the liner oxide layer is performed using alkaline solutions such as ammonia (NH4OH) or tetramethylammonium hydroxide (TMAH). Due to the influence of surface tension and capillary action, the alkaline solution is more likely to fully contact and react in the area with a wider opening above the protrusion to generate dangling bonds such as -OH or -H. However, the penetration in the deep groove area below the protrusion is relatively limited, which may result in a relatively low efficiency of dangling bond generation in this area, creating a certain difference in surface state in space.
[0088] Example 4
[0089] This embodiment provides a metal interconnect layer, which is prepared using the preparation method described in any of the above embodiments. Since this metal interconnect layer and the preparation method are based on the same inventive concept, the metal interconnect layer prepared using this method has all the advantages mentioned in the preparation method, which will not be elaborated further here.
[0090] In the above embodiments, the unexpected technical effect of this application is:
[0091] By designing protrusions on the sidewalls of metal wires and utilizing their physical shielding effect, combined with selective surface treatment of the inner wall of the groove, controllable fabrication of the air gap structure is achieved. Its width and height can be controlled by designing the spacing between adjacent protrusions, the height difference between the bottom of the groove and the bottom of the protrusion, and the parameters of the surface treatment process (such as power and time). This effectively eliminates the additional photolithography and etching steps used in traditional processes to define the air gap morphology, simplifying the process and potentially reducing costs.
[0092] In addition, the materials and processes used in the entire fabrication process of the air gap structure (such as low-temperature ALD, conventional CVD, CMP, etc.) are highly compatible with existing integrated circuit manufacturing platforms, providing a highly feasible solution for reducing interconnect parasitic capacitance and alleviating RC delay problems.
[0093] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0094] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for fabricating a metal interconnect layer, characterized in that, include: Provide a substrate; A dielectric stack and initial metal wires are alternately arranged on the substrate along a first direction parallel to the first surface of the substrate; The sidewall of the initial metal conductor includes a protrusion, which is embedded in the dielectric stack along the first direction; After etching the dielectric stack to form a groove between adjacent initial metal wires that exposes the surface of the initial metal wires, a pad oxide layer is formed covering the inner surface of the groove and the top surface of the initial metal wires; the bottom surface of the groove is lower than the bottom surface of the protrusion. The exposed surface of the pad oxide layer is subjected to a surface treatment process, which increases the target dangling bonds for increasing the coating rate by adding at least a certain number of target dangling bonds to the inner surface of the groove below the protrusion. Due to the obstruction of the protrusion, the formation efficiency of the target dangling bonds in the groove region below the protrusion is lower than that in the groove region above the protrusion, thereby creating a spatial difference in the distribution of the target dangling bonds. After forming an oxide layer in the groove, the remaining film layer with its top surface higher than the top surface of the protrusion is removed to obtain the target metal wire; the oxide layer has an air gap structure.
2. The preparation method according to claim 1, characterized in that, The width ratio of the air gap structure within the oxide layer is related to the spacing between adjacent protrusions; The height percentage of the air gap structure within the oxide layer is related to the height difference between the protrusion and the remaining dielectric stack.
3. The preparation method according to claim 1, characterized in that, The dielectric stack includes a diffusion barrier layer, a dielectric layer, a sacrificial dielectric layer, and a sacrificial stack stacked sequentially along the direction away from the substrate; The dielectric layer and the sacrificial stack are made of dielectric materials with a dielectric constant less than 3; The material of the oxide layer includes porous carbon-doped silicon oxide, non-porous carbon-doped silicon oxide, or silicon oxide. The material of the sacrificial dielectric layer is configured to have an etching rate greater than that of the other layers in the dielectric stack.
4. The preparation method according to claim 3, characterized in that, The protrusion includes: The dielectric stack is formed on the substrate; The dielectric stack is etched to form trenches spaced apart along the first direction; wherein the etching rate of the sacrificial dielectric layer is greater than the etching rate of the other film layers, such that the width of the sacrificial dielectric layer is smaller than that of the diffusion barrier layer, the dielectric layer, and the sacrificial stack, forming an inward shrinkage; An initial metal wire is formed to fill the groove, and the initial metal wire located at the inward position constitutes the protrusion.
5. The preparation method according to claim 1, characterized in that, The surface treatment process includes: A plasma treatment process is performed on the exposed surface of the pad oxide layer to add -H or -OH dangling bonds to the inner surface of the groove at least below the protrusion and the top surface of the initial metal wire.
6. The preparation method according to claim 5, characterized in that, The plasma processing technology is performed using a mixture of inert gas and oxygen-containing gas, hydrogen-containing gas, or ammonia-containing gas.
7. The preparation method according to claim 1, characterized in that, The surface treatment process includes: An ion implantation process is performed on the exposed surface of the pad oxide layer to add -H or -OH dangling bonds to the inner surface of the groove at least below the protrusion and the top surface of the initial metal wire.
8. The preparation method according to claim 1, characterized in that, The surface treatment process includes: The exposed surface of the liner oxide layer is subjected to alkaline wet cleaning, which adds -H or -OH dangling bonds to the inner surface of the groove at least below the protrusion and the top surface of the initial metal wire.
9. The preparation method according to any one of claims 1-8, characterized in that, The target metal wire, the oxide layer, and the remaining dielectric stack constitute an interconnect structure; After forming the interconnect structure, the method further includes: repeating the steps of forming the target metal wire on the substrate and forming the oxide layer to form a multilayer interconnect structure constituting the metal interconnect layer.
10. A metal interconnect layer, characterized in that, It is prepared by the preparation method according to any one of claims 1-9.