Semiconductor device
By designing the layout of packaging components and heat-conducting elements in semiconductor devices, the problem of insufficient heat dissipation of semiconductor switching elements is solved, heat dissipation performance and integration are improved, crosstalk in electrical connection paths is reduced, and device stability is enhanced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- INNOSCIENCE (SUZHOU) TECH CO LTD
- Filing Date
- 2026-01-09
- Publication Date
- 2026-04-21
AI Technical Summary
In existing semiconductor devices, the heat dissipation of semiconductor switching elements is poor, which leads to high temperatures adversely affecting the performance of the elements and drivers.
The packaged component design embeds the semiconductor switching element and driver within the packaged component. The heat-conducting component contacts the fourth surface of the switching element, while the heat exchange surface is exposed on the second surface. Heat is exchanged with the external medium through the heat-conducting component. Combined with the pin structure, the heat dissipation path is optimized to improve the heat dissipation effect.
It achieves efficient heat dissipation of semiconductor switching elements, improves the heat dissipation performance and integration of semiconductor devices, reduces crosstalk in electrical connection paths, and enhances shock resistance.
Smart Images
Figure CN121908880A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor device technology, and more particularly to a semiconductor device. Background Technology
[0002] In the field of semiconductor packaging, some semiconductor devices integrate a semiconductor switching element and a driver for driving that switching element into the same package structure. When a semiconductor device containing a semiconductor switching element is in use, the switching element generates a significant amount of heat.
[0003] In related technologies, semiconductor devices have poor heat dissipation for semiconductor switching elements, and high temperatures inside the semiconductor device can easily have an adverse effect on the performance of semiconductor switching elements and drivers. Summary of the Invention
[0004] This application provides a semiconductor device that improves the heat dissipation effect of semiconductor switching elements and enhances the heat dissipation performance of the semiconductor device.
[0005] This application provides a semiconductor device comprising: a package assembly having opposing first and second surfaces, the package assembly including a first pin and a second pin located on the first surface; a semiconductor switching element embedded within the package assembly, the semiconductor switching element having a third surface facing the first surface and a fourth surface facing the second surface, the semiconductor switching element including switching electrodes for electrical connection, all of the switching electrodes of the semiconductor switching element being located on the third surface, and at least one of the switching electrodes being electrically connected to the first pin; a driver embedded within the package assembly and located on the side of the fourth surface of the semiconductor switching element, the driver including a chip electrode for electrical connection, at least one of the chip electrodes being electrically connected to the second pin; and a thermal conductive element at least partially located within the package assembly and on the side of the fourth surface of the semiconductor switching element, the thermal conductive element contacting the fourth surface, the thermal conductive element having a heat exchange surface exposed from the second surface.
[0006] According to the foregoing embodiments of this application, the packaging assembly includes a substrate, a first packaging layer, and a second packaging layer sequentially stacked from the first surface to the second surface. The first surface is one surface of the substrate, the second surface is one surface of the second packaging layer, the semiconductor switching element is located within the first packaging layer, and the driver and at least a portion of the thermal conductive element are located within the second packaging layer.
[0007] According to any of the foregoing embodiments of this application, the first packaging layer includes a support layer, the support layer includes a receiving groove, and the semiconductor switching element is located within the receiving groove.
[0008] According to any of the foregoing embodiments of this application, the first encapsulation layer further includes an insulating filler that fills the receiving groove.
[0009] According to any of the foregoing embodiments of this application, the first encapsulation layer is a resin encapsulation layer.
[0010] According to any of the foregoing embodiments of this application, the thermally conductive component includes a thermally conductive block and a thermally conductive interconnect. The thermally conductive block is embedded in the second encapsulation layer and has the heat exchange surface. The thermally conductive interconnect is connected to the thermally conductive block and passes through a portion of the first encapsulation layer and is connected to the fourth surface.
[0011] According to any of the foregoing embodiments of this application, the heat-conducting block includes a first heat-conducting portion and a second heat-conducting portion disposed along the thickness direction of the second encapsulation layer and connected to each other. The area of the orthographic projection of the second heat-conducting portion on the second surface is greater than the area of the orthographic projection of the first heat-conducting portion on the second surface. The second heat-conducting portion is located on the side of the driver away from the first surface. The orthographic projection of the second heat-conducting portion on the plane where the driver is located overlaps with the driver.
[0012] According to any of the foregoing embodiments of this application, the substrate has a wiring surface opposite to the first surface, and the semiconductor device further includes: a first electrical connector located within the package assembly and electrically connecting the switching electrode to the first pin, wherein the first electrical connector includes a first pad and a first via conductor, the first pad is located on the wiring surface, the first pad is connected to the corresponding switching electrode, and the first via conductor penetrates the substrate and is electrically connected between the first pad and the first pin.
[0013] According to any of the foregoing embodiments of this application, the substrate has a wiring surface opposite to the first surface, and the semiconductor device further includes: a second electrical connector located within the packaging assembly and electrically connecting the chip electrode to the corresponding second pin, wherein the second electrical connector includes a second pad, a second via conductor, and a third via conductor, the second pad being located on the wiring surface, the second via conductor penetrating the first packaging layer and electrically connecting the second pad to the corresponding chip electrode, and the third via conductor penetrating the substrate and electrically connecting the second pad to the second pin.
[0014] According to any of the foregoing embodiments of this application, the number of semiconductor switching elements is two or more, the orthographic projection of the driver onto the plane where the semiconductor switching elements are located overlaps with at least two of the semiconductor switching elements, and at least a portion of the second via conductor of the second electrical connector is located between adjacent semiconductor switching elements.
[0015] According to any of the foregoing embodiments of this application, the semiconductor switching element includes a first semiconductor switching element, a second semiconductor switching element, a third semiconductor switching element, and a fourth semiconductor switching element. The first semiconductor switching element and the second semiconductor switching element are spaced apart along a first direction. The third semiconductor switching element and the fourth semiconductor switching element are located on one side of the first semiconductor switching element and the second semiconductor switching element along a second direction, which is perpendicular to the first direction. The orthographic projection of the driver onto the plane where the semiconductor switching element is located overlaps with the first semiconductor switching element and the second semiconductor switching element. The second via conductor of a portion of the second electrical connector is located between the first semiconductor switching element and the second semiconductor switching element, and the second via conductor of a portion of the second electrical connector is located on the side of the first semiconductor switching element and the second semiconductor switching element away from the third semiconductor switching element and the fourth semiconductor switching element.
[0016] According to any of the foregoing embodiments of this application, the semiconductor device further includes: a third electrical connector located within the packaging assembly, which electrically connects the chip electrode to the switch electrode.
[0017] According to any of the foregoing embodiments of this application, the semiconductor switching element includes a first semiconductor switching element, a second semiconductor switching element, a third semiconductor switching element, and a fourth semiconductor switching element. The first semiconductor switching element and the second semiconductor switching element are spaced apart along a first direction. The third semiconductor switching element and the fourth semiconductor switching element are located on one side of the first semiconductor switching element and the second semiconductor switching element along a second direction, which is perpendicular to the first direction. The third semiconductor switching element and the fourth semiconductor switching element share the same substrate.
[0018] According to any of the foregoing embodiments of this application, the first semiconductor switching element and the second semiconductor switching element are high-voltage side switching elements, and the third semiconductor switching element and the fourth semiconductor switching element are low-voltage side switching elements.
[0019] According to an embodiment of the semiconductor device of this application, the package assembly has a first surface and a second surface facing each other, and a first pin and a second pin are arranged on the first surface. A semiconductor switching element embedded within the package assembly has a third surface facing the first surface and a fourth surface facing the second surface. All switching electrodes of the semiconductor switching element are located on the third surface, i.e., all switching electrodes of the semiconductor switching element are located on its surface facing the first surface. The fourth surface of the semiconductor switching element does not have switching electrodes, and therefore does not have electrical connection-related structures. Thus, the entire second surface can serve as the connection surface for a heat dissipation structure. A heat-conducting element contacts the fourth surface, and the heat exchange surface of the heat-conducting element is exposed from the second surface. The heat-conducting element exchanges heat with the heat exchange medium outside the semiconductor device through the heat exchange surface, achieving efficient heat dissipation of the semiconductor switching element. According to an embodiment of the semiconductor device of this application, the pin structure for electrical connection, i.e., the first pin and the second pin, are both located on the first surface, allowing a larger area of heat exchange surface to be arranged on the second surface, thereby improving the heat dissipation effect on the semiconductor switching element and enhancing the heat dissipation performance of the semiconductor device. Attached Figure Description
[0020] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.
[0021] Figure 1 This is a perspective view of one embodiment of the semiconductor device according to this application; Figure 2 This is a perspective view of another embodiment of a semiconductor device according to this application; Figure 3 This is a top view schematic diagram of one embodiment of a semiconductor device according to this application; Figure 4 This is a cross-sectional schematic diagram of one embodiment of a semiconductor device according to this application; Figure 5 This is a top view schematic diagram of a substrate, a first packaging layer, and a semiconductor switching element in one embodiment of the semiconductor device according to this application; Figure 6 yes Figure 3 Schematic diagram of the cross section in the middle BB direction; Figure 7 This is a cross-sectional schematic diagram of an alternative embodiment of the semiconductor device according to this application. Detailed Implementation
[0022] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.
[0023] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movement of the components in a specific posture (as shown in the attached figures); if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.
[0024] This application provides a semiconductor device. Figure 1 , Figure 2 These are perspective schematic diagrams from different viewpoints of one embodiment of the semiconductor device according to this application. Figure 3 This is a top view schematic diagram of one embodiment of the semiconductor device according to this application. Figure 4 This is a cross-sectional schematic diagram of one embodiment of the semiconductor device according to this application. Figure 3 The AA line in the diagram shows Figure 4 The cross-sectional view shows the cut position. The semiconductor device 100 includes a package assembly 110, a semiconductor switching element 120, a driver 130, and a heat-conducting component 140.
[0025] The package assembly 110 has a first surface S1 and a second surface S2 opposite to each other. The package assembly 110 includes a first pin P1 and a second pin P2 located on the first surface S1.
[0026] The first pin P1 and the second pin P2 are conductive structural components. In some embodiments, the first pin P1 and the second pin P2 are metal components. In one example, the first pin P1 and the second pin P2 are made of copper.
[0027] Semiconductor switching element 120 is embedded within package assembly 110. Semiconductor switching element 120 has a third surface S3 facing a first surface S1 and a fourth surface S4 facing a second surface S2. Semiconductor switching element 120 includes switching electrodes 121 for electrical connection, all of which are located on the third surface S3, and at least one switching electrode 121 is electrically connected to a first pin P1.
[0028] Semiconductor switching element 120 is, for example, a high electron mobility transistor (HEMT). In other embodiments, semiconductor switching element 120 may be other switching elements such as metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), etc. In this embodiment, semiconductor switching element 120 is, for example, a gallium nitride (GaN) HEMT. Switching electrode 121 is, for example, the gate electrode, source electrode, or drain electrode of a gallium nitride HEMT.
[0029] In some embodiments, the number of semiconductor switching elements 120 in the semiconductor device 100 is one, while in some embodiments, the number of semiconductor switching elements 120 in the semiconductor device 100 is two or more.
[0030] Driver 130 is embedded within package assembly 110 and located on the side of the fourth surface S4 of semiconductor switching element 120. Driver 130 includes chip electrodes 131 for electrical connection, at least one of which is electrically connected to a second pin P2. Driver 130 internally houses an integrated circuit for driving semiconductor switching element 120. Specifically, driver 130 provides a drive signal for controlling the semiconductor switching element 120 to turn on or off. In one example, the drive signal is a high-level or low-level signal that acts on a control terminal (e.g., the gate of semiconductor switching element 120) of semiconductor switching element 120, causing semiconductor switching element 120 to turn on or off.
[0031] The thermal conductive element 140 is at least partially located within the package assembly 110 and on the side where the fourth surface S4 of the semiconductor switching element 120 is located. The thermal conductive element 140 is in contact with the fourth surface S4. The thermal conductive element 140 has a heat exchange surface 140a exposed from the second surface S2.
[0032] The heat-conducting element 140 can be made of a material with high thermal conductivity known in the art. In some embodiments, the heat-conducting element 140 can be made of a metal with good thermal conductivity. In one example, at least a portion of the heat-conducting element 140 is made of copper.
[0033] The heat exchange surface 140a of the heat-conducting element 140 exchanges heat with the heat exchange medium outside the semiconductor device 100. In one example, the heat exchange medium outside the semiconductor device 100 is air, and the heat exchange surface 140a of the heat-conducting element 140 exchanges heat with the air to achieve heat dissipation. In other embodiments, the heat exchange surface 140a of the heat-conducting element 140 can be used in conjunction with other heat exchange devices or heat dissipation devices, such as liquid cooling heat exchange devices or air cooling heat exchange devices, to achieve more efficient heat dissipation.
[0034] According to an embodiment of this application, a semiconductor device 100 has a package assembly 110 with opposing first surfaces S1 and second surfaces S2. A first pin P1 and a second pin P2 are arranged on the first surface S1. A semiconductor switching element 120 embedded within the package assembly 110 has a third surface S3 facing the first surface S1 and a fourth surface S4 facing the second surface S2. All switching electrodes 121 of the semiconductor switching element 120 are located on the third surface S3, i.e., all switching electrodes 121 of the semiconductor switching element 120 are located on its surface facing the first surface S1. The fourth surface S4 of the semiconductor switching element 120 does not have switching electrodes 121, and therefore does not have electrical connection-related structures. Thus, the entire second surface S2 can serve as the connection surface for a heat dissipation structure. A heat-conducting element 140 contacts the fourth surface S4, and its heat exchange surface 140a is exposed from the second surface S2. The heat-conducting element 140 exchanges heat with the heat exchange medium outside the semiconductor device 100 through the heat exchange surface 140a, thereby achieving efficient heat dissipation for the semiconductor switching element 120. According to the embodiments of the present application, the semiconductor device 100 has a pin structure for electrical connection, namely the first pin P1 and the second pin P2, which are both located on the first surface S1, so that the second surface S2 can be arranged with a larger heat exchange surface 140a, thereby improving the heat dissipation effect on the semiconductor switching element 120 and improving the heat dissipation performance of the semiconductor device 100.
[0035] In some embodiments, the packaging assembly 110 includes a substrate 111, a first packaging layer 112, and a second packaging layer 113 sequentially stacked from a first surface S1 to a second surface S2. The first surface S1 is one surface of the substrate 111. The second surface S2 is one surface of the second packaging layer 113. A semiconductor switching element 120 is located within the first packaging layer 112. A driver 130 and at least a portion of a thermally conductive element 140 are located within the second packaging layer 113.
[0036] In some embodiments, substrate 111 is a core support layer of semiconductor device 100, and substrate 111 may include an insulating support plate and conductive wiring disposed on the insulating support plate. In some embodiments, second encapsulation layer 113 is a resin encapsulation layer.
[0037] In the above embodiment, the semiconductor switching element 120 is located in the first packaging layer 112 and the driver 130 is located in the second packaging layer 113, so that the driver 130 and the semiconductor switching element 120 are stacked in the thickness direction of the semiconductor device 100, which further improves the integration of the semiconductor device 100 and makes the package size of the semiconductor device 100 smaller.
[0038] Figure 5 This is a top view schematic diagram of a substrate, a first packaging layer, and a semiconductor switching element in one embodiment of the semiconductor device according to this application. In some embodiments, the first packaging layer 112 includes a support layer 1121, and the support layer 1121 includes a receiving groove C1. The semiconductor switching element 120 is located within the receiving groove C1.
[0039] In this embodiment, the first encapsulation layer 112 includes a support layer 1121. The material of the support layer 1121 can be the same as that of the insulating support plate of the substrate 111, that is, the support layer 1121 can be made of the same material used to make the insulating support plate for the core support layer. In one example, the support layer 1121 is made of glass fiber and epoxy resin.
[0040] In the above embodiment, the support layer 1121 includes a receiving groove C1, and the semiconductor switching element 120 is located in the receiving groove C1, which facilitates the direct connection of the switching electrode 121 of the semiconductor switching element 120 to the conductive wiring on the substrate 111, thereby reducing the electrical connection path between the semiconductor switching element 120 and the external device of the semiconductor device 100, and making the electrical connection path resistance of the semiconductor switching element 120 smaller and the crosstalk less.
[0041] In some embodiments, the first pin P1 can have a larger area on the first surface S1, thereby providing better heat dissipation for the semiconductor switching element 120. In the above embodiments, the semiconductor switching element 120 is located in the receiving groove C1, which facilitates the direct connection of the switching electrode 121 of the semiconductor switching element 120 to the conductive wiring on the substrate 111, making the heat conduction path of the semiconductor switching element 120 through the first pin P1 shorter and improving the bottom heat dissipation capability of the semiconductor switching element 120 (i.e., the heat dissipation capability of the first surface S1).
[0042] In some embodiments, the first encapsulation layer 112 further includes an insulating filler 1122, which is filled within the receiving groove C1. The insulating filler 1122 can be a liquid filler or a solid filler. The insulating filler 1122 enables the semiconductor switching element 120 to be positioned more stably within the first encapsulation layer 112, thereby improving the shock resistance of the semiconductor device 100.
[0043] In an alternative embodiment, the first encapsulation layer 112 is a resin encapsulation layer. The first encapsulation layer 112 may be made of the same material as the second encapsulation layer 113.
[0044] In some embodiments, the thermally conductive element 140 includes a thermally conductive block 141 and a thermally conductive interconnect 142, wherein the thermally conductive block 141 is embedded in the second encapsulation layer 113. The thermally conductive block 141 has a heat exchange surface 140a. The thermally conductive interconnect 142 is connected to the thermally conductive block 141, passes through a portion of the first encapsulation layer 112, and is connected to the fourth surface S4.
[0045] The heat-conducting block 141 and the heat-conducting interconnect 142 can be made of materials with high thermal conductivity known in the art. In one example, the heat-conducting block 141 is a copper block. In another example, the heat-conducting interconnect 142 is a metal component. The heat-conducting interconnect 142 may include a plurality of columnar interconnects connected between the heat-conducting block 141 and the semiconductor switching element 120 along the thickness direction of the semiconductor device 100.
[0046] In the above embodiment, the heat-conducting block 141 is embedded in the second encapsulation layer 113, and its block structure ensures efficient heat conduction. In the above embodiment, the pin structures for electrical connection, namely the first pin P1 and the second pin P2, are both located on the first surface S1, while the heat-conducting block 141 for heat dissipation is exposed on the second surface S2. On the surface of the semiconductor device 100, the electrical connection structure and the heat dissipation structure are located on different surfaces, avoiding crosstalk effects on the electrical connection structure when the heat-conducting component 140 is a conductive material.
[0047] like Figure 5 In some embodiments, the number of semiconductor switching elements 120 is two or more, and the orthographic projection of the driver 130 onto the plane containing the semiconductor switching elements 120 overlaps with at least two semiconductor switching elements 120. In one example, the orthographic projection of the driver 130 onto the plane containing the semiconductor switching elements 120 overlaps with two semiconductor switching elements 120; in other examples, the orthographic projection of the driver 130 onto the plane containing the semiconductor switching elements 120 may overlap with three, four, or other numbers of semiconductor switching elements 120. The driver 130 and the semiconductor switching elements 120 are stacked in the thickness direction of the semiconductor device 100, further improving the integration of the semiconductor device 100 and making the package size of the semiconductor device 100 smaller.
[0048] like Figure 5In some embodiments, the semiconductor switching element 120 includes a first semiconductor switching element 120a, a second semiconductor switching element 120b, a third semiconductor switching element 120c, and a fourth semiconductor switching element 120d. The first semiconductor switching element 120a and the second semiconductor switching element 120b are spaced apart along a first direction X. The third semiconductor switching element 120c and the fourth semiconductor switching element 120d are located on the side of the first semiconductor switching element 120a and the second semiconductor switching element 120b along a second direction Y. The second direction Y is perpendicular to the first direction X.
[0049] In some embodiments, the first encapsulation layer 112 has a first functional region, a second functional region, and a third functional region. The first functional region and the second functional region are spaced apart along a first direction X, and the third functional region is located on one side of the first functional region and the second functional region along a second direction Y. A first semiconductor switching element 120a is disposed in the first functional region, a second semiconductor switching element 120b is disposed in the second functional region, and a third semiconductor switching element 120c and a fourth semiconductor switching element 120d are disposed in the third functional region.
[0050] like Figure 5 In some embodiments, the third semiconductor switching element 120c and the fourth semiconductor switching element 120d share the same substrate, further improving integration.
[0051] In some embodiments, the first semiconductor switching element 120a and the second semiconductor switching element 120b are high-side (HS) switching elements, for example, the first semiconductor switching element 120a and the second semiconductor switching element 120b are HSHEMTs; the third semiconductor switching element 120c and the fourth semiconductor switching element 120d are low-side (LS) switching elements, for example, the third semiconductor switching element 120c and the fourth semiconductor switching element 120d are LS HEMTs.
[0052] In some embodiments, the substrate 111 has a wiring surface S9 opposite to the first surface S1. In some embodiments, the semiconductor device 100 further includes a first electrical connector 150 located within the package assembly 110 and electrically connecting the switching electrode 121 to the first pin P1.
[0053] In this embodiment, the first electrical connector 150 includes a first pad 151 and a first via conductor 152. The first pad 151 is located on the wiring surface S9 and is connected to the corresponding switch electrode 121. The first via conductor 152 penetrates the substrate 111 and is electrically connected between the first pad 151 and the first pin P1.
[0054] In some embodiments, each semiconductor switching element 120 includes a plurality of switching electrodes 121, such as a gate electrode, a source electrode, and a drain electrode. In some embodiments, each switching electrode 121 of each semiconductor switching element 120 is electrically connected to a corresponding first pin P1 via a corresponding first electrical connector 150, such that all switching electrodes 121 of all semiconductor switching elements 120 are led out to the corresponding first pin P1 of the first surface S1. In other embodiments, a portion of the plurality of switching electrodes 121 may be electrically connected to the corresponding first pin P1 via corresponding first electrical connectors 150; for example, the source electrode and the drain electrode are respectively electrically connected to the corresponding first pin P1 via their respective corresponding first electrical connectors 150.
[0055] In some embodiments, depending on the layout of the switch electrode 121 and the corresponding first pin P1, and according to the wiring structure requirements within the semiconductor device 100, at least one first electrical connector 150 may further include a first connection wiring. The first connection wiring is located on the wiring surface S9 or inside the substrate 111, and the first connection wiring electrically connects the first pad 151 in the first electrical connector 150 to the first via conductor 152.
[0056] In some embodiments, the substrate 111 has a wiring surface S9 opposite to the first surface S1. In some embodiments, the semiconductor device 100 further includes a second electrical connector 160 located within the package assembly 110, which electrically connects the chip electrode 131 to the second pin P2.
[0057] Figure 6 yes Figure 3 Schematic diagram of the cross section along the BB direction. Figure 2 The middle section also uses the BB line to illustrate this. Figure 6 The location and direction of the cutoff. For example... Figure 4 , Figure 6 In some embodiments, the second electrical connector 160 includes a second pad 161, a second via conductor 162, and a third via conductor 163. The second pad 161 is located on the wiring plane S9. The second via conductor 162 penetrates the first package layer 112 and electrically connects the second pad 161 to the corresponding chip electrode 131. The third via conductor 163 penetrates the substrate 111 and electrically connects the second pad 161 and the second pin P2.
[0058] In this embodiment, all the chip electrodes 131 of the driver 130 are located on the surface of the driver 130 facing the first surface S1.
[0059] In some embodiments, depending on the layout of the chip electrode 131 and the corresponding second pin P2, and according to the wiring structure requirements within the semiconductor device 100, at least one second electrical connector 160 may further include a second connection wiring and / or a third connection wiring. The second connection wiring is located on the wiring surface S9 and electrically connects the second pad 161 in the second electrical connector 160 to the third via conductor 163. The third connection wiring is located on the first surface S1 and electrically connects the third via conductor 163 in the first electrical connector 150 to the corresponding second pin P2.
[0060] In some embodiments, the driver 130 includes a plurality of chip electrodes 131, such as signal input electrodes, power supply input electrodes, drive signal output electrodes, etc. In some embodiments, each chip electrode 131 is electrically connected to a corresponding second pin P2 via a corresponding second electrical connector 160, such that all chip electrodes 131 of all semiconductor switching elements 120 are led out to the corresponding second pin P2 of the first surface S1.
[0061] As described above, in some embodiments, the number of semiconductor switching elements 120 is two or more, and the orthographic projection of the driver 130 onto the plane containing the semiconductor switching elements 120 overlaps with at least two semiconductor switching elements 120. In some embodiments, at least a portion of the second via conductor 162 of the second electrical connection 160 is located between adjacent semiconductor switching elements 120. Figure 5 In one example, there are four semiconductor switching elements 120, and the orthographic projection of the driver 130 onto the plane containing the semiconductor switching elements 120 overlaps with two of the semiconductor switching elements 120. At least a portion of the second via conductor 162 of the second electrical connector 160 is located between adjacent semiconductor switching elements 120 that overlap with the driver 130.
[0062] In one example, the semiconductor switching element 120 includes a first semiconductor switching element 120a, a second semiconductor switching element 120b, a third semiconductor switching element 120c, and a fourth semiconductor switching element 120d. The first semiconductor switching element 120a and the second semiconductor switching element 120b are spaced apart along a first direction X. The third semiconductor switching element 120c and the fourth semiconductor switching element 120d are located on one side of the first semiconductor switching element 120a and the second semiconductor switching element 120b along a second direction Y, which is perpendicular to the first direction X. In this embodiment, the orthographic projection of the driver 130 onto the plane containing the semiconductor switching element 120 overlaps with the first semiconductor switching element 120a and the second semiconductor switching element 120b.
[0063] like Figure 5In one example, the second via conductor 162 of a portion of the second electrical connector 160 is located between the first semiconductor switching element 120a and the second semiconductor switching element 120b, and the second via conductor 162 of a portion of the second electrical connector 160 is located on the side of the first semiconductor switching element 120a and the second semiconductor switching element 120b away from the third semiconductor switching element 120c and the fourth semiconductor switching element 120d. That is, the second via conductor 162 of a portion of the second electrical connector 160 is located on the side of the first semiconductor switching element 120a and the second semiconductor switching element 120b away from the third semiconductor switching element 120c and the fourth semiconductor switching element 120d along the second direction Y.
[0064] In some other embodiments, the driver 130 is not limited to overlapping the projections of the two semiconductor switching elements 120. For example, in another example, the orthographic projection of the driver 130 onto the plane containing the semiconductor switching elements 120 overlaps with the first semiconductor switching element 120a, the second semiconductor switching element 120b, the third semiconductor switching element 120c, and the fourth semiconductor switching element 120d. In this case, at least a portion of the second electrical connection 160 can be provided between each pair of adjacent semiconductor switching elements 120 as a second via conductor 162.
[0065] In other embodiments, a portion of the multiple chip electrodes 131 may be electrically connected to a corresponding second pin P2 via a corresponding second electrical connector 160. A portion of the chip electrodes 131 may also be electrically connected to a corresponding switch electrode 121 within the package assembly 110. In some embodiments, the semiconductor device 100 further includes a third electrical connector (not shown) located within the package assembly 110, which electrically connects the chip electrodes 131 to the switch electrodes 121. In one example, the drive signal output electrode of the driver 130 is correspondingly connected to the gate electrode of the semiconductor switching element 120, and the drive signal output electrode is used to transmit a drive signal to the semiconductor switching element 120.
[0066] In one example, substrate 111 has a wiring surface S9 opposite to the first surface S1. The third electrical connector includes a third pad, a fourth pad, a fourth via conductor, and a fourth connection wiring. The third pad and the fourth pad are located on the wiring surface S9, and the third pad is connected to the corresponding switch electrode 121. The fourth via conductor penetrates the first package layer 112 and electrically connects the fourth pad to the corresponding chip electrode 131. The fourth connection wiring may be located on the wiring surface S9, and the fourth connection wiring electrically connects the third pad and the fourth pad of the third electrical connector.
[0067] Figure 7This is a cross-sectional schematic diagram of an alternative embodiment of the semiconductor device according to this application. Parts of the structure of the alternative embodiment are the same as those of the foregoing embodiment; the differences will be described below, while the similarities will not be detailed further.
[0068] The thermally conductive component 140 includes a thermally conductive block 141 and a thermally conductive interconnect 142. The thermally conductive block 141 is embedded in the second encapsulation layer 113. The thermally conductive block 141 has a heat exchange surface 140a. The thermally conductive interconnect 142 is connected to the thermally conductive block 141, passes through a portion of the first encapsulation layer 112, and is connected to the fourth surface S4.
[0069] In this embodiment, the heat-conducting block 141 includes a first heat-conducting portion 1411 and a second heat-conducting portion 1412 disposed along the thickness direction of the second encapsulation layer 113 and interconnected thereto. The first heat-conducting portion 1411 has a first cross-sectional area in its cross-section perpendicular to the thickness direction of the second encapsulation layer 113, and the area of the orthographic projection of the second heat-conducting portion 1412 onto the second surface S2 is larger than the area of the orthographic projection of the first heat-conducting portion 1411 onto the second surface S2. The second heat-conducting portion 1412 is located on the side of the driver 130 away from the first surface S1, and the orthographic projection of the second heat-conducting portion 1412 onto the plane of the driver 130 overlaps with the driver 130.
[0070] In the above embodiment, the second heat-conducting portion 1412 of the heat-conducting block 141 has a larger area of orthographic projection on the second surface S2. The second heat-conducting portion 1412 is located on the side of the driver 130 away from the first surface S1. The orthographic projection of the second heat-conducting portion 1412 on the plane where the driver 130 is located overlaps with the driver 130, thereby further utilizing the space of the second encapsulation layer 113 and further improving the heat dissipation performance of the heat-conducting block 141.
[0071] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A semiconductor device, characterized in that, include: A package assembly having opposing first and second surfaces, the package assembly including a first pin and a second pin located on the first surface; A semiconductor switching element is embedded within the package assembly. The semiconductor switching element has a third surface facing the first surface and a fourth surface facing the second surface. The semiconductor switching element includes switching electrodes for electrical connection. All of the switching electrodes of the semiconductor switching element are located on the third surface, and at least one of the switching electrodes is electrically connected to the first pin. A driver, embedded within the package assembly and located on the side of the fourth surface of the semiconductor switching element, the driver including a chip electrode for electrical connection, at least one of the chip electrodes being electrically connected to the second pin; A thermal conductive element, at least partially located within the package assembly and on the side of the fourth surface of the semiconductor switching element, is in contact with the fourth surface and has a heat exchange surface exposed from the second surface.
2. The semiconductor device according to claim 1, characterized in that, The packaging assembly includes a substrate, a first packaging layer, and a second packaging layer, which are sequentially stacked from the first surface to the second surface. The first surface is a surface of the substrate, the second surface is a surface of the second packaging layer, the semiconductor switching element is located in the first packaging layer, and the driver and at least a portion of the thermal conductive element are located in the second packaging layer.
3. The semiconductor device according to claim 2, characterized in that, The first encapsulation layer includes a support layer, the support layer includes a receiving groove, and the semiconductor switching element is located within the receiving groove.
4. The semiconductor device according to claim 3, characterized in that, The first encapsulation layer further includes an insulating filler that fills the receiving groove.
5. The semiconductor device according to claim 2, characterized in that, The first encapsulation layer is a resin encapsulation layer.
6. The semiconductor device according to claim 2, characterized in that, The thermally conductive component includes a thermally conductive block and a thermally conductive interconnect. The thermally conductive block is embedded in the second encapsulation layer and has the heat exchange surface. The thermally conductive interconnect is connected to the thermally conductive block and passes through a portion of the first encapsulation layer and is connected to the fourth surface.
7. The semiconductor device according to claim 6, characterized in that, The heat-conducting block includes a first heat-conducting portion and a second heat-conducting portion that are disposed along the thickness direction of the second encapsulation layer and connected to each other. The area of the orthographic projection of the second heat-conducting portion on the second surface is greater than the area of the orthographic projection of the first heat-conducting portion on the second surface. The second heat-conducting portion is located on the side of the driver away from the first surface. The orthographic projection of the second heat-conducting portion on the plane where the driver is located overlaps with the driver.
8. The semiconductor device according to claim 2, characterized in that, The substrate has a wiring surface opposite to the first surface, and the semiconductor device further includes: A first electrical connector is located within the package assembly and electrically connects the switching electrode to the corresponding first pin. The first electrical connector includes a first pad and a first via conductor. The first pad is located on the wiring surface and is connected to the corresponding switch electrode. The first via conductor passes through the substrate and is electrically connected between the first pad and the first pin.
9. The semiconductor device according to claim 2, characterized in that, The substrate has a wiring surface opposite to the first surface, and the semiconductor device further includes: The second electrical connector is located within the packaging assembly and electrically connects the chip electrode to the corresponding second pin. The second electrical connector includes a second pad, a second via conductor, and a third via conductor. The second pad is located on the wiring surface. The second via conductor penetrates the first packaging layer and electrically connects the second pad to the corresponding chip electrode. The third via conductor penetrates the substrate and electrically connects the second pad to the second pin.
10. The semiconductor device according to claim 9, characterized in that, The number of semiconductor switching elements is two or more, the orthographic projection of the driver onto the plane where the semiconductor switching elements are located overlaps with at least two of the semiconductor switching elements, and at least a portion of the second via conductor of the second electrical connector is located between adjacent semiconductor switching elements.
11. The semiconductor device according to claim 9, characterized in that, The semiconductor switching element includes a first semiconductor switching element, a second semiconductor switching element, a third semiconductor switching element, and a fourth semiconductor switching element. The first semiconductor switching element and the second semiconductor switching element are spaced apart along a first direction. The third semiconductor switching element and the fourth semiconductor switching element are located on one side of the first semiconductor switching element and the second semiconductor switching element along a second direction, and the second direction is perpendicular to the first direction. The orthographic projection of the driver onto the plane where the semiconductor switching element is located overlaps with the first semiconductor switching element and the second semiconductor switching element; The second via conductor of a portion of the second electrical connector is located between the first semiconductor switching element and the second semiconductor switching element, and the second via conductor of a portion of the second electrical connector is located on the side of the first semiconductor switching element and the second semiconductor switching element away from the third semiconductor switching element and the fourth semiconductor switching element.
12. The semiconductor device according to claim 1, characterized in that, Also includes: A third electrical connector is located within the packaging assembly and electrically connects the chip electrode to the corresponding switch electrode.
13. The semiconductor device according to claim 1, characterized in that, The semiconductor switching element includes a first semiconductor switching element, a second semiconductor switching element, a third semiconductor switching element, and a fourth semiconductor switching element. The first semiconductor switching element and the second semiconductor switching element are spaced apart along a first direction. The third semiconductor switching element and the fourth semiconductor switching element are located on one side of the first semiconductor switching element and the second semiconductor switching element along a second direction, and the second direction is perpendicular to the first direction. The third semiconductor switching element and the fourth semiconductor switching element share the same substrate.
14. The semiconductor device according to claim 13, characterized in that, The first semiconductor switching element and the second semiconductor switching element are high-voltage side switching elements, and the third semiconductor switching element and the fourth semiconductor switching element are low-voltage side switching elements.