Semiconductor device and semiconductor device preparation method
By combining a conductive layer and a heat dissipation layer in a semiconductor device, the current conduction cross-sectional area between the drain and the drain pad is maximized, and heat dissipation is carried out on both sides of the chip. This solves the problems of poor heat dissipation and difficulty in utilizing high-frequency characteristics in traditional packaging, achieving low power consumption and efficient heat dissipation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING ZHONGKE XINWEITE SCI & TECH DEV
- Filing Date
- 2026-01-20
- Publication Date
- 2026-04-21
AI Technical Summary
Traditional packaging methods make it difficult for semiconductor devices to achieve high-frequency and low-power characteristics, and their heat dissipation effect is limited, resulting in the inability to maximize chip performance.
A conductive layer is used to set up a first surface region and a second surface region with a height difference to ensure that the current conduction cross-sectional area between the drain and the drain pad is maximized, and heat dissipation is performed on both sides of the chip. The combination of the conductive layer and the heat dissipation layer achieves double-sided heat dissipation and avoids short circuits caused by the leakage of conductive medium.
This achieves low power consumption characteristics of low-voltage, low-on-resistance chips, improves heat dissipation efficiency, and ensures stable operation and efficient heat dissipation of semiconductor devices.
Smart Images
Figure CN121908881A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of semiconductors, and in particular relates to a semiconductor device and a method for fabricating a semiconductor device. Background Technology
[0002] In the semiconductor field, chips are becoming increasingly powerful, possessing higher thermal conductivity, higher frequency characteristics, higher voltage, and greater power handling capabilities. However, traditional packaging methods make it difficult for them to reach their full potential. For surface-mount devices, the traditional method of using wire bonding to achieve electrical interconnection results in excessively large parasitic inductance parameters, making it difficult to utilize the high-frequency characteristics of the chip. Furthermore, for low-voltage, low-on-resistance chips, the contact resistance introduced by the bonding wires also makes it difficult for the chip to achieve low-power characteristics. Summary of the Invention
[0003] This application provides a method for fabricating semiconductor devices, which can solve the problems in the prior art where surface-mount devices are electrically interconnected by bonding wires, resulting in excessively large parasitic inductance parameters, making it difficult to utilize the high-frequency characteristics of the chip. Furthermore, for low-voltage, low-on-resistance chips, the contact resistance introduced by the bonding wires also makes it difficult for the chip to utilize its low-power characteristics.
[0004] In a first aspect, embodiments of this application provide a semiconductor device, including: A chip includes a drain pad, a source pad, and a gate pad. The electrode portion includes a first insulating layer, and a gate, a source, and a drain disposed through the first insulating layer; The heat dissipation part includes a conductive layer. The surface of the conductive layer facing the electrode part includes a first surface region and a second surface region with a height difference, and the height of the first surface region is lower than the height of the second surface region. The first surface region is connected to the first contact surface of the drain electrode near the conductive layer and covers the entire first contact surface; the second surface region is connected to the second contact surface of the drain electrode pad near the conductive layer and covers the entire second contact surface. The source pad on the side of the chip facing away from the conductive layer is connected to the source, and the gate pad on the side of the chip facing away from the conductive layer is connected to the gate.
[0005] In one feasible implementation, the heat dissipation part further includes a heat dissipation layer; The heat dissipation layer is located on the side of the conductive layer that faces away from the electrode.
[0006] In one feasible implementation, the heat dissipation portion further includes a second insulating layer; The second insulating layer is located between the heat dissipation layer and the conductive layer.
[0007] In one feasible implementation, the aforementioned second surface region is connected to all surfaces of the chip that are adjacent to the heat dissipation portion.
[0008] In one feasible implementation, the heat dissipation part further includes a heat dissipation housing for connection with the electrode part; The heat dissipation housing includes a recessed structure consisting of a heat dissipation base and a metal frame; The groove structure contains a second insulating layer and a conductive layer arranged sequentially from bottom to top.
[0009] In one feasible implementation, the electrode portion is formed with a sealing welding ring; the electrode portion is welded to the heat dissipation housing via the sealing welding ring in a parallel seam welding manner.
[0010] In one feasible implementation, a buffer layer is provided between the first surface region and the drain electrode.
[0011] In one feasible implementation, a buffer layer is provided between the source electrode and the source electrode pad. A buffer layer is provided between the gate and the gate pad.
[0012] Secondly, embodiments of this application provide a method for fabricating a semiconductor device, the method comprising: A chip, an electrode section, and a heat dissipation section are provided; the chip includes a drain pad, a source pad, and a gate pad; the electrode section includes a first insulating layer, and a gate, a source, and a drain disposed through the first insulating layer; the heat dissipation section includes a conductive layer, and the surface of the conductive layer facing the electrode section includes a first surface region and a second surface region having a height difference, and the height of the first surface region is lower than the height of the second surface region. The second surface region is connected to the second contact surface of the drain pad that is close to the conductive layer, so that the second surface region covers the entire second contact surface; The first surface region is connected to the first contact surface of the drain near the conductive layer so that the first surface region covers the entire first contact surface, while the source pad is connected to the source and the gate pad is connected to the gate.
[0013] In one feasible implementation, the heat dissipation part further includes a heat dissipation housing for connecting with the electrode part. The heat dissipation housing includes a groove structure composed of a heat dissipation base and a metal frame. A second insulating layer and a conductive layer are sequentially disposed in the groove structure from bottom to top. The above-mentioned connection of the first surface region to the first contact surface of the drain near the conductive layer, so that the first surface region covers the entire first contact surface, and simultaneously connecting the source pad to the source and the gate pad to the gate, includes: The electrode portion is sealed and welded to the heat sink housing so that the first surface area is connected to the first contact surface of the drain electrode near the conductive layer, the first surface area covers the entire first contact surface, and at the same time the source pad is connected to the source electrode and the gate pad is connected to the gate electrode.
[0014] The semiconductor device and semiconductor device fabrication method of this application embodiment, by setting a first surface region connected to the first contact surface of the drain electrode near the conductive layer and covering the entire first contact surface, and setting a second surface region connected to the second contact surface of the chip's drain pad near the conductive layer and covering the entire second contact surface, can maximize the current conduction cross-sectional area between the drain electrode and the drain pad, thereby reducing contact resistance and achieving low power consumption characteristics of low-voltage, low-on-resistance chips. It can also reduce heat generation and ensure effective heat dissipation. By setting the surface of the conductive layer near the electrode portion to include a first surface region and a second surface region with a height difference, and the height of the first surface region being lower than the height of the second surface region, it can prevent the conductive medium at the connection between the drain electrode and the conductive layer from overflowing to the chip surface, causing the chip to short-circuit, thus achieving stable operation of the semiconductor device. Furthermore, the set conductive layer can dissipate heat on one side of the chip drain electrode, achieving double-sided heat dissipation of the chip and improving the heat dissipation effect. Attached Figure Description
[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0016] Figure 1 This is a schematic diagram of the structure of a chip in an existing semiconductor device; Figure 2 This is a schematic diagram of the packaging structure of an existing semiconductor device; Figure 3 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application; Figure 4 This is a schematic diagram of a semiconductor device with a heat dissipation layer provided in an embodiment of this application; Figure 5 This is a schematic diagram of a semiconductor device with a second insulating layer provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a heat dissipation shell in a semiconductor device provided in an embodiment of this application; Figure 7 This is a schematic cross-sectional view of a heat dissipation housing in a semiconductor device provided in an embodiment of this application; Figure 8 This is a schematic diagram of the structure of the electrode portion in a semiconductor device provided in an embodiment of this application; Figure 9 This is a schematic cross-sectional view of the electrode portion in a semiconductor device provided in an embodiment of this application; Figure 10 This is a schematic diagram of the packaged structure of a semiconductor device provided in an embodiment of this application; Figure 11 This is a schematic cross-sectional view of a packaged semiconductor device provided in an embodiment of this application; Figure 12 This is a schematic flowchart of a semiconductor device fabrication method provided in an embodiment of this application; The annotations in the attached figures are explained as follows: 11-Gate pad, 12-Source pad, 13-Drain pad; 21-Metal frame, 22-Ceramic frame, 23-Gate or source, 24-Drain, 25-Cover plate, 26-Sealed cavity, 27-Chip, 28-Solder, 29-Bond wire; 31-First insulating layer, 32-Conductive layer; 40 - Heat dissipation layer; 50 - Second insulating layer; 60 - Heat sink housing, 61 - Heat sink base; 81-Gate, 82-Source, 83-Sealing weld ring. Detailed Implementation
[0017] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.
[0018] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.
[0019] In the semiconductor field, chips are becoming increasingly powerful, possessing higher thermal conductivity, higher frequency characteristics, higher voltage, and greater power handling capabilities. For example, MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices are widely used in power electronics as core electronic components due to their low on-resistance, high power, and simple driving characteristics. With the research and development of third-generation semiconductor materials, silicon carbide power devices have rapidly developed in the high-voltage field and are widely used in power electronic systems due to their numerous advantages such as high breakdown voltage, high power, low on-resistance, and high temperature resistance. Nitride semiconductor devices have also found important applications in the high-frequency field due to their excellent power density, efficiency, and frequency characteristics.
[0020] As chips become increasingly powerful, possessing higher thermal conductivity, higher frequency characteristics, higher voltage, and greater power handling capabilities, traditional packaging methods struggle to fully realize their advantages. (See reference...) Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the structure of a chip in an existing semiconductor device. In the existing chip packaging structure, the gate pad 11, source pad 12, and drain pad 13 are all located on the same side of the chip. In this case, the chip can be electrically connected to the corresponding electrode metal by flip-chip bonding. Existing chips with this structure generally only dissipate heat on one side through the side that is electrically connected to the electrode metal, which has limited heat dissipation effect. Figure 2This is a schematic diagram of a conventional semiconductor device packaging structure. A metal frame 21, a ceramic frame 22, a gate or source 23, a drain 24, and a cover plate 25 constitute the package shell, which forms a sealed cavity 26. The drain pad of the chip 27 is soldered to the drain 24 via solder 28, and the source and gate pads of the chip are electrically connected to the gate and source via bonding wires 29. In this packaging structure, the chip 27 still only dissipates heat on one side, towards the drain 24. Furthermore, the traditional method of using wire bonding for surface-mount devices to achieve electrical interconnection results in excessively large parasitic inductance parameters, making it difficult to utilize the chip's high-frequency characteristics. For low-voltage, low-on-resistance chips, the contact resistance introduced by the bonding wires also hinders the chip's low-power characteristics. In addition, because the electrodes and heat sink in traditional semiconductor packaging structures are located on the same side of the chip and are generally of the same structure, the heat dissipation design is limited, making it difficult to utilize the device's high-power processing capabilities. The complex heat dissipation design also leads to high system design costs.
[0021] To address the problems in the prior art, this application provides a semiconductor device and a method for fabricating a semiconductor device.
[0022] This application maximizes the current conduction cross-sectional area between the drain and the conductive layer by setting a first surface region that connects to and covers the first contact surface of the drain electrode and the conductive layer, and setting a second surface region that connects to and covers the second contact surface of the drain pad of the chip and the conductive layer. This reduces contact resistance, achieves low power consumption characteristics of the low-voltage, low-on-resistance chip, and reduces heat generation, ensuring effective heat dissipation. By setting the conductive layer surface near the electrode to include a first surface region and a second surface region with a height difference, and the height of the first surface region being lower than the height of the second surface region, the conductive medium at the connection between the drain and the conductive layer can be prevented from overflowing to the chip surface, causing a short circuit in the chip, thus ensuring stable operation of the semiconductor device. Furthermore, the conductive layer can dissipate heat on one side of the chip drain, achieving double-sided heat dissipation of the chip and improving the heat dissipation effect.
[0023] The semiconductor devices provided in the embodiments of this application will be described below.
[0024] Figure 3 A schematic diagram of the structure of a semiconductor device according to an embodiment of this application is shown. Figure 3 As shown, the semiconductor device may include the following structure: Chip 27 includes a drain pad, a source pad, and a gate pad; The electrode portion includes a first insulating layer 31, and a gate, a source, and a drain 24 disposed through the first insulating layer 31; The heat dissipation part includes a conductive layer 32. The surface of the conductive layer 32 facing the electrode part includes a first surface region and a second surface region with a height difference, and the height of the first surface region is lower than the height of the second surface region. The first surface region is connected to the first contact surface of the drain 24 toward the conductive layer 32 and covers the entire first contact surface; the second surface region is connected to the second contact surface of the drain pad of the chip 27 toward the conductive layer 32 and covers the entire second contact surface. The source pad on the side of chip 27 facing away from conductive layer 32 is connected to the source, and the gate pad on the side of chip 27 facing away from conductive layer 32 is connected to the gate 81.
[0025] This embodiment of the application sets a first surface region connected to the first contact surface of the drain 24 near the conductive layer 32 and covering the entire first contact surface, and sets a second surface region connected to the second contact surface of the drain pad of the chip 27 near the conductive layer 32 and covering the entire second contact surface. This maximizes the current conduction cross-sectional area between the drain 24 and the drain pad, thereby reducing contact resistance and achieving the low power consumption characteristics of the low-voltage, low-on-resistance chip 27. It also reduces heat generation and ensures effective heat dissipation. By setting the surface of the conductive layer 32 near the electrode portion to include a first surface region and a second surface region with a height difference, and the height of the first surface region being lower than the height of the second surface region, it can prevent the conductive medium at the connection between the drain 24 and the conductive layer 32 from overflowing to the surface of the chip 27, which could cause a short circuit in the chip 27. This ensures stable operation of the semiconductor device. Furthermore, the conductive layer 32 can dissipate heat on one side of the drain 24 of the chip 27, achieving double-sided heat dissipation of the chip 27 and improving the heat dissipation effect.
[0026] Each structure is explained in detail below: In this embodiment, adapted to a packaging structure, the gate pad and source pad of chip 27 are located on the same side surface of chip 27, while the drain pad of chip 27 should be located on the other side surface of chip 27. In this embodiment, the surface where the drain pad of chip 27 is located is located on the opposite side of the surfaces where the gate pad and source pad of chip 27 are located. At this time, the gate is located on the side where the gate pad of chip 27 is located and can directly contact and connect with the gate pad of chip 27. Similarly, the source is located on the side where the source pad of chip 27 is located and can directly contact and connect with the source pad of chip 27. The drain 24, source, and gate are all disposed at the first insulating layer 31, and the drain 24, source, and gate are all disposed through the first insulating layer 31. The portion of the drain 24, source, and gate extending from the side of the first insulating layer 31 away from chip 27 is used for conductive connection with the outside. In the portions of the source and gate extending from the first insulating layer 31 toward the chip 27, the portions extending from the source and gate are directly connected to the source and gate pads provided on the side of the chip 27 toward the first insulating layer 31. However, the drain 24 is not connected to the drain pad of the chip 27. It is necessary to extend the drain 24 to the other side of the chip 27 to connect with the drain pad of the chip 27, or extend it to the other side of the chip 27 to connect with the drain pad of the chip 27 through a conductive structure. Alternatively, for ease of processing, the drain 24 can be extended to the other side of the chip 27 first, and then extended to the drain pad of the chip 27 through a conductive structure. In this embodiment, the drain 24 is connected to the drain pad of the chip 27 by first extending the drain 24 to the other side of the chip 27 and then extending it to the drain pad of the chip 27 through the conductive layer 32.
[0027] The above method sets up corresponding electrode portions and heat dissipation portions on both sides of the chip 27. The gate, source, and other structures on the side of the chip 27 connected to the electrode portion can achieve heat dissipation of the chip 27. On the side of the chip 27 connected to the heat dissipation portion, the conductive layer 32 can be used to conduct heat away from the chip 27 to achieve heat dissipation, thereby realizing double-sided heat dissipation of the chip 27, improving heat dissipation efficiency, and ensuring stable operation of the chip 27.
[0028] Furthermore, in this embodiment, since the drain 24 extends to the other side of the chip 27, specifically extending past the side of the chip 27, the height of the portion of the drain 24 extending from the first insulating layer 31 toward the chip 27 should be higher than the height of the gate and source on the same side. Simultaneously, the conductive layer 32, on the side surface toward the electrode portion, includes a first surface region and a second surface region with a height difference. The height of the first surface region where the conductive layer 32 connects to the drain 24 is lower than the height of the second surface region where the conductive layer 32 connects to the drain pad in the chip 27. This prevents the conductive medium from overflowing to the adjacent chip 27 and causing a short circuit when the first and second surface regions of the conductive layer 32 are at the same height, thus ensuring stable operation of the chip 27. In this embodiment, the height difference between the first and second surface regions of the conductive layer 32 can be set according to the characteristics of the conductive medium and the distance between the first and second surface regions in actual conditions, as long as the conductive medium at the first surface region does not overflow to the second surface region. At this point, it is necessary to ensure that the conductive layer 32 has a certain thickness. Specifically, the thickness should be greater than the height difference between the first surface region and the second surface region to ensure that the conductive layer 32 can be processed into the above structure.
[0029] Furthermore, in this embodiment, by setting a first surface region connected to the first contact surface of the drain 24 near the conductive layer 32 and covering the entire first contact surface, and a second surface region connected to the second contact surface of the drain pad of the chip 27 near the conductive layer 32 and covering the entire second contact surface, the conductive layer 32 completely covers the drain 24 and the drain pad, maximizing the current conduction cross-sectional area, thereby reducing contact resistance and achieving the low-power characteristics of the low-voltage, low-on-resistance chip 27. The larger contact area also improves the heat dissipation efficiency of the chip 27. In this embodiment, based on the above structure, the source can also cover the entire surface exposed by the source pad, and the gate can cover the entire surface exposed by the gate pad, further reducing the contact resistance of the semiconductor device and ensuring the low-power characteristics of the low-voltage, low-on-resistance chip 27.
[0030] In one feasible embodiment, reference can be made to Figure 4 , Figure 4 This is a schematic diagram of a semiconductor device with a heat dissipation layer provided in an embodiment of this application. To improve the double-sided heat dissipation effect of the semiconductor device, the heat dissipation portion may further include a heat dissipation layer 40; The heat dissipation layer 40 is disposed on the side of the conductive layer 32 facing away from the electrode portion.
[0031] In this embodiment, the heat dissipation section further includes a heat dissipation layer 40. This heat dissipation layer 40 should be a structural layer with high thermal conductivity and can be attached to the conductive layer 32 to dissipate heat from the conductive layer 32 to the outside, ensuring the heat dissipation effect of the chip 27. It should be noted that when the heat dissipation layer 40 is attached to the conductive layer 32, and when the heat dissipation layer 40 serves as the outer shell of a semiconductor package device, it needs to be a non-conductive heat dissipation layer 40 to prevent leakage from the drain pads of the chip 27.
[0032] In one feasible embodiment, reference can be made to Figure 5 , Figure 5 This is a schematic diagram of a semiconductor device with a second insulating layer provided in an embodiment of this application. To prevent leakage of the conductive layer 32 and ensure the operational stability of the semiconductor device, the heat dissipation portion may further include a second insulating layer 50; The second insulating layer 50 is located between the heat dissipation layer 40 and the conductive layer 32.
[0033] In feasible implementations, in order to avoid the material selection of the heat dissipation layer 40 being affected by conductivity and to ensure the heat dissipation effect of the heat dissipation layer 40, the heat dissipation part can be provided to also include a second insulating layer 50. The second insulating layer 50 is disposed between the heat dissipation layer 40 and the conductive layer 32. While ensuring that the material selection of the heat dissipation layer 40 is not affected by conductivity, it can prevent the drain of the chip 27 from being conductively connected to the outside through the heat dissipation layer 40, which could lead to circuit failure of the chip 27. At the same time, it ensures the operational stability and heat dissipation effect of the semiconductor device.
[0034] In one feasible embodiment, in order to reduce the complexity of the conductive layer 32 structure and improve the ease of preparation of the conductive layer 32, the second surface region can be configured to be connected to all surfaces of the chip 27 that are close to the heat dissipation part.
[0035] In this embodiment, the second surface region of the conductive layer 32 is connected to all surfaces of the chip 27 facing the heat dissipation part. That is, the second surface region carries all surfaces of the chip 27 facing the heat dissipation part. On the one hand, the chip 27 is directly attached to the conductive layer 32, ensuring the stability of the structure. On the other hand, the conductive layer 32 is directly connected to all surfaces of the chip 27 facing the heat dissipation part, eliminating the need to consider the precise positioning problem when the conductive layer 32 is connected to the drain pad of the chip 27. By directly contacting the entire surface of the chip 27 with the conductive layer 32, it can naturally be connected to the drain pad, improving the simplicity of the fabrication. At the same time, the surface of the conductive layer 32 can be directly set to a planar shape, reducing the complexity of the fabrication of the conductive layer 32.
[0036] In one feasible embodiment, reference can be made to Figure 6 and Figure 7 , Figure 6This is a schematic diagram of the structure of a heat sink in a semiconductor device provided in an embodiment of this application. Figure 7 This is a cross-sectional structural diagram of a heat sink in a semiconductor device according to an embodiment of this application. To improve the ease of semiconductor device packaging, the aforementioned heat sink may further include a heat sink housing 60 for connection with the electrode portion; The heat sink housing 60 may include a groove structure consisting of a heat sink base 61 and a metal frame 21; The groove structure contains a second insulating layer 50 and a conductive layer 32 arranged sequentially from bottom to top.
[0037] In this embodiment, the heat dissipation part includes a heat dissipation housing 60. After the second insulating layer 50 and the conductive layer 32 are sequentially set in the groove structure in the heat dissipation housing 60 from bottom to top, the electrode part, the chip 27 and the heat dissipation housing 60 can be directly installed and soldered to complete the sealed packaging of the semiconductor device and improve the manufacturing efficiency.
[0038] In one feasible embodiment, reference can be made to Figure 8 and Figure 9 , Figure 8 This is a schematic diagram of the electrode portion in a semiconductor device provided in an embodiment of this application. Figure 9 This is a cross-sectional structural diagram of an electrode portion in a semiconductor device provided in an embodiment of this application. To achieve efficient and stable welding between the electrode portion and the heat sink housing 60, a sealing welding ring 83 can be formed on the electrode portion, and the electrode portion is welded to the heat sink housing 60 via the sealing welding ring 83 in a parallel seam welding manner.
[0039] In this embodiment, the sealing welding ring 83 surrounds the side of the electrode part. When the electrode part is installed with the heat sink housing 60, the sealing welding ring 83 in the electrode part abuts against the top surface of the metal frame 21 in the heat sink housing 60. At this time, the contact gap between the electrode part and the heat sink housing 60 surrounds the side of the overall structure after assembly and is exposed. Therefore, the welding of the electrode part and the heat sink housing 60 can be achieved by using a parallel seam welding process, which improves the stability and efficiency of the welding.
[0040] In one feasible embodiment, in order to ensure a stable and effective weld between the conductive layer 32 and the drain electrode 24 and to avoid poor contact, a buffer layer is provided between the first surface area and the drain electrode 24.
[0041] In this embodiment, the electrode section and heat dissipation section are separately configured during fabrication. However, during assembly, the gate 81 and source 82 in the electrode section may have already contacted the gate pad and source pad, respectively, and the chip 27 may have already contacted the conductive layer 32. Due to tolerances in the device fabrication, the drain 24 may not be able to connect to the surface of the conductive layer 32, resulting in a gap and poor contact. In this embodiment, a buffer layer of a predetermined thickness is provided on the first surface region of the conductive layer 32 and soldered to the drain 24. This buffer layer eliminates the poor contact problem caused by the manufacturing tolerances of each component, ensuring a stable and effective soldering between the conductive layer 32 and the drain 24. The predetermined thickness needs to be sufficient to fill the gap width between the first surface region and the drain 24; that is, the predetermined thickness is greater than or equal to the gap width. In this embodiment, the buffer layer can specifically be a solder layer, and the predetermined thickness can specifically be set to 200-300 micrometers, specifically 250 micrometers.
[0042] In this embodiment, the solder layer is provided firstly to ensure effective contact and conductive connection between the drain electrode 24 and the conductive layer 32, and secondly to improve welding efficiency. That is, the solder layer first serves as a buffer layer to achieve effective contact between the drain electrode 24 and the conductive layer 32, and then plays the role of solder in assisting welding. The reason for setting the solder layer is to consider the adaptability of the solution. The difference between the solder layer in this embodiment and conventional solder is that the preset thickness is set based on the gap width between the first surface area and the drain electrode 24.
[0043] In one feasible embodiment, in order to ensure a stable connection between the components in the semiconductor device, a buffer layer can be provided between the source electrode and the source electrode pad. A buffer layer is provided between the gate and the gate pad.
[0044] In this embodiment of the application, in order to ensure a stable connection between the source and the source pad, and a stable connection between the gate and the gate pad, a buffer layer is provided between the source and the source pad, and a buffer layer is provided between the gate and the gate pad. The buffer layer can be used to eliminate gaps and achieve a stable connection.
[0045] The semiconductor device provided in this application includes a chip 27, which includes a drain pad, a source pad, and a gate pad; an electrode portion, which includes a first insulating layer 31 and a gate, a source, and a drain 24 disposed through the first insulating layer 31; and a heat dissipation portion, which includes a conductive layer 32. The surface of the conductive layer 32 facing the electrode portion includes a first surface region and a second surface region with a height difference, and the height of the first surface region is lower than the height of the second surface region. The first surface region is connected to a first contact surface of the drain 24 facing the conductive layer 32 and covers the entire first contact surface. The second surface region is connected to a second contact surface of the drain pad of the chip 27 facing the conductive layer 32 and covers the entire second contact surface. The source pad on the side of the chip 27 facing away from the conductive layer 32 is connected to the source, and the gate pad on the side of the chip 27 facing away from the conductive layer 32 is connected to the gate 81.
[0046] This embodiment of the application sets a first surface region connected to the first contact surface of the drain 24 near the conductive layer 32 and covering the entire first contact surface, and sets a second surface region connected to the second contact surface of the drain pad of the chip 27 near the conductive layer 32 and covering the entire second contact surface. This maximizes the current conduction cross-sectional area between the drain 24 and the drain pad, thereby reducing contact resistance and achieving the low power consumption characteristics of the low-voltage, low-on-resistance chip 27. It also reduces heat generation and ensures effective heat dissipation. By setting the surface of the conductive layer 32 near the electrode portion to include a first surface region and a second surface region with a height difference, and the height of the first surface region being lower than the height of the second surface region, it can prevent the conductive medium at the connection between the drain 24 and the conductive layer 32 from overflowing to the surface of the chip 27, which could cause a short circuit in the chip 27. This ensures stable operation of the semiconductor device. Furthermore, the conductive layer 32 can dissipate heat on one side of the drain 24 of the chip 27, achieving double-sided heat dissipation of the chip 27 and improving the heat dissipation effect.
[0047] Furthermore, this embodiment of the application includes a heat dissipation layer 40 by setting a heat dissipation part. The heat dissipation layer 40 should be a structural layer with high thermal conductivity and can be attached to the conductive layer 32 to dissipate the heat transferred from the conductive layer 32 to the outside, ensuring the heat dissipation effect of the chip 27 and preventing leakage of the drain pad of the chip 27. The heat dissipation part also includes a second insulating layer 50, which is disposed between the heat dissipation layer 40 and the conductive layer 32. While ensuring that the material of the heat dissipation layer 40 is not affected by conductivity, it can prevent the drain of the chip 27 from being conductively connected to the outside through the heat dissipation layer 40, which could lead to circuit failure of the chip 27. At the same time, it ensures the operational stability and heat dissipation effect of the semiconductor device. By setting the second surface area to be connected to all surfaces of the chip 27 that are close to the heat dissipation part, on the one hand, the stability of the structure is ensured, and on the other hand, there is no need to consider the conductive layer 32 and the chip 27. The precise positioning of the drain pads during connection improves the ease of fabrication, and the surface of the conductive layer 32 can be directly set as a planar shape, reducing the complexity of its fabrication. By providing a heat dissipation section including a heat dissipation housing 60, the electrode section, chip 27, and heat dissipation housing 60 can be directly installed and welded together to complete the sealed encapsulation of the semiconductor device, improving fabrication efficiency. By providing a sealing welding ring 83, the electrode section and heat dissipation housing 60 can be welded using a parallel seam welding process, improving welding stability and efficiency. By providing a buffer layer between the first surface area of the conductive layer 32 and the drain 24, a stable and effective weld between the conductive layer 32 and the drain 24 can be ensured. By providing buffer layers between the source and source pads, and between the gate and gate pads, a stable connection between the components in the semiconductor device can be ensured.
[0048] To make the embodiments of this application easier to understand, this application also provides a specific application scenario embodiment, which specifically includes the following structure. (See reference...) Figure 10 and Figure 11 , Figure 10 This is a schematic diagram of the packaged structure of a semiconductor device provided in an embodiment of this application. Figure 11 This is a schematic cross-sectional view of a packaged semiconductor device provided in an embodiment of this application.
[0049] Chip 27, electrode housing and heat sink housing 60; The electrode housing includes a first insulating layer 31, and a gate metal 81, a source metal 82, and a drain metal 24 disposed through the first insulating layer 31; a first insulating layer 31 is disposed between the gate metal 81, the source metal 82, and the drain metal 24 to separate adjacent electrode metals; the electrode housing is formed with a sealing welding ring 83, and the electrode housing is welded to the heat dissipation housing 60 by parallel seam welding through the sealing welding ring 83; The heat dissipation housing 60 includes a groove structure composed of a heat dissipation base 61 and a metal frame 21. A second insulating layer 50 and a conductive layer 32 are sequentially disposed from bottom to top in the groove structure. The conductive layer 32 forms a first surface region and a second surface region with a height difference against the surface of the electrode housing, and the height of the first surface region is lower than the height of the second surface region. The heat dissipation base 61 is located on the side of the conductive layer 32 facing away from the electrode housing, and the second insulating layer 50 is disposed between the heat dissipation base 61 and the conductive layer 32. The first surface region is connected to the first contact surface of the drain metal 24 toward the conductive layer 32 and covers the entire first contact surface; the second surface region is connected to the second contact surface of the drain pad of the chip 27 toward the conductive layer 32 and covers the entire second contact surface; all surfaces of the chip 27 toward the heat sink 60 are in contact with the second surface region. The source pad of chip 27 facing away from the conductive layer 32 is connected to the source metal 82, and the gate pad of chip 27 facing away from the conductive layer 32 is connected to the gate metal 81. A buffer layer is provided between the first surface region and the drain 24, a buffer layer is provided between the source and the source pad, and a buffer layer is provided between the gate and the gate pad.
[0050] Taking aluminum wire as an example of traditional bonding wire selection, in the existing technology of hermetic ceramic metal tube packaging, if the source bonding wire diameter is 250μm aluminum wire, the approximate calculation formula for the parasitic inductance of the straight wire is shown in formula (1): (1) in, L For parasitic inductance, μ0 is the free permeability. Let r be the length of the material and r be the radius of the material.
[0051] Based on the above calculation formula, using a traditional 250μm bonding wire and an SMD-2 package shape, the source parasitic inductance L is about 18nH. With this solution, the electrode length will become 1.5mm, and the radius will be calculated as 1mm, so the source parasitic inductance L is 2.4nH, reducing the parasitic inductance by 87%.
[0052] The theoretical calculation of contact resistance is shown in formula (2). The contact resistance value is inversely proportional to the cube of the contact radius. The contact area of the bonding wire is significantly lower than the contact area of the electrode directly pressed. Therefore, this scheme can significantly reduce the contact resistance and improve the device performance.
[0053] in, For contact resistance, Let F be the resistivity of the contact material, and F be the force applied at the contact point. R is the equivalent Young's modulus, and R is the radius of the sphere.
[0054] Figure 12 This is a schematic flowchart of a semiconductor device fabrication method provided in an embodiment of this application. As shown in the figure, this method is used to fabricate the semiconductor device described above and may include: S1201: Provides a chip, an electrode section, and a heat dissipation section; the chip includes a drain pad, a source pad, and a gate pad; the electrode section includes a first insulating layer, and a gate, a source, and a drain disposed through the first insulating layer; the heat dissipation section includes a conductive layer, the surface of the conductive layer facing the electrode section includes a first surface region and a second surface region with a height difference, and the height of the first surface region is lower than the height of the second surface region. S1202: Connect the second surface region to the second contact surface of the drain pad that is close to the conductive layer, so that the second surface region covers the entire second contact surface; S1203: Connect the first surface region to the first contact surface of the drain near the conductive layer so that the first surface region covers the entire first contact surface, and at the same time connect the source pad to the source and the gate pad to the gate.
[0055] The above-described method can be used to complete the fabrication of the semiconductor device in the embodiments of this application. Other descriptions of the semiconductor device structure have been clearly described above and will not be repeated here.
[0056] In one feasible embodiment, in order to improve the convenience and efficiency of preparation, the heat dissipation part may further include a heat dissipation housing for connecting with the electrode part. The heat dissipation housing includes a groove structure composed of a heat dissipation base and a metal frame. A second insulating layer and a conductive layer are sequentially disposed in the groove structure from bottom to top. The above-described connection of the first surface region to the first contact surface of the drain near the conductive layer, such that the first surface region covers the entire first contact surface, and simultaneously connecting the source pad to the source and the gate pad to the gate, may include: The electrode portion is sealed and welded to the heat sink housing so that the first surface area is connected to the first contact surface of the drain electrode near the conductive layer, the first surface area covers the entire first contact surface, and at the same time the source pad is connected to the source electrode and the gate pad is connected to the gate electrode.
[0057] In this embodiment, by setting up the electrode part and the heat sink housing, after the corresponding chip is installed, the electrode part and the heat sink housing can be directly sealed and welded to complete the sealed packaging of the semiconductor device, which improves the manufacturing efficiency.
[0058] The semiconductor device fabrication method provided in this application includes S1201: providing a chip, an electrode portion, and a heat dissipation portion; the chip includes a drain pad, a source pad, and a gate pad; the electrode portion includes a first insulating layer, and a gate, a source, and a drain disposed through the first insulating layer; the heat dissipation portion includes a conductive layer, the surface of the conductive layer near the electrode portion including a first surface region and a second surface region having a height difference, and the height of the first surface region being lower than the height of the second surface region; S1202: connecting the second surface region to a second contact surface of the drain pad near the conductive layer, so that the second surface region covers the entire second contact surface; S1203: connecting the first surface region to a first contact surface of the drain near the conductive layer, so that the first surface region covers the entire first contact surface, while connecting the source pad to the source and the gate pad to the gate.
[0059] This embodiment of the application sets a first surface region connected to and covering the first contact surface of the drain electrode near the conductive layer, and a second surface region connected to and covering the second contact surface of the drain pad of the chip near the conductive layer. This maximizes the current conduction cross-sectional area between the drain electrode and the drain pad, thereby reducing contact resistance and achieving low power consumption characteristics of the low-voltage, low-on-resistance chip. It also reduces heat generation and ensures effective heat dissipation. By setting the surface of the conductive layer near the electrode to include a first surface region and a second surface region with a height difference, and the height of the first surface region being lower than the height of the second surface region, it can prevent the conductive medium at the connection between the drain electrode and the conductive layer from overflowing to the chip surface, which could cause a short circuit in the chip. This ensures stable operation of the semiconductor device. Furthermore, the conductive layer can dissipate heat on one side of the chip drain electrode, achieving double-sided heat dissipation and improving the heat dissipation effect.
[0060] The foregoing description, with reference to the structures, preparation methods, and accompanying drawings of embodiments of this disclosure, has described various aspects of this disclosure. The above descriptions are merely specific embodiments of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the structures and methods described above can be referred to the corresponding descriptions in the foregoing structural embodiments, and will not be repeated here. It should be understood that the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application.
Claims
1. A semiconductor device, characterized in that, include: Chip (27), the chip (27) includes a drain pad, a source pad and a gate pad; The electrode portion includes a first insulating layer (31), and a gate (81), a source (82) and a drain (24) disposed through the first insulating layer (31). The heat dissipation part includes a conductive layer (32), the surface of the conductive layer (32) facing the electrode part includes a first surface region and a second surface region with a height difference, and the height of the first surface region is lower than the height of the second surface region. The first surface region is connected to the first contact surface of the drain (24) toward the conductive layer (32) and covers the entire first contact surface; the second surface region is connected to the second contact surface of the drain pad toward the conductive layer (32) and covers the entire second contact surface. The source pad on the side of the chip (27) facing away from the conductive layer (32) is connected to the source (82), and the gate pad on the side of the chip (27) facing away from the conductive layer (32) is connected to the gate (81).
2. The semiconductor device according to claim 1, characterized in that, The heat dissipation part also includes a heat dissipation layer (40). The heat dissipation layer (40) is located on the side of the conductive layer (32) that faces away from the electrode portion.
3. The semiconductor device according to claim 2, characterized in that, The heat dissipation part also includes a second insulating layer (50); The second insulating layer (50) is located between the heat dissipation layer (40) and the conductive layer (32).
4. The semiconductor device according to claim 1, characterized in that, The second surface region is connected to all surfaces of the chip (27) that are adjacent to the heat dissipation part.
5. The semiconductor device according to claim 1, characterized in that, The heat dissipation section also includes a heat dissipation housing (60) for connection with the electrode section. The heat dissipation housing (60) includes a groove structure consisting of a heat dissipation base (21) (61) and a metal frame; The groove structure is provided with a second insulating layer (50) and a conductive layer (32) arranged sequentially from bottom to top.
6. The semiconductor device according to claim 5, characterized in that, The electrode portion is formed with a sealing welding ring (83); the electrode portion is welded to the heat dissipation housing (60) by parallel seam welding through the sealing welding ring (83).
7. The semiconductor device according to any one of claims 1-6, characterized in that, A buffer layer is provided between the first surface area and the drain electrode (24).
8. The semiconductor device according to claim 7, characterized in that, A buffer layer is provided between the source electrode and the source electrode pad; A buffer layer is provided between the gate and the gate pad.
9. A method for fabricating a semiconductor device, characterized in that, include: A chip (27), an electrode portion, and a heat dissipation portion are provided; the chip (27) includes a drain pad, a source pad, and a gate pad; the electrode portion includes a first insulating layer (31), and a gate (81), a source (82), and a drain (24) disposed through the first insulating layer (31); the heat dissipation portion includes a conductive layer (32), the surface of the conductive layer (32) facing the electrode portion includes a first surface region and a second surface region having a height difference, and the height of the first surface region is lower than the height of the second surface region; The second surface region is connected to the second contact surface of the drain pad that is close to the conductive layer (32) so that the second surface region covers the entire second contact surface; The first surface area is connected to the drain (24) and the first contact surface of the conductive layer (32) so that the first surface area covers the entire first contact surface, while the source pad is connected to the source (82) and the gate pad is connected to the gate (81).
10. The method for fabricating a semiconductor device according to claim 9, characterized in that, The heat dissipation part also includes a heat dissipation housing (60) for connecting with the electrode part. The heat dissipation housing (60) includes a groove structure composed of a heat dissipation base (21) (61) and a metal frame. A second insulating layer (50) and the conductive layer (32) are arranged sequentially from bottom to top in the groove structure. The step of connecting the first surface region and the drain (24) to the first contact surface of the conductive layer (32) so that the first surface region covers the entire first contact surface, and simultaneously connecting the source pad to the source (82) and the gate pad to the gate (81), includes: The electrode portion is sealed and welded to the heat dissipation housing (60) so that the first surface area is connected to the drain (24) towards the first contact surface of the conductive layer (32), the first surface area covers the entire first contact surface, and the source pad is connected to the source (82), and the gate pad is connected to the gate (81).