Package structure and method of forming the same

Abstract

A packaging structure and a method for forming the same are disclosed. The method includes: providing a temporary carrier; forming a temporary bonding layer on the temporary carrier; forming a redistribution layer on the temporary bonding layer; forming a dicing opening in a dicing region of the redistribution layer, the sidewalls of the dicing opening having a stepped morphology; and cutting the temporary bonding layer and the temporary carrier based on the dicing opening until the cut penetrates both the temporary bonding layer and the temporary carrier. The stepped morphology of the receding structure can change the single vertical interface morphology, transforming stress concentration points into multi-level continuous transition surfaces, allowing warpage stress to be gradually dispersed between different levels. This multi-level structure forms a stress release buffer mechanism, effectively avoiding stress peaks at interface corners, thereby significantly reducing the risk of interface separation. This effectively improves the delamination problem after cutting, enhancing the interlayer bonding stability and overall reliability of the packaging structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a packaging structure and a method for forming the same. Background Technology

[0002] With the rapid development of the semiconductor industry, chip manufacturing faces increasing challenges. At extremely small sizes, physical bottlenecks become more difficult to overcome, leading to rising R&D and production costs, declining product yields, and a gradual slowdown of Moore's Law, ushering in the post-Moore era for the semiconductor industry. Traditional packaging can no longer meet the new demands represented by artificial intelligence and high-performance computing. Leading companies in the semiconductor manufacturing field have begun to shift their focus from improving wafer manufacturing technology nodes to exploring innovations in system-in-package (SiP) technologies, giving rise to advanced packaging technologies.

[0003] Advanced packaging technologies have significantly improved chip performance by modifying packaging methods without shrinking process nodes. Among these, fan-out packaging technologies, including Fan-Out Wafer Level Packaging (FOWLP) and Fan-Out Panel Level Packaging (FOPLP), have been a key driver of advancements in advanced packaging. Emerging 2.5D and 3D packaging technologies further expand the application potential of flip-chip and wafer-level packaging processes by vertically stacking multiple chips, achieving more efficient input / output. With the rapidly increasing computing power demands of artificial intelligence, these packaging technologies need to support higher frequencies and faster speeds of finer circuitry to shorten data transmission distances between chips, improve chip-to-die collaboration efficiency, thereby enhancing system performance and reducing overall power consumption.

[0004] However, there are still many problems in the formation process of the packaging structure in the existing technology. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a packaging structure and a method for forming the same, so as to improve the reliability of the packaging structure.

[0006] To address the aforementioned problems, the present invention provides a method for forming a packaging structure, comprising: providing a temporary carrier board; forming a temporary bonding layer on the temporary carrier board; forming a redistribution layer on the temporary bonding layer, wherein the dicing region of the redistribution layer has a dicing opening, and the sidewall of the dicing opening has a stepped morphology; and cutting the temporary bonding layer and the temporary carrier board based on the dicing opening until penetrating the temporary bonding layer and the temporary carrier board to form a plurality of mutually separated single-unit structures.

[0007] Optionally, the sidewalls on both sides of the cut opening are stepped.

[0008] Optionally, the cutting opening in the stacking direction of the redistribution layer includes: a plurality of sequentially connected sub-openings.

[0009] Optionally, the redistribution layer includes: a plurality of sub-routing layers stacked sequentially; each of the sub-routing layers has one sub-opening.

[0010] Optionally, the corner positions of the sub-openings in each layer can be oblique, arc-shaped, or multi-folded.

[0011] Optionally, the width of the sub-opening located at the bottom layer is the smallest, and the width of the sub-openings in each layer above the bottom layer is equal.

[0012] Optionally, the size range of the single-side wall retraction of each of the sub-openings located above the bottom layer relative to the sub-opening located at the bottom layer is 50 micrometers to 500 micrometers.

[0013] Optionally, the width of the sub-openings in each layer increases progressively from the stacking direction of the redistribution layers.

[0014] Optionally, the size range of the single-side wall recess of the sub-opening in the adjacent upper layer relative to the sub-opening in the adjacent lower layer is 50 micrometers to 500 micrometers.

[0015] Optionally, the method for forming the cutting opening includes: forming each layer of the sub-opening by employing a number of patterning etching processes, wherein each patterning etching process forms one layer of the sub-opening.

[0016] Optionally, the temporary bonding layer includes: a bonding adhesive layer and a release layer located on the bonding adhesive layer.

[0017] Optionally, after forming several of the individual unit structures, the method further includes: performing debonding processing on each of the individual unit structures to remove the temporary carrier and the temporary bonding layer; forming several solder joints, each of the solder joints being electrically connected to the redistribution layer to form several package structures.

[0018] Accordingly, the present invention also provides a packaging structure formed by the method described in any of the above technical solutions, comprising: a redistribution layer, wherein the sidewalls of the redistribution layer have a stepped morphology.

[0019] Optionally, the redistribution layer includes: a plurality of sub-routing layers stacked sequentially.

[0020] Optionally, the corner positions of the sub-wiring layers in each layer may be oblique, arc-shaped, or multi-folded.

[0021] Optionally, the sidewalls of the sub-wiring layers above the bottom layer are flush with each other, and the sidewalls of the bottom sub-wiring layers protrude from the sidewalls of the sub-wiring layers above the bottom layer.

[0022] Optionally, from the stacking direction of the redistribution layers, the sidewalls of each sub-distribution layer recede layer by layer.

[0023] Optionally, it may also include: a plurality of solder joints, each of which is electrically connected to the redistribution layer.

[0024] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0025] In the method for forming the packaging structure of the present invention, before cutting the temporary carrier and the temporary bonding layer, a cutting opening is formed in the cutting channel region of the redistribution layer, and the sidewall of the cutting opening has a stepped morphology. The stepped morphology of the receding structure can change the single vertical interface shape, transforming stress concentration points into multi-level continuous transition surfaces, allowing warpage stress to be gradually dispersed between different levels. This multi-level structure forms a stress release buffer mechanism, effectively avoiding stress peaks at interface corners, thereby significantly reducing the risk of interface separation. Thus, the delamination problem after cutting is effectively improved, enhancing the interlayer bonding stability and overall reliability of the packaging structure.

[0026] Furthermore, the sidewalls on both sides of the cut opening are stepped. The stepped shape on both sides of the cut opening creates a symmetrical receding structure, allowing the stress dispersion mechanism to work simultaneously on both sides of the cut opening. This avoids asymmetric warping deformation caused by unilateral stress release, ensuring balanced stress distribution across the overall structure. The synergistic effect on both sides more thoroughly decomposes the accumulated stress within the redistribution layer, preventing excessive stress concentration at either interface and further optimizing the interlayer bonding reliability after cutting.

[0027] Furthermore, the corner positions of the sub-openings in each layer are characterized by oblique angles, arcs, or multiple folds. These shapes decompose the stress acting at the location into multiple directional components, reducing local stress peaks and thus improving the stress concentration problem of traditional right-angle corners. This structural design further enhances the anti-delamination capability at the details based on the stepped morphology, thereby further optimizing the reliability of interlayer bonding after cutting.

[0028] Furthermore, from the stacking direction of the redistribution layers, the width of the sub-openings in each layer increases progressively. The progressively widening openings create a finer stress transition gradient, allowing the warpage stress within the redistribution layers to attenuate smoothly and continuously in the vertical direction. This progressive structural design decomposes the stress dispersion process into multiple consecutive stages, avoiding abrupt stress concentration at any interface level and ensuring that the stress amplitude at each layer interface remains below the safe threshold of material bonding strength. This significantly enhances the interlayer bonding reliability and significantly improves the encapsulation structure's resistance to delamination.

[0029] In the packaging structure of this invention, the sidewalls of the redistribution layer have a stepped morphology. This stepped, receding structure alters the single vertical interface shape, transforming stress concentration points into multi-level continuous transition surfaces, allowing warpage stress to be gradually dispersed between different layers. This multi-level structure forms a stress-relieving buffer mechanism, effectively preventing stress peaks at interface corners and significantly reducing the risk of interface separation. This effectively improves the delamination problem after cutting, enhancing the interlayer bonding stability and overall reliability of the packaging structure.

[0030] Furthermore, the corners of the sub-wiring layers in each layer are characterized by oblique angles, arcs, or multiple folds. These shapes decompose the stress acting at the location into multiple directional components, reducing local stress peaks and thus improving the stress concentration problem of traditional right-angle corners. This structural design further enhances the anti-delamination capability at details based on the stepped morphology, thereby further optimizing the interlayer bonding reliability after cutting.

[0031] Furthermore, from the stacking direction of the redistribution layers, the sidewalls of each sub-distribution layer recede layer by layer to construct a finer stress transition gradient, enabling a smooth and continuous attenuation and release of warpage stress within the redistribution layers in the vertical direction. This progressive structural design decomposes the stress dispersion process into multiple continuous stages, avoiding abrupt stress concentration at any interface level and ensuring that the stress amplitude at each interface remains below the safe threshold of material bonding strength. This significantly enhances the reliability of interlayer bonding and significantly improves the encapsulation structure's resistance to delamination. Attached Figure Description

[0032] Figures 1 to 6 This is a schematic diagram of each step in the method for forming the encapsulation structure in an embodiment of the present invention;

[0033] Figure 7 This is a schematic diagram of two packaging structures in another embodiment of the present invention. Detailed Implementation

[0034] As described in the background section, there are still many problems in the formation process of the packaging structure in the prior art. These will be explained in detail below.

[0035] As fan-out panel-level packaging evolves towards miniaturized linewidth and spacing and increased integration density, the redistribution layer (RDL) process faces severe material mechanics challenges. During the curing process of photosensitive polyimide (PSPI), thermal shrinkage occurs, inducing built-in stress and causing the substrate to warp upwards. When the redistribution layer has multiple sub-layers stacked, the stress in each individual sub-layer accumulates layer by layer, significantly amplifying the overall warpage. When a tear occurs in the dicing area, the stress concentration effect is significantly exacerbated, and peeling easily starts from the right-angle edge and propagates along the interface. Ultimately, this leads to adhesion failure between the redistribution layer and the underlying release layer, causing interlayer delamination and severely impacting the reliability of the package structure.

[0036] Based on this, the present invention provides a packaging structure and its formation method. Before cutting the temporary carrier and the temporary bonding layer, a cutting opening is formed in the cutting channel region of the redistribution layer, and the sidewall of the cutting opening has a stepped morphology. The stepped morphology of the receding structure can change the single vertical interface morphology, transforming stress concentration points into multi-level continuous transition surfaces, allowing warpage stress to be gradually dispersed between different levels. This multi-level structure forms a stress release buffer mechanism, effectively avoiding stress peaks at interface corners, thereby significantly reducing the risk of interface separation. Thus, the delamination problem after cutting is effectively improved, enhancing the interlayer bonding stability and overall reliability of the packaging structure.

[0037] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] Figures 1 to 6 This is a schematic diagram of the steps in the method for forming the encapsulation structure in an embodiment of the present invention.

[0039] Please refer to Figure 1 Provide a temporary carrier board 100.

[0040] In this embodiment, the temporary carrier 100 serves as a support component in the fan-out packaging process. Its function is to provide a rigid load-bearing platform, maintaining the overall structural flatness and dimensional stability during interlayer stacking and curing in the packaging process, and preventing pattern distortion due to warping. It maintains structural integrity in subsequent cutting processes, making the monomer separation process controllable. Finally, it achieves damage-free separation from the package through debonding, completing its temporary function.

[0041] The temporary carrier 100 must possess high flatness, excellent thermal stability, sufficient mechanical strength, and good chemical resistance. The temporary carrier 100 is typically made of materials such as glass, silicon wafers, or ceramics, all of which can meet the requirements of high-temperature processes and precise dimensional control. The selection process must comprehensively consider cost, reusability, and compatibility with the bonding adhesive layer to ensure reliable support while achieving cost-effective and efficient large-scale production.

[0042] Please refer to Figure 2 A temporary bonding layer 101 is formed on the temporary carrier plate 100.

[0043] In this embodiment, the temporary bonding layer 101 includes a bonding adhesive layer 1011 and a release layer 1012 located on the bonding adhesive layer 1011. The bonding adhesive layer 1011 provides temporary adhesive force, firmly securing the subsequently formed redistribution layer to the surface of the temporary carrier board 100, ensuring mechanical stability during the process. The release layer 1012 regulates the interfacial bonding strength, ensuring reliable adhesion during the process while achieving non-destructive separation during subsequent debonding. The dual-layer structure design of the bonding adhesive layer 1011 and the release layer 1012 balances process stability and peelability through differentiated material properties, thereby improving the overall reliability of the packaging process.

[0044] Please refer to Figure 3 A redistribution layer 102 is formed on the temporary bonding layer 101. The slit area of ​​the redistribution layer 102 has a slit opening 103, and the sidewall of the slit opening 103 has a stepped shape.

[0045] It should be noted that the redistribution layer 102 is the core interconnect structure of the fan-out package. Its main function is to redistribute the chip's I / O ports, fan out dense pins to a larger area, and support high-frequency and high-speed signal transmission.

[0046] In this embodiment, the redistribution layer 102 includes a plurality of sequentially stacked sub-wiring layers 1021; wherein each sub-wiring layer 1021 includes an electrical interconnect structure and an insulating material (not shown) enclosing the electrical interconnect structure. The insulating material may be photosensitive polyimide (PSPI), which generates built-in stress due to thermal shrinkage during the curing process. When multiple sub-wiring layers 1021 are stacked, the stress of a single sub-wiring layer 1021 will accumulate layer by layer.

[0047] In this embodiment, the sub-wiring layer 1021 described in layer 4 is taken as an example.

[0048] In its embodiments, the number of sub-routing layers in the redistribution layer may be less than or more than four layers.

[0049] In this embodiment, the redistribution layer 102 further includes a seed layer 1022 located at the bottom. The seed layer 1022 serves as a conductive substrate, providing an electron transport path for the electroplating deposition of the electrical interconnection structures in the subsequent sub-wiring layers 1021, ensuring uniform growth of the metal lines and excellent crystal quality. At the same time, the seed layer 1022 can also enhance the interfacial bonding strength and improve the adhesion reliability with the underlying temporary bonding layer 101 through its material properties.

[0050] Before cutting the temporary carrier 100 and the temporary bonding layer 101, a cutting opening 103 is formed in the cutting channel region of the redistribution layer 102, and the sidewalls of the cutting opening 103 have a stepped morphology. This stepped, receding structure alters the single vertical interface morphology, transforming stress concentration points into multi-level continuous transition surfaces, allowing warpage stress to be gradually dispersed between different layers. This multi-level structure forms a stress-relieving buffer mechanism, effectively preventing stress peaks at interface corners, thereby significantly reducing the risk of interface separation. This effectively improves the delamination problem after cutting, enhancing the interlayer bonding stability and overall reliability of the encapsulation structure.

[0051] It should be noted that, in this embodiment, before cutting the temporary bonding layer 101 and the temporary carrier plate 100, the cutting opening 103 is first formed in the redistribution layer 102. This allows the laser energy for subsequent cutting of the temporary bonding layer 101 and the temporary carrier plate 100 to be concentrated at a single point, making it easier to penetrate the material thickness and establish a stable cutting front. The cutting opening 103 can release internal material stress in advance, preventing workpiece deformation or cracking due to thermal stress concentration during subsequent cutting. The cutting opening 103 can also provide a slag removal channel for the auxiliary gas in subsequent laser cutting, allowing molten material to be discharged quickly and preventing it from accumulating in the initial section of the cutting path, ensuring a neat and smooth cut.

[0052] In this embodiment, the sidewalls on both sides of the cutting opening 103 are stepped. The stepped shape on both sides of the cutting opening 103 creates a symmetrical receding structure, allowing the stress dispersion mechanism to act simultaneously on both sides of the cutting opening 103. This avoids asymmetric warping deformation caused by unilateral stress release, ensuring balanced stress distribution across the overall structure. The synergistic effect on both sides can more thoroughly decompose the accumulated stress within the redistribution layer 102, preventing excessive stress concentration at either interface and further optimizing the interlayer bonding reliability after cutting.

[0053] In this embodiment, the cutting opening 103 from the stacking direction of the redistribution layer 102 includes: a plurality of sequentially connected sub-openings 1031, with each sub-distribution layer 1021 having one sub-opening 1031.

[0054] In this embodiment, the cutting opening 103 penetrates the redistribution layer 102, that is, the cutting opening 103 penetrates several sub-wiring layers 1021 and the seed layer 1022 located at the bottom.

[0055] In this embodiment, the width of the sub-openings 1031 in each layer increases progressively from the stacking direction of the redistribution layers 102. The progressively widened openings 103 create a finer stress transition gradient, allowing the warpage stress within the redistribution layers 102 to be smoothly and continuously attenuated and released in the vertical direction. This progressive structural design decomposes the stress dispersion process into multiple continuous stages, avoiding abrupt stress concentration at any interface level and ensuring that the stress amplitude at each layer interface remains below the safe threshold of material bonding strength. This significantly enhances the interlayer bonding reliability and significantly improves the encapsulation structure's resistance to peeling and delamination.

[0056] In this embodiment, the size range of the single-side wall recess d of the adjacent upper layer sub-opening 1031 relative to the adjacent lower layer sub-opening 1031 is 50 micrometers to 500 micrometers. The single-side wall recess d refers to the lateral offset distance of the sidewall of the adjacent sub-opening 1031. The larger the value, the gentler the step slope, the longer the stress dispersion path, and the better the buffering effect. However, increasing the recess d will directly lead to a linear increase in the total width of the cut opening 103, excessively encroaching on the effective chip area that could be used for wiring, and reducing the package integration density. In actual production, it is necessary to balance the stress relief requirements with space utilization. In high-stress scenarios, the upper limit is taken to enhance reliability, while in high-density packaging, the lower limit is preferred to save area, thereby achieving the optimal balance between performance and cost.

[0057] In this embodiment, the method for forming the cutting opening 103 includes: forming each layer of the sub-opening 1031 using a series of patterning etching processes, with each patterning etching process forming one layer of the sub-opening 1031. Specifically, for each sub-wiring layer 1021 formed, a corresponding sub-opening 1031 is formed in that sub-wiring layer 1021.

[0058] Please refer to Figure 4 In this embodiment, the corner positions of the sub-openings 1031 in each layer are oblique angles, arcs, or multiple folds.

[0059] Angled, circular, or multi-folded morphologies can decompose the stress acting at a location into multiple directional components, reducing local stress peaks and thus improving the stress concentration problem at traditional right-angle corners. This structural design further enhances the anti-delamination capability at details based on the stepped morphology, thereby further optimizing the reliability of interlayer bonding after cutting.

[0060] In this embodiment, after the redistribution layer 102 is formed, a chip (not shown) is bonded onto the redistribution layer 102 to complete the electrical connection between the redistribution layer 102 and the chip.

[0061] Please refer to Figure 5 The temporary bonding layer 101 and the temporary carrier plate 100 are cut based on the cutting opening 103 until they penetrate through the temporary bonding layer 101 and the temporary carrier plate 100, forming several mutually separated single-unit structures.

[0062] In this embodiment, laser cutting is used to penetrate the temporary bonding layer 101 and the temporary carrier plate 100. The micron-sized laser spot can precisely cut the temporary carrier plate 100 and the temporary bonding layer 101 along the stepped opening path, and its non-contact characteristic can avoid mechanical stress from damaging the fragile interface.

[0063] Please refer to Figure 6 After forming several of the aforementioned monomer structures, each of the monomer structures is debonded to remove the temporary carrier 100 and the temporary bonding layer 101; several solder joints (not shown) are formed, and each of the solder joints is electrically connected to the redistribution layer 102 to form several encapsulation structures.

[0064] In this embodiment, the debonding process peels the temporary carrier 100 from the bonding adhesive layer 1011 using thermal, optical, or mechanical methods, freeing the redistribution layer 102 from process constraints and making it an independent functional layer, thus completing the transformation from panel-level processing to a single device. The subsequently formed solder joints serve as the electrical interconnection interface between the redistribution layer 102 and the external circuit board, undertaking signal transmission and power supply functions. Their array arrangement directly determines the package I / O density and system-level integration capability, ultimately constructing an independent package structure with complete electrical interconnection, mechanical protection, and external solderability.

[0065] In this embodiment, the figure shows two encapsulation structures formed after cutting.

[0066] It should be noted that in this embodiment, the final package structure includes a molding compound (not shown) to encapsulate the chip. This molding compound is the core protective structure of the chip package and is typically made of thermosetting polymer materials such as epoxy molding compound (EMC), with added silica filler to optimize performance. This layer completely encapsulates the chip through injection molding, providing mechanical support and protection, effectively isolating it from moisture, dust, and chemical corrosion, while also achieving electrical isolation between the chip and the external environment. Furthermore, the molding compound also has an auxiliary heat dissipation function, conducting the heat generated by the chip during operation to the outside.

[0067] Accordingly, this invention also provides a packaging structure, please refer to the following: Figure 6 It includes: a redistribution layer 102, wherein the sidewalls of the redistribution layer 102 have a stepped shape.

[0068] The sidewalls of the redistribution layer 102 have a stepped morphology. This stepped, receding structure alters the single vertical interface shape, transforming stress concentration points into multi-level continuous transition surfaces, allowing warpage stress to be gradually dispersed between different layers. This multi-level structure forms a stress-relieving buffer mechanism, effectively preventing stress peaks at interface corners and significantly reducing the risk of interface separation. This effectively improves the delamination problem after cutting, enhancing the interlayer bonding stability and overall reliability of the encapsulation structure.

[0069] In this embodiment, the redistribution layer 102 includes a plurality of sub-routing layers 1021 stacked sequentially.

[0070] Please continue to refer to this. Figure 4 In this embodiment, the corner positions of the sub-wiring layers 1021 in each layer have oblique angles, arcs, or multiple folds. Oblique angles, arcs, or multiple folds can decompose the stress acting at that location into multiple directional components, reducing local stress peaks and thus improving the stress concentration problem of traditional right-angle corners. This structural design further enhances the anti-delamination capability at details based on the stepped topography, thereby further optimizing the interlayer bonding reliability after cutting.

[0071] In this embodiment, starting from the stacking direction of the redistribution layer 102, the sidewalls of each sub-distribution layer 1021 recede layer by layer to construct a finer stress transition gradient, enabling a smooth and continuous attenuation and release of warpage stress within the redistribution layer 102 in the vertical direction. This progressive structural design decomposes the stress dispersion process into multiple continuous stages, avoiding abrupt stress concentration at any interface level and ensuring that the stress amplitude at each interface remains below the safe threshold of material bonding strength. This significantly enhances the interlayer bonding reliability and significantly improves the encapsulation structure's resistance to peeling and delamination.

[0072] In this embodiment, the packaging structure further includes a plurality of solder joints, each of which is electrically connected to the redistribution layer 102. These solder joints serve as the electrical interconnection interface between the redistribution layer 102 and the external circuit board, undertaking signal transmission and power supply functions. Their array arrangement directly determines the package I / O density and system-level integration capability, ultimately constructing an independent packaging structure with complete electrical interconnection, mechanical protection, and external solderability.

[0073] Figure 7 This is a schematic diagram of two packaging structures in another embodiment of the present invention.

[0074] This embodiment further describes the method for forming the packaging structure based on the above embodiments. The rest is the same as the above embodiments, except that the morphology of the cutting opening 103 is different. The following will provide a detailed description in conjunction with the accompanying drawings.

[0075] Please refer to Figure 7 The width of the sub-opening 1031 located at the bottom layer of the cutting opening 103 is the smallest, and the width of the sub-openings 1031 located above the bottom layer is equal.

[0076] Please continue to refer to this. Figure 7 In this embodiment, the size range of the single-side wall recess d of each of the sub-openings 1031 located at the top of the bottom layer relative to the sub-opening 1031 located at the bottom layer is 50 micrometers to 500 micrometers. The single-side wall recess d refers to the lateral offset distance of the sidewall of the adjacent sub-opening 1031. The larger the value, the gentler the step slope, the longer the stress dispersion path, and the better the buffering effect. However, increasing the recess d will directly lead to a linear increase in the total width of the cutting opening 103, excessively encroaching on the effective chip area that could be used for wiring, and reducing the package integration density. In actual production, it is necessary to balance the stress relief requirements with the space utilization rate. In high-stress scenarios, the upper limit is taken to enhance reliability, while in high-density packaging, the lower limit is preferred to save area, thereby achieving the optimal balance between performance and cost.

[0077] Accordingly, this invention also provides a packaging structure, please refer to the following: Figure 7 The rest are the same as the packaging structure provided in the above embodiments, except that: the sidewalls of the sub-wiring layers 1021 located above the bottom layer in the redistribution layer 102 are flush, and the sidewalls of the sub-wiring layers 1021 located at the bottom layer protrude from the sidewalls of the sub-wiring layers 1021 located above the bottom layer.

[0078] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a package structure, the method comprising: include: Provide temporary carrier board; A temporary bonding layer is formed on the temporary carrier plate; A redistribution layer is formed on the temporary bonding layer, and the cut channel region of the redistribution layer has a cut opening, the sidewall of the cut opening having a stepped morphology. The temporary bonding layer and the temporary carrier are cut through the cutting opening until they penetrate the temporary bonding layer and the temporary carrier, forming several separate monolithic structures.

2. The method of forming a package structure of claim 1, wherein, The sidewalls on both sides of the cut opening are stepped.

3. The method for forming the packaging structure as described in claim 2, characterized in that, The cut opening from the stacking direction of the redistribution layer includes: a plurality of sequentially connected sub-openings.

4. The method for forming the packaging structure as described in claim 3, characterized in that, The rewiring layer includes: a plurality of sub-routing layers stacked sequentially; each of the sub-routing layers has one sub-opening.

5. The method for forming the packaging structure as described in claim 3, characterized in that, The corner positions of the sub-openings in each layer are oblique angles, arcs, or multiple folds.

6. The method for forming the packaging structure as described in claim 3 or 5, characterized in that, The sub-opening at the bottom layer has the smallest width, and the sub-openings at each layer above the bottom layer have the same width.

7. The method for forming the packaging structure as described in claim 6, characterized in that, The size range of the single-side wall receding amount of each of the sub-openings located above the bottom layer relative to the sub-opening located at the bottom layer is 50 micrometers to 500 micrometers.

8. The method for forming the packaging structure as described in claim 3 or 5, characterized in that, From the stacking direction of the redistribution layers, the width of the sub-openings in each layer increases progressively.

9. The method for forming the packaging structure as described in claim 8, characterized in that, The size range of the single-side wall recess of the sub-opening in the adjacent upper layer relative to the sub-opening in the adjacent lower layer is 50 micrometers to 500 micrometers.

10. The method for forming the packaging structure as described in claim 4, characterized in that, The method for forming the cutting opening includes: forming each layer of the sub-opening by employing a number of patterning etching processes, wherein each patterning etching process forms one layer of the sub-opening.

11. The method for forming the packaging structure as described in claim 1, characterized in that, The temporary bonding layer includes: a bonding adhesive layer and a release layer located on the bonding adhesive layer.

12. The method for forming the packaging structure as described in claim 1, characterized in that, After forming several of the aforementioned monomer structures, the process further includes: performing debonding processing on each of the aforementioned monomer structures to remove the temporary carrier board and the temporary bonding layer; forming several solder joints, each of the solder joints being electrically connected to the redistribution layer to form several package structures.

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