Silicon carbide semiconductor device

Abstract

A silicon carbide semiconductor device (10) is provided with: a silicon carbide semiconductor substrate (11) of a first conductivity type; a first semiconductor layer (12) of the first conductivity type; a parallel pn region (26) in which first pillar regions (25) of the first conductivity type and second pillar regions (24) of a second conductivity type are repeatedly and alternately arranged; a second semiconductor layer (13) of the second conductivity type; a second semiconductor region (15) of the second conductivity type, a trench (16), a gate insulating film (17), a gate electrode (18), and a high-concentration region (21) of the second conductivity type provided at a position facing the trench (16) in the depth direction. A connection region (23) of the second conductivity type, which is selectively provided on the second semiconductor layer (13) side with respect to the high-concentration region (21) and on the silicon carbide semiconductor substrate (11) side with respect to the second semiconductor layer (13) so as to be in contact with the high-concentration region (21) and the second semiconductor layer (13); a first electrode (44); and a second electrode (45).

Description

Technical Field

[0001] The disclosure relates to a silicon carbide semiconductor device. Background Technology

[0002] Conventionally, a semiconductor device is known, comprising a carrier transport layer of a first conductivity type, an injection control region of a second conductivity type disposed on the upper surface of the carrier transport layer, an upper buried region of the second conductivity type connected to the lower surface of the injection control region, and a lower buried region of the second conductivity type connected to the lower surface of the upper buried region and the bottom surface of a trench, wherein the lower buried regions are separated from each other between the trenches via the carrier transport layer (for example, see Patent Document 1 below). Additionally, a superjunction silicon carbide semiconductor device is known, which, by alternately providing a lower p-type pillar region and an upper p-type pillar region, maintains its on-resistance even when pattern deviation occurs and suppresses performance deviations (for example, see Patent Document 2 below).

[0003] Existing technical documents Patent documents Patent Document 1: International Publication No. 2022 / 137789 Patent Document 2: Japanese Patent No. 7293750 Summary of the Invention

[0004] Technical issues However, in existing semiconductor device structures, the complex structure of each cell makes it difficult to shorten the cell spacing. Therefore, it is particularly difficult to reduce resistance in SiC, where channel mobility is low. Furthermore, due to the structural complexity, the p-type region of the pn junction becomes thinner, which can easily lead to electric field concentration and a decrease in breakdown voltage.

[0005] In order to solve the problems of the prior art, the purpose of this disclosure is to provide a silicon carbide semiconductor device that can shorten the cell spacing, achieve high voltage resistance and low resistance, and reduce drift resistance.

[0006] Technical solution To address the aforementioned issues and achieve the purpose of this disclosure, the disclosed silicon carbide semiconductor device has the following features: A first semiconductor layer of a first conductivity type with a lower impurity concentration than the silicon carbide semiconductor substrate is disposed on the front side of a first conductivity type silicon carbide semiconductor substrate. Parallel pn regions are provided, and on the surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate side, a first pillar region of the first conductivity type and a second pillar region of the second conductivity type are alternately arranged on a surface parallel to the front side. A second semiconductor layer of a second conductivity type is disposed on the surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate side. A first semiconductor region of the first conductivity type is selectively disposed on the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side. A second semiconductor region of the second conductivity type is selectively disposed on the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side, in a manner that it is in contact with the first semiconductor region and the second semiconductor layer. A trench is provided that penetrates the first semiconductor region and the second semiconductor layer to reach the first semiconductor layer. A gate electrode is disposed inside the trench, separated by a gate insulating film. Inside the first semiconductor layer, a high-concentration region of a second conductivity type is provided at a position opposite the trench along the depth direction. Inside the first semiconductor layer, a connection region of the second conductivity type is selectively provided at a position closer to the second semiconductor layer than the high-concentration region and closer to the silicon carbide semiconductor substrate than the second semiconductor layer, in a manner that connects to the high-concentration region and the second semiconductor layer. A first electrode is provided on the surface of the first semiconductor region and the second semiconductor region. A second electrode is provided on the back side of the silicon carbide semiconductor substrate. The second semiconductor region is periodically arranged along the length direction of the trench, and the connection region is periodically arranged along the length direction of the trench in a region that does not overlap with the second semiconductor region when viewed from above.

[0007] According to the above disclosure, p is set under the trench. + The p-type region (high-concentration region) is shallower than the p-type base region (second semiconductor layer). + Type-type connection region (connection region). Therefore, it is possible to increase the p + Type region and p ++ The area of ​​the p-type contact region connection can suppress feedback capacitance fluctuations and reduce SW losses. Furthermore, because the p-type base region utilizes p... + The p-type connection region reduces the area exposed to the drain electrode side, thus making it less likely to apply high voltage to the p-type base region and improving the withstand voltage. Additionally, the p-type connection region under the trench... + Below the type region, a pn parallel region forming an SJ structure is formed. Therefore, n... - The type-type drift region (first semiconductor layer) achieves high impurity concentration and can realize n- Thinning the thickness of the drift region can reduce drift resistance.

[0008] Technical effect According to the silicon carbide semiconductor device disclosed herein, it is possible to shorten the cell spacing to achieve high voltage withstand and low resistance, and to reduce drift resistance. Attached Figure Description

[0009] Figure 1 This is a perspective view showing the structure of the silicon carbide semiconductor device according to Embodiment 1.

[0010] Figure 2A This illustrates the structure of the silicon carbide semiconductor device according to Embodiment 1. Figure 1 A-A' cross-sectional view.

[0011] Figure 2B This illustrates the structure of the silicon carbide semiconductor device according to Embodiment 1. Figure 1 The B-B' cross-sectional view.

[0012] Figure 2C This illustrates the structure of the silicon carbide semiconductor device according to Embodiment 1. Figure 1 The C-C' cross-sectional view.

[0013] Figure 2D Other structures of the silicon carbide semiconductor device shown in Embodiment 1 are also illustrated. Figure 1 The C-C' cross-sectional view.

[0014] Figure 3A This illustrates the structure of the silicon carbide semiconductor device according to Embodiment 1. Figures 2A to 2C Surface D top view.

[0015] Figure 3B This illustrates the structure of the silicon carbide semiconductor device according to Embodiment 1. Figures 2A to 2C Depth E top view.

[0016] Figure 3C This illustrates the structure of the silicon carbide semiconductor device according to Embodiment 1. Figures 2A to 2C The depth F top view.

[0017] Figure 3D This illustrates the structure of the silicon carbide semiconductor device according to Embodiment 1. Figures 2A to 2C The depth G top view.

[0018] Figure 4 This is a perspective view showing the structure of the silicon carbide semiconductor device according to Embodiment 2.

[0019] Figure 5 This illustrates the structure of the silicon carbide semiconductor device according to Embodiment 2. Figure 4A-A' cross-sectional view.

[0020] Figure 6 This illustrates the structure of the silicon carbide semiconductor device according to Embodiment 2. Figure 5 The top view of B-B'.

[0021] Figure 7 This is a perspective view showing the structure of the silicon carbide semiconductor device according to Embodiment 3.

[0022] Figure 8 This illustrates the structure of the silicon carbide semiconductor device according to Embodiment 3. Figure 7 A-A' cross-sectional view.

[0023] Figure 9 This illustrates the structure of the silicon carbide semiconductor device according to Embodiment 3. Figure 8 The top view of B-B'.

[0024] Figure 10 This is a perspective view showing the structure of the silicon carbide semiconductor device according to Embodiment 4.

[0025] Figure 11 This illustrates the structure of the silicon carbide semiconductor device according to Embodiment 4. Figure 10 A-A' cross-sectional view.

[0026] Figure 12 This illustrates the structure of the silicon carbide semiconductor device according to Embodiment 4. Figure 10 The B-B' cross-sectional view.

[0027] Figure 13 This illustrates the structure of the silicon carbide semiconductor device according to Embodiment 4. Figure 11 and Figure 12 The top view of C-C'.

[0028] Figure 14 This illustrates the structure of a silicon carbide semiconductor device as a comparative example. Figure 16 A-A' cross-sectional view.

[0029] Figure 15 This illustrates the structure of a silicon carbide semiconductor device as a comparative example. Figure 16 The B-B' cross-sectional view.

[0030] Figure 16 This is a perspective view showing the structure of a silicon carbide semiconductor device of a comparative example.

[0031] Figure 17 This is a characteristic diagram showing the relationship between the cell spacing and the on-resistance of the silicon carbide semiconductor device according to Embodiment 1.

[0032] Symbol Explanation 10, 110 Silicon carbide semiconductor devices 11、111 n + Type leak area (n) + Silicon carbide substrate) 12, 112 n - Type Drift Zone 13, 113 p-type base region 14, 114 n + Source area 15, 115 p ++ Type contact area 16, 116 trenches 17, 117 Gate insulating film 18, 118 gate electrodes 19 and 119 interlayer insulating film 20, 120 n-type current diffusion region p under trenches 21 and 121 + Type area 23 p + Type connection area 24 p-type column area 25 n-type column area 26 pn parallel region 38, 138 barrier metals 40, 140 semiconductor substrates 41, 141 n + Type of starting substrate 42, 142 n - Type silicon carbide layer 43 and 143 ohm electrodes 44, 144 source electrodes 45, 145 Drain Electrode 122 p ++ p under type contact area + Type area Detailed Implementation

[0033] <Overview of Embodiments of this Disclosure> To address the aforementioned issues and achieve the purpose of this disclosure, the disclosed silicon carbide semiconductor device has the following features: A first semiconductor layer of a first conductivity type with a lower impurity concentration than the silicon carbide semiconductor substrate is disposed on the front side of a silicon carbide semiconductor substrate of a first conductivity type. Parallel pn regions are provided, on the surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate side, with first pillar regions of the first conductivity type and second pillar regions of the second conductivity type alternately arranged on a surface parallel to the front side. A second semiconductor layer of the second conductivity type is disposed on the surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate side. A first semiconductor region of the first conductivity type is selectively disposed on the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side. A second semiconductor region of the second conductivity type is selectively disposed on the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side, in a manner that it is in contact with the first semiconductor region and the second semiconductor layer. A trench is provided that penetrates the first semiconductor region and the second semiconductor layer to reach the first semiconductor layer. A gate electrode is disposed inside the trench, separated by a gate insulating film. Inside the first semiconductor layer, a high-concentration region of a second conductivity type is provided at a position opposite to the trench in the depth direction. Inside the first semiconductor layer, at a position closer to the second semiconductor layer than the high-concentration region and closer to the silicon carbide semiconductor substrate than the second semiconductor layer, a connection region of the second conductivity type is selectively provided in a manner that connects to the high-concentration region and the second semiconductor layer. A first electrode is provided on the surface of the first semiconductor region and the second semiconductor region. A second electrode is provided on the back side of the silicon carbide semiconductor substrate. The second semiconductor region is periodically arranged along the length direction of the trench, and the connection region is periodically arranged along the length direction of the trench in a region that does not overlap with the second semiconductor region when viewed from above.

[0034] According to the above disclosure, p is set under the trench. + The p-type region (high-concentration region) is shallower than the p-type base region (second semiconductor layer). + Type-type connection region (connection region). Therefore, it is possible to increase the p + Type region and p ++ The area of ​​the p-type contact region connection can suppress feedback capacitance fluctuations and reduce SW losses. Furthermore, because the p-type base region utilizes p... + The p-type connection region reduces the area exposed to the drain electrode side, thus making it less likely to apply high voltage to the p-type base region and improving the withstand voltage. Additionally, the p-type connection region under the trench... + Below the type region, a pn parallel region forming an SJ structure is formed. Therefore, n... - The type-type drift region (first semiconductor layer) achieves high impurity concentration and can realize n -Thinning the drift region can reduce drift resistance.

[0035] Furthermore, the silicon carbide semiconductor device disclosed herein is characterized in that, in the above disclosure, the second pillar region is in contact with the surface of the silicon carbide semiconductor substrate side of the high concentration region, and is disposed on the silicon carbide semiconductor substrate side of the high concentration region.

[0036] Furthermore, the silicon carbide semiconductor device disclosed herein is characterized in that, in the above disclosure, the second pillar region is in contact with the surface of the silicon carbide semiconductor substrate side of the connection region, and is disposed on the silicon carbide semiconductor substrate side of the connection region.

[0037] Furthermore, the silicon carbide semiconductor device disclosed herein is characterized in that, in the above disclosure, the second pillar region is in contact with the surface of the silicon carbide semiconductor substrate side of the second semiconductor region, and is disposed on the silicon carbide semiconductor substrate side of the second semiconductor region.

[0038] Furthermore, the silicon carbide semiconductor device disclosed herein is characterized in that, in the above disclosure, the second pillar region is in contact with the surface of the silicon carbide semiconductor substrate side of the high concentration region and the connection region, and is disposed on the silicon carbide semiconductor substrate side of the high concentration region and the connection region.

[0039] Furthermore, the silicon carbide semiconductor device disclosed herein is characterized in that, in the above disclosure, the width of the second pillar region is the same as the width of the region where the second pillar region is connected to the surface on the opposite side of the silicon carbide semiconductor substrate.

[0040] Furthermore, the silicon carbide semiconductor device disclosed herein is characterized in that, in the above disclosure, the width of the second pillar region is narrower than the width of the region where the second pillar region is connected to the surface on the opposite side of the silicon carbide semiconductor substrate.

[0041] Furthermore, the silicon carbide semiconductor device disclosed herein is characterized in that, in the above disclosure, the periodic repetition spacing between the first pillar region and the second pillar region is 1.8 μm to 2.2 μm.

[0042] <Insights that form the basis of this disclosure> First, the topic of the comparative example semiconductor device will be explained. Silicon carbide (SiC) is expected to be the next-generation semiconductor material to replace silicon (Si). Compared with conventional semiconductor devices using silicon, semiconductor devices using silicon carbide have various advantages, such as reducing the resistance of the device in the conducting state to a few hundredths and being able to operate in environments with higher temperatures (above 200°C). This is due to the inherent characteristics of silicon carbide, such as its band gap being about three times larger than that of silicon and its dielectric breaking electric field strength being nearly an order of magnitude greater than that of silicon.

[0043] As silicon carbide semiconductor devices, Schottky barrier diodes (SBDs), planar gate structures, and trench gate structures of vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) have been commercialized to date.

[0044] A planar gate structure is a MOS gate structure formed by mounting the MOS gate in a flat plate shape on the front side of a semiconductor substrate. A trench gate structure is a MOS gate structure formed by embedding the MOS gate within a trench formed on the front side of the semiconductor substrate (semiconductor chip), with channels (inversion layers) formed along the sidewalls of the trench in a direction orthogonal to the front side of the semiconductor substrate. Therefore, compared to a planar gate structure with channels formed along the front side of the semiconductor substrate, it is possible to increase the unit cell density (the building block of an element) per unit area and increase the current density per unit area, thus offering a cost advantage.

[0045] Figure 14 This illustrates the structure of a silicon carbide semiconductor device as a comparative example. Figure 16 A-A' cross-sectional view. Figure 15 This illustrates the structure of a silicon carbide semiconductor device as a comparative example. Figure 16 The B-B' cross-sectional view. Figure 16 This is a perspective view showing the structure of a silicon carbide semiconductor device of a comparative example. Figures 14-16 The comparative example semiconductor device 110 shown is a vertical MOSFET formed by having a trench gate structure on a semiconductor substrate (semiconductor chip) 140 made of silicon carbide. Figures 14-16 In the text, only the active region is shown, and the edge terminal region is omitted.

[0046] Semiconductor substrate 140 is used to make n - Type drift region 112 of n - Type 142 silicon carbide layer in n composed of silicon carbide +The semiconductor substrate 140 is epitaxially grown on the front side of the type-initiating substrate 141. - The main surface of the silicon carbide layer 142 is set as the front side, and n + The main surface on the side of the type starting substrate 141 is designated as the back surface. On the back surface (n) of the semiconductor substrate 140... + A drain electrode 145 is provided on the entire back surface of the type-starting substrate 141. + Type-starting substrate 141 is n + Leakage area 111.

[0047] In n - Type drift region 112 and n + An n-type current diffusion region 120 is provided on the surface opposite to the silicon carbide substrate 111. Furthermore, within the n-type current diffusion region 120, p-type current diffusion regions are selectively provided at positions opposite to the bottom of the trench 116 in the depth direction. + Type region 121. The MOS gate of the trench gate structure consists of p-type base region 113, n-type base region 121 ... + Source region 114, p ++ The contact area 115, trench 116, gate insulating film 117, and gate electrode 118 are constituted. Additionally, in p... ++ The contact area 115 is selectively provided with p + Type 122.

[0048] Additionally, an interlayer insulating film 119 is provided on the gate electrode 118, and an opening in the interlayer insulating film 119 is provided with a portion corresponding to n. + Source region 114 and p ++ An ohmic electrode 143 is connected to the contact region 115. A barrier metal 138 is provided on the ohmic electrode 143 and the interlayer insulating film 119 to prevent metal atoms from diffusing towards the gate electrode 118. An active electrode 144 is provided on the barrier metal 138.

[0049] p + n-type regions 121 and 122 are fixed at the potential of the source electrode 144 and have the function of depleting the MOSFET (silicon carbide semiconductor device 110) when it is turned off (or depleting the n-type current diffusion region 120, or both) and mitigating the electric field applied to the gate insulating film 117. + Type 121 and type p-base 113 are disposed separately and face each other in the depth direction to the bottom surface of groove 116. + Type region 121 is locally linked to p + The type region 122 is electrically connected to the source electrode 144. Figure 14 Shows that p is not set + The cross-section of part of type 122, Figure 15 It shows that p is set +Type region 122 and p + Type 122 and p + The cross section of the part connected to section 121.

[0050] Thus, the elimination setting is related to p + p between the grooves 116 at the same depth in type region 121 + The model region is designed to unify the JFET structure of each cell (the structure of the portion where current flows between trenches 116). Furthermore, p + Type 121 and p ++ The connection between the contact areas 115 is achieved by forming a deep p in the center between the grooves 116. + This is achieved through type 122.

[0051] Therefore, the cell spacing can be shortened by simplifying the structure of each cell, and the resistance of SiC MOSFETs with low channel mobility can be reduced by shortening the cell spacing. Furthermore, the structure between trenches 116 can have slack, allowing the p-type transistors located under trenches 116 to... + The width of type region 121 is increased. By widening the flat portion of the pn junction, the electric field concentration can be mitigated, thereby improving the withstand voltage.

[0052] However, in this structure, p under trench 116 + Type 121 and p ++ p under type contact area 115 + The connection between the type regions 122 becomes thinner. Therefore, if a high voltage is applied to the drain electrode 145, causing the depletion region to expand, then p + Type 121 and p + Neutral region separation of type 122, p + When region 121 is in a floating state, there is a problem of drastic fluctuations in the feedback capacitance and an increase in SW (switching) losses due to these fluctuations. Additionally, due to the p-value of the protection trench 116... + The p-type base region 121 is electrically floated, which causes problems such as applying a high voltage to the gate insulating film 117. In addition, since the area of ​​the p-type base region 113, which is the channel region, exposed on the side of the drain electrode 145 is relatively wide, there is a problem of a decrease in breakdown voltage caused by applying a high voltage to the channel.

[0053] Hereinafter, preferred embodiments of the silicon carbide semiconductor device of this disclosure will be described in detail with reference to the accompanying drawings. In this specification and the drawings, layers or regions marked with n or p refer to those where electrons or holes are the majority carriers, respectively. Furthermore, a "+" indicating n or p indicates a higher impurity concentration than layers or regions without n or p markings, and a "-" indicating n or p indicates a lower impurity concentration than layers or regions without n or p markings. It should be noted that in the following description of the embodiments and the accompanying drawings, the same components are labeled with the same symbols, and repeated descriptions are omitted. Moreover, considering manufacturing variations, identical or equivalent descriptions may be included within 5%.

[0054] (Implementation Method 1) The structure of the silicon carbide semiconductor device of Embodiment 1 will be described. Figure 1 This is a perspective view showing the structure of the silicon carbide semiconductor device according to Embodiment 1. Figure 2A This illustrates the structure of the silicon carbide semiconductor device according to Embodiment 1. Figure 1 A-A' cross-sectional view. Figure 2B This illustrates the structure of the silicon carbide semiconductor device according to Embodiment 1. Figure 1 The B-B' cross-sectional view. Figure 2C This illustrates the structure of the silicon carbide semiconductor device according to Embodiment 1. Figure 1 The C-C' cross-sectional view. Figure 2D Other structures of the silicon carbide semiconductor device shown in Embodiment 1 are also illustrated. Figure 1 The C-C' cross-sectional view. Figure 3A This illustrates the structure of the silicon carbide semiconductor device according to Embodiment 1. Figures 2A to 2C A top-down view of depth D. Figure 3B This illustrates the structure of the silicon carbide semiconductor device according to Embodiment 1. Figures 2A to 2C Depth E top view. Figure 3C This illustrates the structure of the silicon carbide semiconductor device according to Embodiment 1. Figures 2A to 2C The depth F top view. Figure 3D This illustrates the structure of the silicon carbide semiconductor device according to Embodiment 1. Figures 2A to 2C The depth G top view. Figures 1 to 3D The silicon carbide semiconductor device 10 shown in Embodiment 1 is a vertical MOSFET formed by having a trench gate structure on a semiconductor substrate (semiconductor chip) 40 made of silicon carbide (SiC).

[0055] exist Figures 1 to 3DThe text only describes the active region where current flows in the on-state, omitting the description of the edge termination region, which is roughly rectangular and surrounded by a voltage-resistant structure. The voltage-resistant structure serves to mitigate the electric field near the boundary between the active region and the edge termination region, thus maintaining voltage withstand capability. Voltage withstand capability refers to the limiting voltage at which breakdown does not occur even if avalanche breakdown occurs at the pn junction, increasing the drain-source current.

[0056] On the semiconductor substrate 40, multiple unit cells (functional units of the element) of the same structure (element structure) of the MOSFET are arranged adjacently in a side-by-side manner. The semiconductor substrate 40 is designed to be n - Type drift region (first semiconductor layer of first conductivity type) 12 of n - Type 42 silicon carbide layer in n composed of silicon carbide + The semiconductor substrate 40 is epitaxially grown on the front side of the type-initiating substrate (a silicon carbide semiconductor substrate of the first conductivity type). - The main surface of the silicon carbide layer 42 is set as the front side (first main surface), and n + The main surface on the side of the type starting substrate 41 is set as the back side (second main surface).

[0057] n + Type-starting substrate 41 is n + Type drain region 11. In order to form the various parts of the active region, the semiconductor substrate 40 has n... + The type starting substrate 41 becomes n - Type drift region 12 of n - The silicon carbide layers are formed by sequential, multi-level epitaxial growth starting from type 42. - Type drift region 12 is n - The unformed diffusion region of the silicon carbide layer 42 due to ion implantation thus retains the residual impurity concentration from epitaxial growth. - Type drift region 12 and n + The type-starting substrate 41 is connected to and disposed from the active region to the end of the chip. - The p-type silicon carbide layer 42 can be formed through primary epitaxial growth, and the p-type base region 13 and n-type base region 13 can be formed by ion implantation. + Source region 14, p ++ Type 15 contact region, n-type current diffusion region 20, p + Type 21 and p + Type connection area 23.

[0058] In embodiment 1, a trench gate structure is provided in the active region. The trench gate structure consists of a p-type base region (a second semiconductor layer of the second conductivity type) 13, n + Type source region (first semiconductor region of the first conductivity type) 14, p ++The p-type base region 13, n-type contact region (second semiconductor region of the second conductivity type) 15, trench 16, gate insulating film 17, and gate electrode 18 constitute the structure. + Source region 14 and p ++ Type contact area 15 is through n - A diffusion region is formed by ion implantation inside the p-type silicon carbide layer 42. The p-type base region 13 is disposed on the front side of the semiconductor substrate 40 and adjacent to the n-type base region. - The entire area between drift zones 12.

[0059] n + Source region 14 and p ++ The p-type contact regions 15 are selectively disposed between the front side of the semiconductor substrate 40 and the p-type base region 13, and are in contact with the p-type base region 13 at the bottom (lower surface: the back side end of the semiconductor substrate 40). + Source region 14 and p ++ The contact area is set with 15-phase grounding. + Source region 14 and p ++ The contact area 15 is in ohmic contact with the ohmic electrode 43 on the upper surface (the front side end of the semiconductor substrate 40).

[0060] In n - Between the p-type drift region 12 and the p-type base region 13, closer to the n-type base region than the bottom surface of the trench 16. + At a depth on the side of the drain region 11 (the back side of the semiconductor substrate 40), n-type current diffusion regions 20 and p-type current diffusion regions 20 are selectively disposed, respectively. + The high-concentration region 21 of the second conductivity type is selectively provided with p-type base regions 13 on the side closer to the bottom surface of the trench 16. + n-type connection region (connection region of the second conductivity type) 23. n-type current diffusion region 20, p + Type 21 and p + Type connection region 23 is through n - The diffusion region 20 is formed by ion implantation within the n-type silicon carbide layer 42. The n-type current diffusion region 20 preferably reaches a higher density than the p-type current diffusion region. + Type 21 is closer to n + The deep position on the side of the leak zone 11.

[0061] The n-type current spreading region 20 is a so-called current spreading layer (CSL) that reduces the diffusion resistance of charge carriers. The n-type current spreading region 20 is located in the p... + Type 21 and p +The n-type connection regions 23 are connected to these regions and extend in a direction parallel to the front side of the semiconductor substrate 40 to reach the trench 16, thereby connecting to the gate insulating film 17. The upper surface of the n-type current diffusion region 20 is connected to the p-type base region 13, and the bottom of the n-type current diffusion region 20 is connected to the n-type base region 17. - Type drift region 12 is connected.

[0062] Alternatively, the n-type current diffusion region 20 can be omitted. In the absence of the n-type current diffusion region 20, [the following text is missing: "instead of the n-type current diffusion region 20, n..."] - Type drift region 12 reaches p-type base region 13 and interacts with p-type base region 13, p + Type 21 and p + The type connection area 23 is connected. Furthermore, n - The drift region 12 is in contact with the gate insulating film 17 on a portion of the sidewall of the trench 16.

[0063] p + Type 21 and p + The n-type connection region 23 is fixed at the potential of the source electrode 44 (described later) and has the function of depleting (or depleting the n-type current diffusion region 20, or both) when the MOSFET (silicon carbide semiconductor device 10) is turned off, and of mitigating the electric field applied to the gate insulating film 17. + Type 21 is separately disposed from type p base 13 and faces the bottom surface of trench 16 in the depth direction. + Type region 21 is locally linked to p + The type connection region 23 is electrically connected to the source electrode 44. Figure 2A It shows that p is set + Type connection region 23 and p + Type 21 and p + The cross-section of the part connected by type connection area 23. Figure 2B and Figure 2C It shows that p is not set. + The cross section of the type connection area 23.

[0064] p + Type region 21 can be connected to the gate insulating film 17 on the bottom surface of trench 16, or it can be separated from the bottom surface of trench 16. + The width of the shape region 21 is the same as or wider than the width of the groove 16. For example, p + The width of the shaped region 21 is preferably more than twice the width of the groove 16. By making p + The width of the shape region 21 is wider than the width of the groove 16, p + The shape 21 also faces the bottom corner (the boundary between the sidewall and the bottom surface) of the groove 16 in the depth direction. This further improves the performance of the p... +The electric field mitigation effect near the bottom surface of the trench 16 brought about by the shape region 21. For example... Figure 3C As shown, p + When viewed from above, the shaped area 21 is arranged in a striped pattern along the length of the groove 16.

[0065] like Figure 2A As shown, p + Type connection region 23 is to connect p + The region where the p-type base region 21 connects with the p-type base region 13 is formed in a region larger than the p-type base region 13. + Type region 21 is shallower (towards p-type base region 13) and deeper (n) than p-type base region 13. + The position of the starting substrate side. For example... Figure 3B As shown, p + The type-connecting region 23, when viewed from above, is arranged in a stripe pattern between the grooves 16 in a direction orthogonal to the length direction of the groove 16 (the direction of the short side of the groove 16), and connects with the groove 16. By making p + The type connection area 23 is striped between the grooves 16, p + Type connection area 23 and p under groove 16 + The increased contact area in region 21 improves pressure resistance. Additionally, as... Figure 3A As shown, p ++ The contact area 15, when viewed from above, is periodically arranged in a dotted pattern along the length of the grooves 16, and does not connect with the grooves 16. By making p ++ The contact area 15 is dot-shaped, which can improve the characteristics of the silicon carbide semiconductor device 10.

[0066] In addition, such as Figure 3A and Figure 3B As shown, p + Type connection area 23 is configured so that it does not intersect with p when viewed from above. ++ The areas where the contact areas 15 overlap are therefore periodically arranged along the length of the groove 16. Figure 2A That kind of setting has p + Type connection area 23 and no p is set ++ The area of ​​contact zone 15 Figure 2B That kind of unset p + Type connection area 23 and p ++ The area of ​​contact zone 15, and Figure 2C That kind of setting has p ++ Type contact area 15 and no p is set + The area of ​​type connection region 23.

[0067] Additionally, when viewed from above, p + The width ratio of the type connection area 23 in the direction orthogonal to the length direction of the groove 16 is p ++The width of the contact area 15 is wider in the direction orthogonal to the length direction of the groove 16. Therefore, p + Type connection area 23 and p under groove 16 + The increased contact area in the 21-type region improves pressure resistance.

[0068] Thus, by setting p under trench 16 + p-type base region 21 is shallower and deeper than p-type base region 13 + Type connection region 23, which can increase p + Type 21 and p ++ The area connected by the p-type contact region 15. This suppresses feedback capacitance fluctuations and reduces SW losses. Furthermore, since the p-type base region 13 utilizes p... + The p-type connection region 23 reduces the area exposed to the drain electrode 45 side, thus making it less likely to apply high voltage to the p-type base region 13 and improving the withstand voltage.

[0069] Thus, by setting p + Type-connection region 23 can shorten the cell spacing and achieve high breakdown voltage and low channel resistance, but the drift resistance remains unchanged. A known superjunction (SJ) structure uses a parallel pn layer where n-type and p-type pillar regions are alternately and adjacently arranged in a direction parallel to the main surface of the substrate. In the SJ structure, by making the impurity concentrations in the p-type and n-type pillar regions approximately equal, an undoped layer can be simulated in the off-state, thereby achieving high breakdown voltage.

[0070] Therefore, in implementation method 1, n - The p-type drift region 12 and the n-type current diffusion region 20 are configured as an SJ structure. This SJ structure consists of a p-type region (p-type pillar region 24) extending in a direction perpendicular to the main surface of the substrate and having a narrow width in a plane parallel to the main surface of the substrate, and an n-type region (n-type current diffusion region 20 sandwiched by the p-type pillar region 24). - The p-type drift region 12 and the n-type current diffusion region 20 (hereinafter referred to as n-type pillar regions 25) are arranged alternately in a parallel structure (hereinafter referred to as parallel pn structure 26) in a plane parallel to the main surface of the substrate. The p-type pillar regions (second pillar regions of the second conductivity type) 24 and the n-type pillar regions (first pillar regions of the first conductivity type) constituting the parallel pn structure 26 are related to the n-type current diffusion region 25. - Type 12 drift region corresponds to the region where the impurity concentration increases. Figures 1-2D In the middle, p-type column region 24 and n-type column region 25 are those that do not reach n. + The surface of the leak region 11 is configured in a Semi-SJ structure, but it can also be a p-type column region 24 and an n-type column region 25 reaching n. + Full-SJ structure on the surface of leak region 11. Figure 3DThis is a top view showing the structure of the parallel pn structure 26.

[0071] As a charge balancer for the parallel pn structure 26, the product of the width of the p-type pillar 24 and its impurity concentration (impurity mass) is almost equal to the product of the width of the n-type pillar 25 and its impurity concentration (impurity mass). Specifically, the difference between the impurity mass of the p-type pillar 24 and the n-type pillar 25 is within ±5%. Therefore, the parallel pn structure 26 can be fabricated in the off-state to simulate an undoped layer, thereby achieving high breakdown voltage and simultaneously obtaining both low on-resistance and high breakdown voltage characteristics. Thus, n... - The high concentration of impurities in drift region 12 and n - Thinning the drift region 12 can reduce the drift resistance.

[0072] As a charge balance for the parallel pn structure 26, it is preferable to be p-rich with more p-type impurities than n-type impurities. Avalanche tolerance can be improved by being p-rich. Furthermore, since the activation rate of p-type impurities in the p-type layer is low, it is easy to achieve the charge balance of the parallel pn structure 26 by pre-designing it to be p-rich.

[0073] like Figures 1-2C As shown, in Embodiment 1, the p-type column region 24 is aligned with p + The connection method of type area 21 is set in p + The lower part of type 21. Additionally, as... Figures 2A to 2C As shown, the width of the p-type column region 24 can be the same as p + The width of type 21 is the same, but type p column 24 can also be wider than p. + Type 21 is narrow. Figure 2D Showing p-type column region 24 compared to p + When the type area is narrow 21 Figure 1 The C-C' cross-sectional view. Although the details are omitted, Figure 1 A-A' section diagram and Figure 1 The B-B' section diagram is also the same. By making the p-type column region 24 more than p + The p-shaped region 21 is narrow, so even if the formation position of the p-shaped column region 24 is deviated, the upper surface of the p-shaped column region 24 is still close to the p-shaped column region 24. + The connection of type 21 can improve the tolerance to deviation from p-type column 24.

[0074] Additionally, although not shown, parallel pn structures 26 are provided throughout the chip. Therefore, parallel pn structures 26 are also provided in the edge termination region. In the edge termination region, the p-type base region 13 is not provided on the surface, and a protective ring is provided on the n-type pillar region 25 of the parallel pn structure 26 as a withstand voltage structure.

[0075] In addition, p+ The impurity concentration of the p-type connection region 23 is preferably higher than that of the p-type base region 13 and higher than that of the p-type base region 13. + The impurity concentration in region 21 is low. ++ The impurity concentration in contact area 15 is 1×10 20 / cm 3 The above, and compared to p-type base region 13, p + Type 23, p-type column area 24 and p + The impurity concentration in p-type base region 21 is high. Additionally, p-type base region 13, p... + Type connection area 23 and p + The preferred impurity concentration in region 21 is 9.0 × 10⁻⁶. 16 / cm 3 That's all. + Type connection area 23 and p + Type 21 is more preferably the same as the impurity concentration and at 1×10 18 / cm 3 The order of magnitude. The impurity concentration in p-type column region 24 is preferably on the order of magnitude of p. + Type connection area 23 and p + The impurity concentration in region 21 is the same as or higher than that in p + Type connection area 23 and p + The impurity concentration in region 21 is low, at 9.0 × 10⁻⁶. 16 / cm 3 Above and 1×10 18 / cm 3 the following.

[0076] Trench 16 extends through n along the depth direction + The source region 14 and the p-type base region 13 reach the n-type current diffusion region 20 (in the absence of the n-type current diffusion region 20, it is n... - Type drift region 12). Groove 16 can be in p + The interior of the type region 21 terminates. The trench 16 extends in a stripe-like pattern in a direction parallel to the front side of the semiconductor substrate 40, and reaches the outer periphery of the active region (not shown). A gate electrode 18 is disposed inside the trench 16, separated by a gate insulating film 17.

[0077] An interlayer insulating film 19 is disposed on the front side of the semiconductor substrate 40, specifically covering the gate electrode 18. An ohmic electrode (first electrode) 43 is disposed on the front side of the semiconductor substrate 40, on the portion exposed by the contact hole of the interlayer insulating film 19. The ohmic electrode 43 is located in the contact hole of the interlayer insulating film 19, on the front side of the semiconductor substrate 40, and is in contact with n. + Source region 14 and p ++ The contact area is a 15-ohm contact. The ohmic electrode 43 is, for example, a nickel silicide (NixSiy, where x and y are arbitrary integers) film. Instead of a nickel silicide film, n...+ Source region 14 and p ++ The surface of the contact area 15 is set as a cubic 3C-SiC structure to achieve ohmic contact.

[0078] The source electrode (first electrode) 44 is configured to cover the interlayer insulating film 19 by embedding it into a contact hole in the interlayer insulating film 19. The source electrode 44 is disposed over approximately the entire central region of the active region. Furthermore, the source electrode 44 is connected to the n-ohm electrode 43. + Source region 14, p ++ Type 15 contact region, p-type base region 13, p + Type 21 and p + Type connection area 23 electrical connection.

[0079] A barrier metal 38 can be provided on the ohmic electrode 43 and the interlayer insulating film 19 to prevent metal atoms from diffusing towards the gate electrode 18. The barrier metal 38 is, for example, made of titanium (Ti) or titanium nitride (TiN). The barrier metal 38 can be a two-layer structure of Ti and TiN with Ti on the semiconductor substrate 40 side. In this case, an active electrode 44 is provided on the barrier metal 38.

[0080] Drain electrode (second electrode) 45 is disposed on the back side of semiconductor substrate 40 (n + The entire surface of the back side of the type-starting substrate 41, with n + Type Leakage Area 11 (n) + Type 41) ohmic contact with the starting substrate, and with n + Type leakage area 11 electrical connection.

[0081] (Method for manufacturing a silicon carbide semiconductor device according to Embodiment 1) Next, the manufacturing method of the silicon carbide semiconductor device of Embodiment 1 will be described. The silicon carbide semiconductor device of Embodiment 1 is manufactured in the same manner as the silicon carbide semiconductor device of the comparative example. For example, it is manufactured as follows. First, make n - The first n of the type drift region 12 - Type silicon carbide layer in n + Type-starting substrate (n) + Epitaxial growth on the front side of type-starting wafer 41.

[0082] Next, by starting from n - The surface of the n-type drift region 12 is subjected to photolithography and ion implantation of p-type impurities to form n-type impurities. - The p-type pillar region 24 is located within the p-type drift region 12. Next, the second n-type current diffusion region 20 is formed at the lower part of this region. - Type silicon carbide layer in n - Epitaxial growth on the front side of the drift region 12. Then, through the second n...- The surface of the n-type silicon carbide layer is subjected to photolithography and ion implantation of p-type impurities to form the second n-type silicon carbide layer. - The p-type pillar region 24 is located within the p-type silicon carbide layer. Next, ion implantation of n-type impurities is performed to create a second n-type pillar region. - The lower part of the n-type current diffusion region 20 is formed by the formation of a silicon carbide layer. Here, a p-type pillar region 24 is formed by ion implantation, but it can also be formed by forming a second n-type pillar region. - The surface of the type silicon carbide layer reaches n - The trenches of the drift region 12 are formed by epitaxial growth of p-type impurities.

[0083] Next, the third n, which forms the middle of the n-type current diffusion region 20, is then... - Type n silicon carbide layer in the second n - Epitaxial growth of the p-type silicon carbide layer on the front side. Then, through photolithography and ion implantation of p-type impurities, the third n-type layer is formed. - The p-type silicon carbide layer is selectively formed. + Type 21. Next, through ion implantation of n-type impurities, the third n-type impurity is then established. - The silicon carbide layer forms the middle of the n-type current diffusion region 20.

[0084] Next, make the fourth n - A silicon carbide layer is epitaxially grown in the middle of the n-type current diffusion region 20. Then, through ion implantation of n-type impurities, the upper part of the n-type current diffusion region 20 is formed on the fourth n-type layer. - Type n silicon carbide layer. Next, make the fifth n - Type n silicon carbide layer in the fourth n - Epitaxial growth is performed on an n-type silicon carbide layer. Through the processes up to this point, the epitaxial growth on the n-type silicon carbide layer is complete. + n layers are stacked on the type-starting substrate 41 - A semiconductor substrate (semiconductor wafer) 40 of a predetermined thickness is obtained by forming a silicon carbide layer 42.

[0085] Next, through photolithography and ion implantation of p-type impurities, the fifth n-type impurity is obtained. - A p-type base region 13 is formed inside the p-type silicon carbide layer. Then, through photolithography and ion implantation of n-type impurities, a fifth n-type base region is formed. - The surface region of the type silicon carbide layer selectively forms n + Source area 14.

[0086] Next, through photolithography and ion implantation of p-type impurities, in the fourth n - The interior of the silicon carbide layer, below the surface and p + The p-type base region 13 is formed by connecting the p-type region 21 with the p-type base region 21 and having the upper surface connected with the p-type base region 13. +Type-linked region 23. Next, through photolithography and ion implantation of p-type impurities, the fifth n-type impurity is formed. - The surface region of the silicon carbide layer selectively forms p ++ Type 15 contact area.

[0087] n - The portion of the silicon carbide layer 42 that retains the impurity concentration from epitaxial growth without ion implantation becomes n. - Type 12 drift region. Next, ion implantation is performed into n - Heat treatment for impurity activation of silicon carbide layer 42. This heat treatment for impurity activation can be performed by implanting impurity ions into the first n-type silicon carbide layer each time. - Type 5n silicon carbide layer - In the case of a silicon carbide layer, this can be performed simultaneously. Next, the trench 16, the gate insulating film 17, and the gate electrode 18 are formed using conventional methods.

[0088] Next, an interlayer insulating film 19 is formed on the front side of the semiconductor substrate 40. Then, a source electrode 44, a gate pad (not shown), a passivation film (surface protection film: not shown), and a drain electrode 45 are formed using conventional methods. The portion of the source electrode 44 exposed at the opening of the passivation film becomes the source pad. Subsequently, the semiconductor wafer is diced and monolithically assembled into individual chips, thus completing the process. Figures 1 to 3D 10. Silicon carbide semiconductor device.

[0089] As explained above, in the silicon carbide semiconductor device according to Embodiment 1, a p-value is provided below the trench. + p-type base region is shallower and deeper than p-type base region + Type-connected region. Therefore, it is possible to increase the p... + Type region and p ++ The area of ​​the p-type contact region can suppress feedback capacitance fluctuations, thereby reducing SW losses. Furthermore, because the p-type base region utilizes p... + The p-type connection region reduces the area exposed to the drain electrode side, thus making it less likely to apply high voltage to the p-type base region and improving the withstand voltage. Additionally, the p-type connection region under the trench... + Below the type region, a pn parallel region forming an SJ structure is formed. Therefore, n... - The type-type drift region achieves high concentration of impurities and can achieve n - Thinning the thickness of the drift region can reduce the drift resistance.

[0090] For the silicon carbide semiconductor device of Embodiment 1, the on-resistance was simulated by changing the cell spacing. Figure 17 This is a characteristic diagram illustrating the relationship between the cell spacing and on-resistance of the silicon carbide semiconductor device in Embodiment 1. Figure 17 In this study, the impurity concentrations in p-type column region 24 and n-type column region 25 were set to 9.5 × 10⁻⁶. 16 / cm 3 The depths of the p-type pillar 24 and n-type pillar 25 were set to 1.5 μm. The periodic repetition spacing (equivalent to the cell spacing) of the p-type pillar 24 and n-type pillar 25 was varied from 1.6 μm to 2.6 μm to investigate the on-resistance (RonA). The threshold voltage (Vth) was 4 V. A resistance of 2.54 mΩcm was obtained when the cell spacing was 1.8 μm to 2.2 μm. 2 ~2.56mΩcm 2 It exhibits good on-resistance. In any of the above cases, a withstand voltage of over 1500V is achieved, which is sufficient for a component with a withstand voltage rating of 1200V.

[0091] (Implementation Method 2) Next, the structure of the silicon carbide semiconductor device of Embodiment 2 will be described. Figure 4 This is a perspective view showing the structure of the silicon carbide semiconductor device according to Embodiment 2. Figure 5 This illustrates the structure of the silicon carbide semiconductor device according to Embodiment 2. Figure 4 A-A' cross-sectional view. Figure 6 This illustrates the structure of the silicon carbide semiconductor device according to Embodiment 2. Figure 5 The top view of B-B'.

[0092] The difference between the silicon carbide semiconductor device 10 of Embodiment 2 and the silicon carbide semiconductor device 10 of Embodiment 1 is that the p-type pillar region 24 is aligned with the p-type pillar region 24. + The connection method of type connection area 23 is set in p + The lower part of the type connection area 23. Additionally, as... Figure 4 As shown, the p-type column region 24 has the same characteristics as p + The width of the p-type connection area 23 is the same as that of the groove 16 in the depth direction, but the p-type column area 24 can also be larger than the p-type column area 23. + Type connection area 23 is narrow.

[0093] Additionally, due to the setting of p + The position of the p-type connection area 23 does not form a channel, therefore, by setting the p-type column area 24 in the p... + The lower part of the p-type connection region 23 is such that the p-type pillar region 24 does not become a resistor, thus reducing the JFET resistance (diffusion resistance).

[0094] As explained above, the silicon carbide semiconductor device according to Embodiment 2 is configured in the same way as in Embodiment 1, with p... +Type-type connection region. Therefore, similar to Embodiment 1, it is possible to suppress feedback capacitance fluctuations, reduce SW losses, and improve withstand voltage. In Embodiment 2, in p... + Below the type-connecting region, a pn parallel region forming an SJ structure is formed. Thus, similar to embodiment 1, n... - The type-type drift region achieves high concentration of impurities and can achieve n - Thinning the thickness of the drift region can reduce drift resistance.

[0095] (Implementation Method 3) Next, the structure of the silicon carbide semiconductor device of Embodiment 3 will be described. Figure 7 This is a perspective view showing the structure of the silicon carbide semiconductor device according to Embodiment 3. Figure 8 This illustrates the structure of the silicon carbide semiconductor device according to Embodiment 3. Figure 7 A-A' cross-sectional view. Figure 9 This illustrates the structure of the silicon carbide semiconductor device according to Embodiment 3. Figure 8 The top view of B-B'.

[0096] The difference between the silicon carbide semiconductor device 10 of Embodiment 3 and the silicon carbide semiconductor device 10 of Embodiment 1 is that the p-type pillar region 24 is aligned with the p-type pillar region 10. ++ The contact area 15 is connected in a manner set in p ++ The lower part of the contact area 15. Additionally, as... Figure 7 and Figure 8 As shown, the p-type column region 24 is more p than p ++ The contact area is narrow (15mm), but it can also make p... ++ The contact area 15 narrows, thus making the p-type column area 24 become connected with the p-type column area. ++ The contact area of ​​type 15 has the same width.

[0097] like Figure 7 As shown, p ++ The p-type contact areas 15 are distributed dispersedly along the depth direction of the trench 16. Therefore, the p-type pillar areas 24 are also distributed dispersedly along the depth direction of the trench 16. This shortens the current path and improves avalanche tolerance.

[0098] As explained above, the silicon carbide semiconductor device according to Embodiment 3 is configured in the same way as in Embodiment 1, with p... + Type-type connection region. Therefore, similar to Embodiment 1, it is possible to suppress feedback capacitance fluctuations, reduce SW losses, and thereby improve withstand voltage. In Embodiment 3, in p... ++ A pn parallel region forming an SJ structure is formed beneath the contact region. Thus, similar to Embodiment 1, n... -The type-type drift region achieves high concentration of impurities and can achieve n - Thinning the thickness of the drift region can reduce the drift resistance.

[0099] (Implementation Method 4) Next, the structure of the silicon carbide semiconductor device of Embodiment 4 will be described. Figure 10 This is a perspective view showing the structure of the silicon carbide semiconductor device according to Embodiment 4. Figure 11 This illustrates the structure of the silicon carbide semiconductor device according to Embodiment 4. Figure 10 A-A' cross-sectional view. Figure 12 This illustrates the structure of the silicon carbide semiconductor device according to Embodiment 4. Figure 10 The B-B' cross-sectional view. Figure 13 This illustrates the structure of the silicon carbide semiconductor device according to Embodiment 4. Figure 11 and Figure 12 The top view of C-C'.

[0100] The difference between the silicon carbide semiconductor device 10 of Embodiment 4 and the silicon carbide semiconductor device 10 of Embodiment 1 is that the p-type pillar region 24 is connected to the p-type pillar region under the trench. + Type 21 and p + The connection area 23 is set in the groove under p in a way that the two types of connection areas are connected. + Type 21 and p + The lower part of the type connection area 23. Additionally, as... Figure 10 and Figure 12 As shown, the p-type column region 24 has the same characteristics as p + The width of type 21 is the same, but type p column 24 can also be wider than p. + Type 21 is narrow. Additionally, as... Figure 10 As shown, the p-type column region 24 has the same characteristics as p + The width of the p-type connection area 23 is the same as that of the groove 16 in the depth direction, but the p-type column area 24 can also be larger than the p-type column area 23. + Type connection area 23 is narrow.

[0101] In implementation method 4, such as Figure 13 As shown, the n-type column region 25 is surrounded by the p-type column region 24. Therefore, the impurity concentration of the p-type column region 24 can be increased, and the impurity concentration of the n-type column region 25 can also be increased. As a result, the resistance of the pn parallel region 26 is reduced, and the effect of the SJ structure can be improved compared with embodiments 1 to 3.

[0102] As explained above, the silicon carbide semiconductor device according to Embodiment 4 is configured in the same way as in Embodiment 1, with p... +The p-type connection region. Therefore, similar to Embodiment 1, it is possible to suppress feedback capacitance fluctuations, reduce SW losses, and improve withstand voltage. In Embodiment 4, the p-type column region in p... + Type region and p + Below the type-connecting region, a pn parallel region forming an SJ structure is formed. Thus, similar to embodiment 1, n... - The type-type drift region achieves high concentration of impurities and can achieve n - Thinning the drift region can reduce drift resistance.

[0103] In implementation method 4, at p + Type 21 and p + A pn parallel region 26 is formed below the type-connecting region 23, but other combinations are also possible. For example, it can be formed in p ++ Type contact area 15 and p + A pn parallel region 26 is formed below the type connection region 23, or it can be formed in p ++ Type contact area 15 and p + Below type region 21, pn parallel region 26 is formed, and p can also be formed. ++ Type contact area 15, p + Type connection area 23 and p + Below type region 21, pn parallel region 26 is formed.

[0104] As described above, various modifications can be made to the present invention without departing from its spirit. In each of the above embodiments, for example, the dimensions of each part, impurity concentration, etc., are set according to the required specifications. Furthermore, while the above embodiments have been described using a MOSFET with a trench structure as an example, they can also be applied to other semiconductor devices with trench structures, IGBTs, etc.

[0105] Industrial availability As shown above, the silicon carbide semiconductor device disclosed herein is useful for power semiconductor devices used in power conversion devices such as converters, power supply devices for various industrial machinery, ignition systems for automobiles, and the like.

Claims

1. A silicon carbide semiconductor device, characterized in that, have: Silicon carbide semiconductor substrate of the first conductivity type; A first semiconductor layer of a first conductivity type is disposed on the front side of the silicon carbide semiconductor substrate, and the impurity concentration is lower than that of the silicon carbide semiconductor substrate. The parallel pn region is located on the surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate side, in which a first pillar region of a first conductivity type and a second pillar region of a second conductivity type are repeatedly and alternately arranged on a surface parallel to the front side. A second semiconductor layer of a second conductivity type is disposed on the surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate side; A first semiconductor region of a first conductivity type is selectively disposed on the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side; A second semiconductor region of a second conductivity type is selectively disposed on the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side, in a manner that is in contact with the first semiconductor region and the second semiconductor layer. A trench that penetrates the first semiconductor region and the second semiconductor layer to reach the first semiconductor layer; A gate electrode is disposed inside the trench, separated by a gate insulating film; The high-concentration region of the second conductivity type is disposed inside the first semiconductor layer at a position opposite to the trench along the depth direction; The second conductivity type connection region is located inside the first semiconductor layer, and is selectively disposed at a position that is closer to the second semiconductor layer than the high concentration region and closer to the silicon carbide semiconductor substrate than the second semiconductor layer, in a manner that connects to the high concentration region and the second semiconductor layer. A first electrode is disposed on the surfaces of the first semiconductor region and the second semiconductor region; as well as The second electrode is disposed on the back side of the silicon carbide semiconductor substrate. The second semiconductor region is periodically arranged along the length direction of the trench. The connection region is periodically arranged along the length of the trench in an area that does not overlap with the second semiconductor region when viewed from above.

2. The silicon carbide semiconductor device according to claim 1, characterized in that, The second pillar region is in contact with the surface of the silicon carbide semiconductor substrate side of the high concentration region, and is disposed on the silicon carbide semiconductor substrate side of the high concentration region.

3. The silicon carbide semiconductor device according to claim 1, characterized in that, The second pillar region is in contact with the surface of the silicon carbide semiconductor substrate side of the connection region, and is disposed on the silicon carbide semiconductor substrate side of the connection region.

4. The silicon carbide semiconductor device according to claim 1, characterized in that, The second pillar region is in contact with the surface of the silicon carbide semiconductor substrate side of the second semiconductor region, and is disposed on the silicon carbide semiconductor substrate side of the second semiconductor region.

5. The silicon carbide semiconductor device according to claim 1, characterized in that, The second pillar region is in contact with the surface of the silicon carbide semiconductor substrate side of the high concentration region and the connection region, and is disposed on the silicon carbide semiconductor substrate side of the high concentration region and the connection region.

6. The silicon carbide semiconductor device according to any one of claims 2 to 5, characterized in that, The width of the second pillar region is the same as the width of the region where the second pillar region meets the surface on the opposite side of the silicon carbide semiconductor substrate.

7. The silicon carbide semiconductor device according to any one of claims 2 to 5, characterized in that, The width of the second pillar region is narrower than the width of the region where the second pillar region meets the surface on the opposite side of the silicon carbide semiconductor substrate.

8. The silicon carbide semiconductor device according to claim 1, characterized in that, The periodic repetition interval between the first column region and the second column region is 1.8 μm to 2.2 μm.

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