Hardware performance monitor and hardware performance monitoring method

Abstract

The invention provides a hardware performance monitor and a hardware performance monitoring method.The hardware performance monitor comprises 31 M-bit full adders, an N-bit full adder and a 31-bit cyclic shift register; the 31 M-bit full adders are respectively used for carrying out accumulative counting on the events corresponding to the M-bit full adders; the 31-bit cyclic shift register is used for polling overflow bits of the 31 M-bit full adders and sending a polling result to one N-bit full adder, and each bit of the 31-bit cyclic shift register is in one-to-one correspondence with the 31 M-bit full adders; and the N-bit full adder is used for performing accumulation operation on the received overflow values of the overflow bits of the 31 M-bit full adders and the count values of the corresponding M-bit full adders to obtain an accumulated value. By utilizing the technical scheme provided by the embodiment of the invention, the technical effects of reducing power consumption and cost can be achieved while the performance of the PMU is improved.

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