Modular multilevel converter real-time simulation method based on FPGA

Abstract

The application belongs to the technical field of electromagnetic transient real-time simulation, and particularly relates to a modular multilevel converter real-time simulation method based on FPGA, which comprises the following steps: calculating the total number of input sub-modules and the total input voltage through bridge arm current, sub-module capacitor voltage and switching state signal; obtaining instantaneous impedance according to the total number of input sub-modules; obtaining current change rate according to the bridge arm current, combining the characteristic impedance and the instantaneous impedance to generate a mismatch sensitive factor; obtaining dynamic compensation admittance according to the total input voltage, the rated voltage, the reference voltage and the mismatch sensitive factor combined with the maximum compensation conductance; superimposing the characteristic conductance obtained according to the characteristic impedance, the equivalent conductance obtained according to the physical inductance value and the dynamic compensation admittance to obtain node admittance; generating node current according to the Norton equivalent current and historical current component, combining the node admittance to obtain node voltage to complete closed-loop iteration. The application improves the real-time performance and numerical stability of simulation results.

Description

Technical Field

[0001] This invention relates to the field of electromagnetic transient real-time simulation technology. More specifically, this invention relates to a real-time simulation method for modular multilevel converters based on FPGA. Background Technology

[0002] In the field of power system digital twins and hardware-in-the-loop simulation, the Modular Multilevel Converter (MMC) has become a core component of flexible DC transmission due to its high-voltage and high-capacity characteristics. This converter comprises hundreds of cascaded sub-modules, and its electromagnetic transient simulation requires real-time calculation of a massive switching state matrix within microsecond-level steps. To meet these real-time requirements, existing technologies typically employ Field Programmable Gate Arrays (FPGAs) to construct a parallel pipeline architecture and introduce a transmission line model based on the traveling wave principle to solve for the electrical quantities at the converter-grid interface.

[0003] Traditional transmission line models use a preset fixed characteristic impedance, which is set based on the average inductance and capacitance values ​​under the rated operating conditions of the system and remains unchanged throughout the entire simulation cycle.

[0004] However, the equivalent capacitance of the arms of a modular multilevel converter changes dynamically with the number of submodules added, causing the physical topology impedance of the arms to change dynamically. A fixed characteristic impedance cannot track this change, leading to a continuous mismatch between the simulation model parameters and the actual physical state, and generating non-physical numerical reflections at the transmission line computation nodes. Field-programmable gate arrays (FPGAs) use a fixed-step discretization algorithm for simulation calculations. The reflected wave energy, constrained by the step size, cannot be effectively dissipated within a single step, accumulating to form high-frequency numerical noise, manifesting as sawtooth oscillations or spurious spikes in the node voltage, thus compromising the realism and stability of the simulation waveform. Existing technologies lack real-time sensing capabilities and adaptive compensation mechanisms for dynamic changes in the arm topology impedance, making it difficult to suppress numerical oscillations while preserving the true physical dynamic characteristics, thus compromising both simulation accuracy and numerical stability. Summary of the Invention

[0005] To address the numerical oscillations and simulation distortions caused by the mismatch between fixed characteristic impedance and time-varying topological impedance in existing technologies, this invention provides a real-time simulation method for modular multilevel converters based on FPGA. The method includes: reading the converter arm current, the capacitor voltage of each submodule, and the switching status signals using a parallel interface; obtaining the total number of submodules in operation at the current moment based on the switching status signals of each submodule, and obtaining the total in operation voltage at the current moment by combining the corresponding submodule capacitor voltages; obtaining the instantaneous impedance based on the total number of in operation submodules and preset nominal capacitance, physical inductance, and virtual inductance values ​​of the submodules; and obtaining the current variation at the current moment based on the difference between the converter arm current at the current moment and the previous moment, combined with the simulation step size. The simulation process involves: obtaining a mismatch sensitivity factor based on instantaneous impedance, current change rate, and a preset characteristic impedance; modulating the preset maximum compensation conductance to generate dynamic compensation admittance based on the sum of input voltages, a preset reference voltage, and rated voltage, combined with the mismatch sensitivity factor; obtaining the characteristic conductance by taking the reciprocal of the characteristic impedance; obtaining the equivalent conductance based on the physical inductance, virtual inductance, and simulation step size; obtaining the node admittance based on the characteristic conductance, equivalent conductance, and dynamic compensation admittance; obtaining the Norton equivalent current based on the total number of input submodules, nominal capacitance, sum of input voltages, and bridge arm current, and generating node currents by combining historical current components obtained through the transmission line model; obtaining node voltages based on node currents and node admittances; and completing closed-loop real-time simulation iterations based on node voltages.

[0006] This invention utilizes FPGA pipeline preprocessing technology and adder tree structure to synchronously read the converter arm current and the switching status signals of each submodule at the trigger moment of the simulation step, avoiding the communication delay when general-purpose processors process large-scale matrices and maintaining the microsecond-level simulation step size of modular multilevel converters in large-scale topologies; by calculating the instantaneous impedance using the physical definition of characteristic impedance, and combining the time-varying total number of engaged submodules with the virtual inductance, it measures the physical inertia of the converter arm to voltage fluctuations, correcting the parameter jump error caused by fixed parameters in traditional transmission line models; furthermore, this invention... By combining instantaneous impedance and current change rate to calculate the mismatch sensitivity factor, the risk of numerical oscillation when the characteristic impedance and instantaneous impedance are mismatched is identified using the voltage reflection coefficient principle. By constructing dynamic compensation admittance to modulate the maximum compensation conductance, the numerical damping is adaptively adjusted using the mismatch sensitivity factor, which dissipates the energy of numerical oscillations in a directional manner while attenuating the intervention on real physical faults and preserving the real waveform characteristics. By introducing dynamic compensation admittance and using the trapezoidal integral algorithm to update the node voltage, the linkage between the port voltage and the submodule capacitor state is established, eliminating the time lag of numerical calculation and maintaining the energy conservation of the simulation model.

[0007] Preferably, the step of obtaining the total number of sub-modules in operation at the current moment based on the switching status signals of each sub-module, and obtaining the total input voltage at the current moment by combining the corresponding sub-module capacitor voltage, includes: performing parallel statistics on the switching status signals of each sub-module using an adder tree structure to calculate the total number of sub-modules in operation at the current moment; using the switching status signals of each sub-module as numerical weights, performing multiplication with the corresponding sub-module capacitor voltage to obtain input voltage components; and performing parallel accumulation on the input voltage components of all sub-modules using an adder tree structure to calculate the total input voltage at the current moment.

[0008] Preferably, the instantaneous impedance satisfies the following relationship:

[0009] ;

[0010] In the formula, Let be the instantaneous impedance at time t; This is the physical inductance value; For virtual inductance; The nominal capacitor for the submodule; Let be the total number of sub-modules deployed at time t.

[0011] This invention utilizes the physical definition of characteristic impedance combined with the total number of input sub-modules and virtual inductance to calculate instantaneous impedance, characterizing the equivalent controlled source characteristics of modular multilevel converter arms during topology switching, measuring the physical inertia of converter arms to voltage fluctuations, providing a benchmark for evaluating the degree of parameter jumps at discretized nodes, and reducing the risk of computational energy accumulation caused by fixed parameters.

[0012] Preferably, the mismatch sensitivity factor satisfies the following relationship:

[0013] ;

[0014] In the formula, Let be the mismatch sensitivity factor at time t; Characteristic impedance; Let be the instantaneous impedance at time t; The rate of change weighting coefficient; Let be the rate of change of current at time t.

[0015] This invention combines instantaneous impedance and current change rate and uses the voltage reflection coefficient principle to calculate the mismatch sensitivity factor, characterizing the degree of mismatch between the characteristic impedance under a fixed step size and the time-varying instantaneous impedance, measuring the numerical stability risk of the transmission line port when the converter arm current changes drastically, providing a basis for triggering damping intervention under transient operating conditions, and reducing high-frequency oscillations caused by sudden changes in physical impedance.

[0016] Preferably, the dynamic compensation admittance satisfies the following relationship:

[0017] ;

[0018] In the formula, The dynamic compensation admittance at time t; To maximize the compensation conductivity; The saturation coefficient; This represents the total applied voltage at time t; Reference voltage; Rated voltage; Let be the mismatch sensitivity factor at time t.

[0019] This invention obtains dynamic compensation admittance by modulating the maximum compensation conductance using a mismatch sensitivity factor based on the deviation of the sum of input voltages from the reference voltage. This characterizes the numerical dissipation capability used to suppress non-physical overshoot, measures the required numerical damping strength under different simulation conditions, provides an algorithmic implementation for constructing a numerical damping channel for directional dissipation of numerical oscillation energy, and reduces the distortion of real fault characteristics caused by fixed damping parameters.

[0020] Preferably, the node voltage satisfies the following relationship:

[0021] ;

[0022] In the formula, Let be the node voltage at time t; Let be the Norton equivalent current at time t; Characteristic conductivity; Let be the equivalent conductance at time t; The historical current component at time t; Let be the dynamic compensation admittance at time t.

[0023] This invention incorporates dynamic compensation admittance into node admittance and uses the node voltage method to calculate node voltage, characterizing the port potential of the converter arm under dynamic damping. It measures the degree to which dynamic compensation admittance weakens non-physical voltage spikes caused by discretization errors, providing numerical basis for synchronously updating submodule capacitor voltages using the trapezoidal integral algorithm, and reducing the simulation divergence risk caused by inconsistency between port voltage and internal energy storage state.

[0024] Preferably, the step of obtaining the current change rate at the current moment based on the difference between the converter arm current at the current moment and the previous moment, combined with the simulation step size, includes: dividing the absolute value of the difference between the converter arm current at the current moment and the converter arm current at the previous moment by the simulation step size to obtain the current change rate at the current moment.

[0025] Preferably, obtaining the equivalent conductance based on the physical inductance value, virtual inductance, and simulation step size includes: obtaining the equivalent conductance of the converter arm at the current moment using a trapezoidal integral discretization algorithm based on the converter's physical inductance value, virtual inductance, and simulation step size.

[0026] Preferably, the step of obtaining the Norton equivalent current based on the total number of sub-modules in operation, nominal capacitance, total input voltage, and bridge arm current includes: calculating the Norton equivalent current inside the converter using the trapezoidal integral method based on the total number of sub-modules in operation at the current moment, the total input voltage at the previous moment, the bridge arm current at the previous moment, and the nominal capacitance of the sub-modules.

[0027] Preferably, the step of generating node current from historical current components obtained through the transmission line model includes: receiving the incident wave voltage transmitted from the peer converter at the previous moment using the optical fiber interface, and calculating the historical current components using the Bergeron transmission line model.

[0028] The beneficial effects of this invention are as follows: By configuring FPGA pipeline preprocessing technology and adder tree structure, this invention achieves parallel acquisition of the total number of large-scale input sub-modules and the sum of input voltages, suppressing the accumulation of discretization errors under long step sizes and maintaining the real-time performance of simulation results; by calculating the instantaneous impedance characterizing the energy storage change characteristics of the bridge arm, a dynamic parameter reflecting the real-time switching of the topology is established to measure the voltage support under the physical inductance value and capacitor series state, providing a benchmark for numerical damping adjustment; by calculating the mismatch sensitivity factor and fusing the voltage reflection coefficient and current change rate, transient risks caused by the mismatch between fixed step size and time-varying instantaneous impedance are identified, making up for the shortcomings of judging solely based on static characteristic impedance; on this basis, this invention constructs an adaptive numerical damping channel by generating dynamic compensation admittance, automatically adjusting the weight of the maximum compensation conductance according to the degree of voltage deviation, thereby suppressing non-physical numerical noise and preserving large-signal fault characteristics; by using the trapezoidal integral algorithm and dynamic compensation admittance to solve the node voltage, the timing consistency between the port voltage and the internal energy storage state is maintained, preventing simulation divergence caused by energy drift. Attached Figure Description

[0029] Figure 1 This is a flowchart of a real-time simulation method for a modular multilevel converter based on FPGA;

[0030] Figure 2 This is a comparison of the node voltage simulation waveforms of the traditional fixed impedance method and the dynamic compensation method of this invention. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0033] This invention discloses a real-time simulation method for a modular multilevel converter based on FPGA, referring to... Figure 1 This includes steps S1 to S5:

[0034] S1. Obtain real-time status data of the converter, and use FPGA pipeline preprocessing technology to calculate the total number of sub-modules in operation and the total voltage in operation at the current moment.

[0035] It should be noted that in the real-time simulation of modular multilevel converters, the number of sub-modules is large and the switching frequency is high. If a traditional general-purpose processor architecture is used to process a large-scale node matrix, the general-purpose processor architecture will produce serious computation and communication delays. When the simulation step size exceeds the preset proportion of the switching cycle, the discretization error will continue to accumulate, causing numerical instability and resulting in distortion of the simulation waveform. Therefore, this invention utilizes the parallel characteristics of FPGA hardware to construct an adder tree structure to complete the aggregation of multiple data streams within a single clock cycle, ensuring that a microsecond-level simulation step size is maintained under large-scale sub-module conditions, thereby guaranteeing the real-time performance of the simulation results.

[0036] Specifically, the FPGA operating clock frequency and simulation step size are configured; the total number of bridge arm submodules, nominal capacitance of submodules, reference voltage, rated voltage, physical inductance value, virtual inductance, and characteristic impedance are pre-configured into the FPGA registers as static topology parameters; at the trigger time of the simulation step size, the real-time converter bridge arm current is synchronously read using the parallel interface; the real-time capacitor voltage of each submodule is read using the parallel interface; the real-time switching status signals of each submodule are read using the parallel interface, where the submodule switching status signal is 1 for the engaged state and 0 for the disengaged state; pipeline preprocessing is used to perform timing synchronization processing on the converter bridge arm current; the adder tree structure is used to perform parallel statistics on the switching status signals of each submodule to calculate the total number of engaged submodules at the current time; the switching status signals of each submodule are used as numerical weights and multiplied with the corresponding submodule capacitor voltage to obtain the engaged voltage component; the engaged voltage components of all submodules are accumulated in parallel using the adder tree structure to calculate the total engaged voltage at the current time.

[0037] It should be added that adder trees are a commonly used parallel computing structure in FPGA hardware logic. Through multiple cascaded adders, they can perform parallel summation of large-scale data in a very short number of clock cycles. In this invention, this structure is used to synchronously count the switching states and voltages of hundreds of sub-modules, forming the core hardware foundation for ensuring real-time performance. Pipeline preprocessing refers to breaking down complex computational tasks into multiple consecutive stages at the hardware level, allowing data processing in different steps to overlap within the same clock cycle. This type of technique effectively avoids instruction queuing latency in general-purpose processors, ensuring that the simulation step size remains stable at the microsecond level.

[0038] In this embodiment, the FPGA operating clock frequency is set to 100MHz, and the simulation step size is set to 1 microsecond. According to the initial configuration, the total number of bridge arm submodules is set to 200, the nominal capacitance of the submodule is 5mF, the physical inductance is 50mH, and the reference voltage and rated voltage are both set to 200kV. The implementer can adjust the above static topology parameters according to the actual topology scale of the converter.

[0039] In this embodiment, the virtual inductance coefficient determines the numerical calculation stability when the bridge arm current crosses zero, and the empirical range is [1%, 5%]. The virtual inductance coefficient is set to 2% of the physical inductance value. In other embodiments, the implementer can adjust the virtual inductance coefficient according to the numerical oscillation amplitude of the simulated current. For example, when there is significant numerical jitter in the bridge arm current, the virtual inductance coefficient can be appropriately increased to enhance the filtering effect; when high-precision current tracking performance is required and the system is relatively stable, the virtual inductance coefficient can be appropriately decreased.

[0040] In this embodiment, the characteristic impedance determines the reference coupling ratio between the voltage traveling wave and the current traveling wave in the transmission line model, with an empirical range of [20, 50], and the characteristic impedance is set to 32Ω. In other embodiments, the implementer can adjust the characteristic impedance according to the rated electromagnetic parameters of the converter arm. For example, when the physical inductance of the arm is large, resulting in a limited rate of change of current, the characteristic impedance can be appropriately increased to match the high inductive characteristic; when the submodule capacitance is large, resulting in strong voltage support stiffness, the characteristic impedance can be appropriately decreased to match the high capacitive characteristic.

[0041] S2. Based on the total number of sub-modules, calculate the instantaneous impedance characterizing the energy storage change characteristics of the bridge arm using the physical definition of characteristic impedance.

[0042] It should be noted that the equivalent controlled source characteristics of the modular multilevel converter arm change in real time with the number of submodules added. Traditional transmission line models use fixed parameters, which cannot adapt to parameter jumps caused by topology changes, resulting in non-physical accumulation of computational energy at discretized nodes. Therefore, this invention measures the physical inertia of the converter arm to voltage fluctuations by calculating instantaneous impedance, providing a benchmark for subsequent numerical damping adjustment.

[0043] Specifically, the instantaneous impedance at the current moment is obtained by substituting the total number of sub-modules currently in operation with the preset nominal capacitance, physical inductance, and virtual inductance values ​​of the sub-modules into the characteristic impedance standard definition.

[0044] It should be added that this invention follows the standard physical definition of the characteristic impedance of a lossless transmission line in electromagnetic field and circuit theory, and the characteristic impedance satisfies the expression ,in Characteristic impedance, The equivalent inductance of the circuit, This is the equivalent capacitance of the circuit. In a modular multilevel converter (MMC) arm, when When multiple submodules are connected in series, according to the series capacitance law, the equivalent capacitance of the circuit satisfies... ,in The equivalent capacitance of the circuit. Submodule nominal capacitor, This represents the total number of sub-modules involved.

[0045] Specifically, the instantaneous impedance satisfies the expression:

[0046] ;

[0047] In the formula, Let be the instantaneous impedance at time t; This is the physical inductance value; For virtual inductance; The nominal capacitor for the submodule; Let be the total number of sub-modules deployed at time t.

[0048] in, The larger the value, the smaller the total equivalent capacitance of the converter arm according to the capacitor series law, resulting in a lower instantaneous impedance. The larger the value, the higher the rate of voltage change caused by unit current, and the more sensitive the voltage logarithmic disturbance of the converter arm at time t becomes, making the simulation model more prone to voltage fluctuations. The smaller the value, the larger the total equivalent capacitance of the converter arm according to the capacitor series law, resulting in a larger instantaneous impedance. The smaller the value, the stronger the voltage support stiffness, which can more effectively suppress voltage distortion caused by externally injected current, allowing the simulation model to maintain waveform stability under low impedance conditions.

[0049] In addition, the introduction of virtual inductance is a well-known numerical stabilization technique in the field of electromagnetic transient simulation, which aims to avoid numerical errors in the instantaneous impedance calculation when the number of sub-modules in the bridge arm approaches zero.

[0050] S3. Combining instantaneous impedance and current change rate, and using the voltage reflection coefficient principle, calculate the mismatch sensitivity factor that characterizes the numerical stability risk.

[0051] It should be noted that the oscillation risk in numerical simulation mainly stems from the parameter mismatch between the discretized characteristic impedance under a fixed step size and the time-varying instantaneous impedance. When the converter topology undergoes a drastic switch, the sudden change in physical impedance can cause strong numerical reflections at the transmission line ports, leading to non-physical high-frequency oscillations. Judging solely based on static impedance differences is insufficient to capture the transient risks during drastic current changes. This invention generates a mismatch sensitivity factor characterizing the degree of damage to numerical stability, thereby triggering damping intervention under transient conditions.

[0052] Specifically, the current change rate at the current moment is obtained by dividing the absolute value of the difference between the converter arm current at the current moment and the converter arm current at the previous moment by the simulation step size; the characteristic impedance of the converter arm and the instantaneous impedance at the current moment are substituted into the lossless transmission line voltage reflection coefficient in the standard electromagnetic field and circuit theory, and weighted and fused together with the current change rate to generate the mismatch sensitivity factor.

[0053] It should be added that this invention follows the standard physical definition of the voltage reflection coefficient of a lossless transmission line in electromagnetic field and circuit theory, and the voltage reflection coefficient satisfies the expression... ,in Voltage reflection coefficient, For load impedance, Let be the incident wave impedance. The square of the reflection coefficient represents the proportion of reflected energy to incident energy. In the real-time simulation calculation node of a modular multilevel converter, the instantaneous impedance physically corresponds to the load impedance at the end of the transmission line, while the characteristic impedance of the converter arm physically corresponds to the incident wave impedance of the wave propagation medium.

[0054] Specifically, the mismatch sensitivity factor satisfies the expression:

[0055] ;

[0056] In the formula, Let be the mismatch sensitivity factor at time t; Characteristic impedance; Let be the instantaneous impedance at time t; The rate of change weighting coefficient; Let be the rate of change of current at time t.

[0057] In this embodiment, the rate of change weighting coefficient determines the sensitivity of the mismatch sensitivity factor to transient changes in current. The empirical range is [0.0005, 0.005]. In this embodiment, the rate of change weighting coefficient is set to 0.001 s / A. In other embodiments, the implementer can adjust the rate of change weighting coefficient according to the signal-to-noise ratio of the current sampling. For example, when the current sampling noise is high, the rate of change weighting coefficient can be appropriately reduced to prevent false triggering; when the fault current rises extremely rapidly and a fast response is required, the rate of change weighting coefficient can be appropriately increased.

[0058] in, To obtain the voltage reflection coefficient term by substituting the characteristic impedance and instantaneous impedance into the standard voltage reflection coefficient, The closer the value is to 1, the greater the deviation between the characteristic impedance and the instantaneous impedance, and the higher the risk of energy imbalance during numerical calculation, thus increasing the mismatch sensitivity factor. The numerical value increases, thereby driving the subsequent compensation admittance value to increase, which suppresses potential numerical oscillations; The closer the value is to 0, the higher the degree of matching between the characteristic impedance and the instantaneous impedance, and the lower the mismatch sensitivity factor. The numerical value is reduced, thereby minimizing unnecessary numerical interventions and ensuring the accuracy of steady-state calculations.

[0059] The larger the value, the more likely the converter arm current is to be in a transient process of drastic changes, the faster the current changes, and the easier it is for numerical calculations to produce overshoot. The higher the value, the greater the mismatch sensitivity factor. The values ​​are further amplified, thereby increasing the system's sensitivity to mismatch risk during transient processes. The smaller the value, the more likely the converter arm current is to be in a steady-state or low-frequency variation region. The smaller the value, the lower the mismatch sensitivity factor. The more likely it is to remain at the baseline level determined by the static mismatch component, the better to prevent miscompensation caused by sampling noise.

[0060] S4. Based on the degree of voltage deviation, the maximum compensation conductance is modulated using the mismatch sensitivity factor to generate a dynamic compensation admittance for dissipating numerical oscillation energy.

[0061] It should be noted that impedance mismatch can induce non-physical numerical overshoot and high-frequency oscillations at transmission line nodes. If fixed damping parameters are used to suppress these, the actual large-signal fault characteristics may be incorrectly smoothed out while eliminating numerical noise, leading to a decrease in the physical fidelity of the simulation model under transient conditions. Therefore, this invention constructs a dynamic compensation admittance constrained by the degree of voltage deviation to form an adaptive numerical damping channel. This channel dissipates numerical oscillation energy in a directional manner while ensuring automatic attenuation of the intervention intensity under real physical fault conditions.

[0062] Specifically, based on the reference voltage and the rated voltage, the deviation of the total applied voltage from the reference voltage is calculated, and the preset maximum compensation conductance is modulated in conjunction with the mismatch sensitivity factor to obtain the dynamic compensation admittance at the current moment.

[0063] Specifically, the dynamic compensation admittance satisfies the expression:

[0064] ;

[0065] In the formula, The dynamic compensation admittance at time t; To maximize the compensation conductivity; The saturation coefficient; This represents the total applied voltage at time t; Reference voltage; Rated voltage; Let be the mismatch sensitivity factor at time t.

[0066] In this embodiment, the saturation coefficient determines the saturation coefficient's response sensitivity to mismatch-sensitive factors, with an empirical value range of [5, 20], and the saturation coefficient is set to 10. In other embodiments, the implementer can adjust the saturation coefficient according to the required response speed. For example, when rapid suppression of initial oscillations is required, the saturation coefficient can be appropriately increased; when damping intervention is required for a smooth transition, the saturation coefficient can be appropriately decreased.

[0067] In this embodiment, the maximum compensation conductance determines the physical upper bound of the numerical intervention intensity, with an empirical range of [0.05, 0.2], and the maximum compensation conductance is set to 0.1 Siemens. In other embodiments, the implementer can adjust the maximum compensation conductance according to the severity of the numerical oscillation. For example, when the node voltage oscillation amplitude is large and difficult to converge, the maximum compensation conductance can be appropriately increased to enhance the dissipation capability; when the simulation waveform requires extremely high fidelity and the oscillation is relatively mild, the maximum compensation conductance can be appropriately decreased.

[0068] in, This demonstrates the modulation effect of the mismatch sensitivity factor on the maximum compensation conductance. The larger the value, The smaller the value, the more... The closer the value is to 1, the higher the dynamic compensation admittance. The more it converges to the maximum compensation conductance This provides sufficient damping to suppress oscillations while preventing parameter divergence. The smaller the value, The closer the value is to 1, the more... Approaching 0, maximum compensation conductance The value is modulated to near zero to ensure that dynamic compensation of admittance does not introduce additional numerical losses when the system is stable.

[0069] The larger the value, The smaller the value, the larger the deviation of the total applied voltage from the reference voltage, and the more likely the converter has deviated from the linear simulation region and entered the large-signal transient region, thus affecting the dynamic compensation admittance. The value is reduced to prevent the numerical damping from excessively smoothing the amplitude of the real physical waveform and to ensure the accuracy of fault characteristic reproduction. The smaller the value, The closer the value is to 1, the closer the total applied voltage is to the reference voltage, and the more likely the converter is to be in the steady-state micro-disturbance range, which is beneficial for dynamic compensation admittance. The smaller the impact of the value, the better the synergistic suppression of minute numerical fluctuations.

[0070] S5. Introduce dynamic compensation admittance, use the nodal voltage method to solve the nodal voltage, and use the trapezoidal integral algorithm to complete the closed-loop state update.

[0071] It should be noted that while dynamic compensation admittance corrects the transmission line node voltage, failure to feed this correction value back to the internal submodules of the converter in real time will cause a time-series decoupling between the port voltage and the internal energy storage state. This asynchrony can lead to numerical energy drift in discretized calculations, violating the system's energy conservation constraints and causing simulation divergence. Therefore, this invention eliminates time lag errors in numerical calculations by establishing instantaneous linkage updates between node voltage and submodule capacitor states, ensuring data consistency and numerical stability.

[0072] Specifically, the characteristic conductance is obtained by taking the reciprocal of the characteristic impedance; based on the converter's physical inductance, virtual inductance, and simulation step size, the equivalent conductance of the converter arm at the current moment is obtained using the trapezoidal integral discretization algorithm, which is well-known in the field of electromagnetic transient simulation; the characteristic conductance, equivalent conductance, and dynamic compensation admittance are added together to obtain the node admittance; the incident voltage transmitted from the opposite converter at the previous moment is received using the fiber optic interface, and the historical current components are calculated using the Bergeron transmission line model in the field of power system electromagnetic transient simulation; based on the total number of submodules in operation at the current moment, the total voltage in operation at the previous moment, the arm current at the previous moment, and the nominal capacitance of the submodules, the Norton equivalent current inside the converter is calculated using the trapezoidal integral method according to well-known techniques in electromagnetic transient simulation; the node current is obtained based on the Norton equivalent current inside the converter and the historical current components; and the node voltage is obtained by substituting the node current and node admittance into the standard node voltage method.

[0073] Specifically, the node voltage satisfies the expression:

[0074] ;

[0075] In the formula, Let be the node voltage at time t; Let be the Norton equivalent current at time t; Characteristic conductivity; Let be the equivalent conductance at time t; The historical current component at time t; Let be the dynamic compensation admittance at time t.

[0076] in, This represents the physical reference admittance of the converter. For nodal admittance, dynamic compensation admittance The larger the value, the stronger the numerical compensation and the higher the nodal admittance. The value increases, causing the node voltage to... The amplitude response is dynamically reduced. This process is equivalent to connecting a low-impedance energy dissipation channel in parallel at the numerical calculation node, thereby suppressing non-physical voltage spikes caused by algorithm discretization errors, forcing the numerical solution to return to the convergence interval, and preventing simulation divergence.

[0077] Dynamic compensation admittance The smaller the value, the lower the nodal admittance. The closer the value is to the physical reference admittance of the converter and ( This indicates that the more stable the current calculation conditions, the closer the denominator value of the node voltage expression is to the physical true admittance, thus making the node voltage... The solution process tends to revert to the standard transmission line model, thereby reducing the impact on steady-state operating accuracy.

[0078] Furthermore, based on the node voltage, the converter arm current at the current moment is calculated using the standard transmission line branch equation; based on the converter arm current at the current moment, the estimated capacitor voltage of each submodule in the next simulation step is calculated using the standard trapezoidal integral algorithm; the converter arm current at the current moment, the sum of the current input voltage, and the estimated capacitor voltage of each submodule in the next simulation step are written into the FPGA internal memory as historical state data for the next simulation step; the node voltage is converted into an analog signal using the FPGA digital-to-analog conversion interface; the analog signal is output to an external hardware controller to complete the closed-loop real-time simulation iteration.

[0079] It should be added that, in transmission line theory, characteristic conductance and characteristic impedance describe the inherent proportional relationship in the propagation of electromagnetic waves. In simulation modeling, characteristic conductance is the reciprocal of characteristic impedance, serving as a static component of the node admittance matrix and characterizing the reference electrical properties of the interface. The Bergeron transmission line model is a classical electromagnetic transient model based on the traveling wave principle. It utilizes time delay characteristics to electrically decouple converter station nodes that are a certain distance apart, making parallel simulation of large-scale power systems possible. Norton's equivalent current, based on Norton's theorem, simplifies a complex network containing power sources, controlled sources, and linear elements into a parallel form of an equivalent current source and an equivalent admittance. In this field... Commonly used for port modeling of converter submodules within a discretization step size; Trapezoidal integral discretization is the mainstream numerical integration algorithm in electromagnetic transient simulation (EMTP). Its physical meaning is to transform continuous time-domain equations into discrete algebraic equations. By equating energy storage elements such as inductors and capacitors to a parallel structure of resistors and current sources, the step-by-step solution of electrical network equations is achieved; Impedance mismatch refers to the inconsistency between the preset characteristic impedance and the actual instantaneous impedance of the controlled side in simulation based on the transmission line model (TLM). In modular multilevel converters (MMC), frequent switching of submodules can cause a step jump in the equivalent parameters of the bridge arm. If the simulation parameters remain fixed, it will cause non-physical numerical reflections at the computation nodes.

[0080] For example, Figure 2 The figure shows a comparison of the node voltage simulation waveforms of the traditional fixed impedance method and the dynamic compensation method of this invention. In the figure, when the simulation enters the parameter abrupt change interval after 20ms, the traditional fixed impedance method, limited by a constant characteristic impedance, cannot adapt to the real-time transient impedance changes. This impedance mismatch induces severe high-frequency numerical oscillations in the discretization calculation, manifesting as sawtooth peaks on the waveform. The dynamic compensation method of this invention calculates the mismatch sensitivity factor in real time and generates a dynamic compensation admittance accordingly, enabling the curve of the dynamic compensation method of this invention to suppress numerical oscillations in this interval. This invention utilizes the adaptive damping effect introduced by the dynamic compensation admittance to offset the numerical error energy caused by impedance mismatch, reflecting the enhanced numerical stability of the simulation.

Claims

1. A real-time simulation method for a modular multilevel converter based on FPGA, characterized in that, include: The parallel interface is used to read the converter arm current, the capacitor voltage of each submodule, and the switch status signal. The total number of sub-modules in operation at the current moment is obtained based on the switching status signals of each sub-module, and the total voltage of the operation at the current moment is obtained by combining the corresponding sub-module capacitor voltage. The instantaneous impedance is obtained based on the total number of sub-modules and the preset nominal capacitance, physical inductance and virtual inductance of the sub-modules; the current change rate at the current moment is obtained based on the difference between the current of the converter arm and the current of the previous moment, combined with the simulation step size. The mismatch sensitivity factor is obtained based on instantaneous impedance, current change rate, and preset characteristic impedance; Based on the sum of the applied voltages and the preset reference voltage and rated voltage, dynamic compensation admittance is generated by modulating the preset maximum compensation conductance in conjunction with the mismatch sensitivity factor. The characteristic conductance is obtained by taking the reciprocal of the characteristic impedance; the equivalent conductance is obtained based on the physical inductance, virtual inductance, and simulation step size. The node admittance is obtained based on the characteristic conductance, equivalent conductance, and dynamic compensation admittance; the Norton equivalent current is obtained based on the total number of sub-modules, nominal capacitance, total input voltage, and bridge arm current; the node current is generated by combining the historical current components obtained through the transmission line model; the node voltage is obtained based on the node current and node admittance; and the closed-loop real-time simulation iteration is completed based on the node voltage. The mismatch sensitivity factor satisfies the following relationship: In the formula, Let be the mismatch sensitivity factor at time t; Characteristic impedance; Let be the instantaneous impedance at time t; The rate of change weighting coefficient; Let be the rate of change of current at time t; Dynamic compensation admittance satisfies the following relationship: In the formula, The dynamic compensation admittance at time t; To maximize the compensation conductivity; The saturation coefficient; This represents the total applied voltage at time t; Reference voltage; Rated voltage; Let be the mismatch sensitivity factor at time t.

2. The real-time simulation method for a modular multilevel converter based on FPGA according to claim 1, characterized in that, The step of obtaining the total number of sub-modules in operation at the current moment based on the switching status signals of each sub-module, and obtaining the total input voltage at the current moment by combining the corresponding sub-module capacitor voltage, includes: performing parallel statistics on the switching status signals of each sub-module using an adder tree structure to calculate the total number of sub-modules in operation at the current moment; using the switching status signals of each sub-module as numerical weights, performing multiplication with the corresponding sub-module capacitor voltage to obtain input voltage components; and performing parallel accumulation on the input voltage components of all sub-modules using an adder tree structure to calculate the total input voltage at the current moment.

3. The real-time simulation method for a modular multilevel converter based on FPGA according to claim 1, characterized in that, The instantaneous impedance satisfies the following relationship: ； In the formula, Let be the instantaneous impedance at time t; This is the physical inductance value; For virtual inductance; The nominal capacitor for the submodule; Let be the total number of sub-modules deployed at time t.

4. The real-time simulation method for a modular multilevel converter based on FPGA according to claim 1, characterized in that, The node voltages satisfy the following relationship: ； In the formula, Let be the node voltage at time t; Let be the Norton equivalent current at time t; Characteristic conductivity; Let be the equivalent conductance at time t; The historical current component at time t; Let be the dynamic compensation admittance at time t.

5. The real-time simulation method for a modular multilevel converter based on FPGA according to claim 1, characterized in that, The step of obtaining the current change rate at the current moment based on the difference between the converter arm current at the current moment and the previous moment, combined with the simulation step size, includes: dividing the absolute value of the difference between the converter arm current at the current moment and the converter arm current at the previous moment by the simulation step size to obtain the current change rate at the current moment.

6. The real-time simulation method for a modular multilevel converter based on FPGA according to claim 1, characterized in that, The step of obtaining the equivalent conductance based on the physical inductance value, virtual inductance, and simulation step size includes: obtaining the equivalent conductance of the converter arm at the current moment using a trapezoidal integral discretization algorithm based on the converter's physical inductance value, virtual inductance, and simulation step size.

7. The real-time simulation method for a modular multilevel converter based on FPGA according to claim 1, characterized in that, The method of obtaining the Norton equivalent current based on the total number of sub-modules in operation, nominal capacitance, total input voltage, and bridge arm current includes: calculating the Norton equivalent current inside the converter using the trapezoidal integration method based on the total number of sub-modules in operation at the current moment, the total input voltage at the previous moment, the bridge arm current at the previous moment, and the nominal capacitance of the sub-modules.

8. The real-time simulation method for a modular multilevel converter based on FPGA according to claim 1, characterized in that, The process of generating node current from historical current components obtained through the transmission line model includes: receiving the incident wave voltage transmitted from the peer converter at the previous moment using the fiber optic interface, and calculating the historical current components using the Bergeron transmission line model.

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