Grid-based distributed ICG control methods, structures, devices, equipment, and media
By dividing the chip into grid areas and deploying CLU control ICG units, the problems of decreased test coverage and power consumption caused by the introduction of ICG are solved, achieving efficient test coverage and low-power design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SOPHGO TECH LTD
- Filing Date
- 2026-03-23
- Publication Date
- 2026-07-17
Smart Images
Figure CN121920292B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of circuit technology, and in particular to a grid-distributed ICG control method, structure, device, equipment and medium. Background Technology
[0002] With advancements in semiconductor technology, the design scale and complexity of System-on-Chips (SoCs) continue to increase, making low-power design a critical requirement. Integrated Clock Gating (ICG), as a standard unit, reduces dynamic power consumption by gating the clock signal, and has become one of the most direct and effective methods in low-power design. In chip functional modes, the ICG's enable port can control clock propagation as needed. However, in Design for Testability (DFT), the introduction of ICG brings problems such as reduced test coverage.
[0003] Scan testing is a core technology of DFT (Design for Testing). It uses the Automatic Test Pattern Generation (ATPG) tool to generate test vectors to detect manufacturing defects. In at-speed testing, the test needs to reuse the functional clock network, and since the ICG is located on the clock path, the ATPG must configure the E-port of the ICG to a high level to enable the clock before capturing test values. However, when the number of ICGs is large or the control logic of the E-port is too complex, the ATPG struggles to complete the configuration with a limited number of test vectors, resulting in reduced test coverage.
[0004] To address the aforementioned issues, existing technologies have proposed various ICG control schemes. One common approach is to change the ICG's test enable port (TE port) from being controlled by the default scan enable signal (SCAN_EN) to being controlled by the test data register (TDR). During the scan test setup phase, TDR is configured high, eliminating the need for the ATPG to directly configure the E port, thus simplifying the test process and improving coverage. Another method uses a dedicated scan flip-flop (SFF) combined with an OR logic combination of the SCAN_EN signal to control the TE port. When the ATPG cannot activate the ICG via the E port, the value of SFF can be configured through a shift process, indirectly activating the ICG.
[0005] Although the above methods can partially improve test coverage, they still have drawbacks such as excessive test power consumption, insufficient power consumption control, difficulty in timing convergence, and poor scalability. Therefore, how to improve chip test coverage through innovative grid-distributed control structures is a key issue. Summary of the Invention
[0006] This application provides a grid-distributed ICG control method, structure, device, equipment, and medium to improve chip test coverage.
[0007] In a first aspect, this application provides a grid-distributed ICG control method, the method comprising:
[0008] Obtain the target chip for testing, and generate a pre-scan netlist based on each target chip;
[0009] The original chip layout of the target chip is divided into at least one grid region according to the pre-scan netlist, and the clock gating unit (ICG) list corresponding to each grid region is obtained.
[0010] The controllable logic unit (CLU) is obtained according to each of the ICG lists, a CLU scan chain is generated according to each CLU, and a target scan netlist is generated according to the CLU scan chain.
[0011] Each CLU is assigned to each grid region according to the target scan netlist, and each ICG in the ICG list is controlled by the CLU in each grid region.
[0012] Secondly, this application also provides a grid-distributed ICG control structure, the structure comprising:
[0013] At least one grid region, each of the grid regions being a division of the original chip layout based on the target chip;
[0014] At least one controllable logic unit (CLU), each CLU being deployed in one of the grid regions, is used to control the test enable port of each clock gate unit (ICG) in the grid region;
[0015] A scan chain structure, consisting of at least one of the CLUs connected sequentially, is used to control the ICG and perform embedded deterministic testing.
[0016] Thirdly, this application also provides a grid-distributed ICG control device, the device comprising:
[0017] A pre-scan netlist generation module is used to acquire target chips for testing and generate pre-scan netlists based on each target chip.
[0018] The ICG list determination module is used to divide the original chip layout of the target chip into at least one grid region according to the pre-scan netlist, and obtain the clock gating unit (ICG) list corresponding to each grid region.
[0019] The target scan netlist generation module is used to obtain controllable logic units (CLUs) according to each of the ICG lists, generate CLU scan chains according to each of the CLUs, and generate a target scan netlist according to the CLU scan chains.
[0020] The ICG control module is used to assign each of the CLUs to each of the grid regions according to the target scan netlist, and to control each ICG in the ICG list through the CLUs in each of the grid regions.
[0021] Fourthly, this application also provides a computer device, the computer device including a memory and a processor; the memory is used to store a computer program; the processor is used to execute the computer program and implement the grid-distributed ICG control method as described above when executing the computer program.
[0022] Fifthly, this application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, causes the processor to implement the grid-distributed ICG control method as described above.
[0023] This application discloses a grid-distributed ICG control method, structure, apparatus, device, and medium. The grid-distributed ICG control method includes: acquiring a target chip for testing and generating a pre-scan netlist based on each target chip; dividing the original chip layout of the target chip into at least one grid region based on the pre-scan netlist and acquiring a clock-gated cell (ICG) list corresponding to each grid region; acquiring controllable logic units (CLUs) based on each ICG list, generating a CLU scan chain based on each CLU, and generating a target scan netlist based on the CLU scan chain; allocating each CLU to each grid region based on the target scan netlist, and controlling each ICG in the ICG list through the CLU in each grid region. Through this method, this application achieves refined and regionalized on-demand activation of ICG units by physically dividing the chip into multiple grid regions and deploying independent CLUs for control in each grid. Each CLU serves as an independent control point configurable by the scan chain, providing a direct and flexible control channel for automatic test vector generation tools and improving the chip's test coverage. Attached Figure Description
[0024] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0025] Figure 1 This is a schematic flowchart of a grid-distributed ICG control method provided in an embodiment of this application;
[0026] Figure 2 This is a schematic diagram of a grid-distributed ICG control structure provided by an embodiment of this application;
[0027] Figure 3 A schematic diagram of CLU signal connection for a grid-distributed ICG control structure is provided as an embodiment of this application;
[0028] Figure 4 A schematic diagram of the internal structure of the CLU in a grid-distributed ICG control structure is provided for an embodiment of this application;
[0029] Figure 5 A schematic block diagram of a grid-distributed ICG control device provided for embodiments of this application;
[0030] Figure 6 A schematic block diagram of the structure of a computer device provided for an embodiment of this application. Detailed Implementation
[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0032] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.
[0033] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.
[0034] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.
[0035] This application provides a grid-distributed ICG control method, structure, apparatus, device, and medium. The grid-distributed ICG control method can be applied to servers. By physically dividing the chip into multiple grid regions and deploying an independent CLU for control of each grid, it achieves fine-grained and regionalized on-demand activation of ICG units. Each CLU serves as an independent control point configurable by the scan chain, providing a direct and flexible control channel for automated test vector generation tools, thereby improving the chip's test coverage. The server can be a standalone server or a server cluster.
[0036] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0037] Please see Figure 1 , Figure 1 This is a schematic flowchart illustrating a grid-distributed ICG control method provided in an embodiment of this application. This grid-distributed ICG control method can be applied in servers to improve chip test coverage.
[0038] like Figure 1 As shown, the grid-distributed ICG control method specifically includes steps S10 to S40.
[0039] Step S10: Obtain the target chip for testing, and generate a pre-scan netlist based on each target chip;
[0040] Specifically, the IP modules required for scan testing are inserted at the RTL (Register-Transfer Level) stage. Electronic Design Automation (EDA) tools are used to insert the core IP modules required for scan testing. These may include embedded deterministic test (EDT) logic, used to compress test vectors and decompress test responses, basic architecture definition of the scan chain, test clock and reset control logic.
[0041] Logic synthesis, also known as logic synthesis, involves using a logic synthesis tool to synthesize RTL code with inserted DFT IP and the target technology library. The synthesis process converts the high-level description into a gate-level netlist composed of standard cells and macro modules; this netlist is called the pre-scan netlist. The pre-scan netlist contains all ICG (Integrated Clock Gating) cells, but they are not yet connected to the subsequently introduced controllable logic units (CLUs).
[0042] Step S20: Divide the original chip layout of the target chip into at least one grid region according to the pre-scan netlist, and obtain the clock gating unit (ICG) list corresponding to each grid region;
[0043] Specifically, the obtained pre-scanned netlist is imported into the physical implementation tool, and rapid placement is performed without detailed routing. The tool then places standard cells and modules in a preliminary manner to determine the approximate shape and size of the chip's core area.
[0044] Based on the initial layout results, the core area of the chip is uniformly divided into an M×N grid on the plane. For example, a square chip core can be divided into an 8×8 grid, with a total of 64 regions. The number of grids can be adjusted according to the design scale and the requirements for control granularity.
[0045] For each grid region, execute a script or use a tool command to extract and record all ICG cells whose physical locations fall within the grid boundary. Generate an independent ICG list for each grid, which contains the instance name, location coordinates, and other information of all ICG cells that need to be controlled within that region.
[0046] Step S30: Obtain controllable logic unit (CLU) according to each ICG list, generate CLU scan chain according to each CLU, and generate target scan netlist according to the CLU scan chain;
[0047] Specifically, the CLU, as a custom standard unit, consists of a scan flip-flop (SFF) with a communication data input, a 2-to-1 multiplexer (MUX), and a 2-input OR gate. During the scan chain insertion phase, a CLU instance is instantiated for each grid region according to the ICG list. For example, if 64 grids are divided, 64 CLUs are instantiated. All instantiated CLU units are chained together into an independent scan chain. Specifically, the scan enable input of the first CLU is connected to the output of the EDT logic decompression, its scan output Q is connected to the scan enable input of the next CLU, and so on, forming a long shift register chain. This chain is independent of the chip function data scan chain.
[0048] For each grid, the output terminal TE of its CLU is connected to the output terminal TE of each ICG cell in the ICG list of that grid, which means that a CLU will control all ICGs within its grid.
[0049] The final target scan netlist is output through the EDA tool. The target scan netlist contains complete circuit logic, including the original functional circuits and ordinary scan chains, as well as the newly added CLU scan chains and control networks from CLU to each ICG.
[0050] Step S40: Assign each CLU to each grid region according to the target scan netlist, and control each ICG in the ICG list through the CLU in each grid region.
[0051] Specifically, the target scan netlist is imported back into the physical implementation tool for complete and detailed placement and routing. During placement, placement constraints are applied to the CLU cells, forcing the tool to place each CLU cell within the grid area it controls. This ensures that the CLU and the ICG group it controls are physically adjacent. Timing analysis and optimization are then performed based on the actual routing. Because the CLUs are placed close together, the path delay from the CLU to the ICG output TE is very short, making clock gating checks easy to satisfy. The tool only needs to insert a few buffers on a few long paths to achieve timing convergence, thus effectively controlling area overhead.
[0052] Once timing, power consumption, and area all meet design requirements, the tool generates the final physical layout for chip manufacturing. In this layout, the output terminals (TEs) of the ICGs within each grid of the mesh-distributed CLU control architecture are driven and controlled by CLUs located within the same grid.
[0053] This embodiment discloses a grid-distributed ICG control method, structure, device, equipment, and medium. The grid-distributed ICG control method includes: acquiring a target chip for testing and generating a pre-scan netlist based on each target chip; dividing the original chip layout of the target chip into at least one grid region based on the pre-scan netlist and acquiring a clock-gated unit (ICG) list corresponding to each grid region; acquiring controllable logic units (CLUs) based on each ICG list, generating a CLU scan chain based on each CLU, and generating a target scan netlist based on the CLU scan chain; allocating each CLU to each grid region based on the target scan netlist, and controlling each ICG in the ICG list through the CLU in each grid region. Through the above method, this application achieves refined and regionalized on-demand activation of ICG units by physically dividing the chip into multiple grid regions and deploying independent CLUs for control in each grid. Each CLU serves as an independent control point configurable by the scan chain, providing a direct and flexible control channel for automatic test vector generation tools and improving the chip's test coverage.
[0054] based on Figure 1In the illustrated embodiment, step S20 includes:
[0055] A preliminary placement and routing scheme is generated using the pre-scanned netlist and the original chip layout, and the physical dimensions of the target chip are determined using the placement and routing scheme.
[0056] Specifically, the pre-scan netlist generated after logic synthesis is imported into the physical implementation tool, along with the chip's original chip layout framework file and process technology file. In the physical implementation tool, the "coarse placement" command is run. Based on the netlist's connectivity, all standard cells (including all ICG cells, logic gates, etc.) and macro modules are initially, but not ultimately, placed within the chip's core region.
[0057] After the initial layout, a preliminary layout and routing scheme will be formed. Based on this scheme, the width and height of the chip's core area can be accurately calculated, i.e., the chip's physical dimensions. The chip's physical dimensions are the sole basis for subsequent precise mesh division, ensuring that the mesh can completely and uniformly cover the entire chip's core area.
[0058] Based on a preset rectangular grid algorithm and the chip's physical dimensions, the original chip layout is divided into at least one grid region;
[0059] Specifically, the mesh generation parameters are pre-set based on the design scale and the required granularity of test control. There are generally two methods:
[0060] Define the number of grid lines: For example, divide the core area into 8 rows. There are 8 columns, with a total of 64 rectangular grids.
[0061] Define the mesh size: For example, specify that each mesh size is 100μm. 100μm. In the physical implementation environment, a preset rectangular grid algorithm is invoked by writing a script or using the tool's built-in commands. This algorithm uses the lower left corner of the chip core region as the origin (0,0) and the upper right corner (width, height) as the boundary. According to the preset specifications, the algorithm generates an invisible rectangular grid covering the entire core region. The boundary coordinates (X1, Y1, X2, Y2) of each grid are precisely calculated and stored in memory.
[0062] Extract each ICG cell from each of the grid regions, and generate the ICG list based on each of the ICG cells.
[0063] Specifically, for each grid region, the following operations are performed iteratively: A query command is sent to the physical database with the logic: "Find all cells whose instance name is of type 'ICG' and whose layout coordinates (usually the center point or bounding box) fall within the current grid boundary (X1, Y1, X2, Y2)." The tool records the instance name (e.g., U1_ICG_clock_domain_A) of each matching ICG cell in a list structure. Finally, a separate text file or data structure is generated for each grid as the ICG list for that region.
[0064] based on Figure 1 In the illustrated embodiment, step S30 includes:
[0065] The CLU is instantiated from a preset cell library according to the ICG list in each of the grid regions;
[0066] Specifically, the designed Controllable Logic Unit (CLU) needs to be treated as a standard unit, and its front-end (logic function, symbol) and back-end (physical layout, timing library, LEF file) design needs to be completed and integrated into the project's preset unit library. This ensures that synthesis and placement / routing tools can recognize and use the unit.
[0067] Write a script (such as Tcl / Perl / Python) that reads ICG list files in a loop. For each non-empty ICG list file (i.e., at least one ICG cell exists within the mesh), instantiate a CLU cell in the current netlist design. During instantiation, each CLU should be assigned a unique instance name to reflect its mesh location for subsequent physical layout and debugging. For example:
[0068] For the grid (1,1), instantiate CLU_cell_1_1;
[0069] For grid (1,2), instantiate CLU_cell_1_2.
[0070] If a grid's ICG list is empty (i.e., there are no ICG cells in the grid), then there is no need to instantiate a CLU for that grid, thus saving resources.
[0071] The scan input and scan output terminals of each instantiated CLU are cascaded sequentially to generate the CLU scan chain;
[0072] Specifically, a concatenation order is determined for all instantiated CLUs. An intuitive and easy-to-manage strategy is to sort them according to their physical location on the grid, for example, using a row-major order. That is, starting from the first row, all CLUs in that row are connected from left to right, then the second row is connected, and so on.
[0073] Connect the CLUs sequentially according to the determined order, using scripts or netlist editing commands:
[0074] Connect the scan enable input (SI) of the first CLU to the scan data output signal (e.g., edt_scan_out) from the test compression logic (such as EDT).
[0075] Connect the scan output terminal Q of the previous CLU to the scan enable input terminal (SI) of the next CLU.
[0076] Connect the scan output Q of the last CLU to the scan data input signal of the test compression logic (e.g., edt_scan_in), or a test output port for observation.
[0077] In addition, all CLU clock signals need to be connected to a unified test clock, and the communication data input terminals need to be connected to a unified test reset signal.
[0078] The target scan netlist is generated according to the preset scan logic and the CLU scan chain.
[0079] Specifically, the scan mode signal (SCAN_MODE) terminal of each CLU is connected to the global scan mode signal of the chip;
[0080] Connect the scan enable input of each CLU to the global scan enable signal of the chip.
[0081] based on Figure 1 In the illustrated embodiment, step S40 includes:
[0082] Position constraints are applied to the CLU according to the target scan netlist, and the CLU is assigned to the mesh region corresponding to the CLU based on the position constraints;
[0083] Specifically, input the target scan netlist and preliminary layout information (in which the mesh has already been divided), write a layout constraint script, and create a precise position constraint for each CLU instance. For example, specify a placement location for each CLU that should be located near the center of its corresponding mesh area.
[0084] Run the tool's detailed layout commands. The tool will legalize the placement of CLUs and all other standard cells while adhering to all location constraints, and will initially optimize timing and wiring congestion.
[0085] Establish the connection relationship between the CLU and each of the ICGs, and control each of the ICGs through the CLU based on the connection relationship.
[0086] Specifically, clock tree synthesis is performed on all clock networks, including the CLU scan chain clock and the ICG function clock, to balance clock skew, and the tool's global routing and detailed routing commands are executed. The tool will automatically complete the following key connections:
[0087] The scan enable input and scan output Q of each CLU are connected by metal wires. Physical wiring is performed from the output TE of each CLU to the output TE of all ICGs in its grid. After wiring, a physical metal connection is established between the CLU and the ICG.
[0088] During the shift phase of the scan test, the test vector can be serially shifted to the scan trigger inside each CLU through an independent CLU scan chain. During the capture phase, the CLU generates the required level at its output TE based on its latched value, combined with the scan enable and scan mode signals. The level of the output TE is sent to the output TE of all ICGs in the grid almost simultaneously through a very short physical connection, thereby synchronously and precisely controlling the opening and closing of these ICGs.
[0089] This application implements a grid-distributed ICG control structure through physical grid partitioning. During ATPG, when the fault to be tested is only in one or a few physical grids, if ICG needs to be enabled by configuring the CLU control output TE, only the CLUs in the grids covered by the test vector need to be configured; the ICGs in other grids will remain disabled. Because the ATPG tool automatically analyzes the coverage of the test vector and rationally controls the configuration values of the CLU scan chain based on the characteristics of the test vector, test power consumption is minimized.
[0090] Furthermore, the output TE of the CLU module to the ICG requires timing checks under the shift-capture clock domain. The mesh-distributed architecture of the CLU module in this application effectively shortens the physical distance between the CLU and the ICG output TE, while also reducing the clock skew between the CLU and ICG units. This effectively reduces the timing convergence difficulty of the ICG gating check, decreases the number of buffers or inverters inserted during back-end convergence timing, thereby reducing area overhead and further reducing test power consumption.
[0091] Finally, the grid-distributed architecture of this application has two-dimensional scalability, and the distribution density of CLUs can be controllably adjusted according to the designed structure, size, and requirements for DFT test coverage and test power consumption.
[0092] Please see Figure 2 , Figure 2 This is a schematic diagram of a grid-distributed ICG control structure provided by an embodiment of this application.
[0093] like Figure 2 As shown, the grid-distributed ICG control structure includes:
[0094] At least one grid region, each of the grid regions being a division of the original chip layout based on the target chip;
[0095] At least one controllable logic unit (CLU), each CLU being deployed in one of the grid regions, is used to control the test enable port of each clock gate unit (ICG) in the grid region;
[0096] A scan chain structure, consisting of at least one of the CLUs connected sequentially, is used to control the ICG and perform embedded deterministic testing.
[0097] Specifically, based on the physical design layout of the circuit, the design is uniformly divided into grid-like regions. The designed CLUs are instantiated one by one as standard units in the grid circuit to control the output terminals TE of all ICGs in the grid. This architecture is also scalable, and can be divided into different numbers of regions according to the shape and size of the actual circuit. The figure shows an example of dividing into nine regions, and the actual grid can be expanded in two dimensions.
[0098] Specifically, CLU includes:
[0099] A scan trigger, wherein the input terminal of the scan trigger is connected to the scan input signal, the clock terminal of the scan trigger is connected to the scan-capture clock, and the reset terminal of the scan trigger is connected to the test reset signal;
[0100] A multiplexer, wherein the first input terminal of the multiplexer is grounded, the second input terminal of the multiplexer is connected to the output terminal of the scan trigger, and the selection terminal of the multiplexer is connected to the scan mode control signal;
[0101] The OR gate has its first input connected to the output of the multiplexer, its second input connected to the scan enable signal, and its output connected to the test enable port of the ICG.
[0102] Specifically, such as Figure 3 As shown, Figure 3This application provides a schematic diagram of CLU signal connection for a grid-distributed ICG control structure.
[0103] The CLU has five inputs and two outputs. On the input side, the scan enable input receives the vector signal decompressed by the EDT (Embedded Deterministic Testing) logic, the clock signal comes from the shift-capture clock, and the communication data input is controlled by the JTAG network's reset signal. On the output side, the scan output Q is connected to the scan enable input of the subsequent CLU to form a scan chain, and the output TE is connected as a control signal to the output of the ICG.
[0104] Specifically, the output of the CLU is also connected to the scan input of the next-level CLU.
[0105] Specifically, such as Figure 4 As shown, Figure 4 This application provides a schematic diagram of the internal structure of the CLU in a grid-distributed ICG control structure.
[0106] From the standard cell library, select one SFF with communication data input, one two-input MUX, and one two-input OR gate. The SFF has a feedback loop structure from the scan output Q to the scan input D. The scan output Q is also connected to one input of the MUX, and the other input of the MUX is grounded. The selection terminal of the MUX is controlled by the scan mode signal in the design. The output of the MUX is connected to one input of the OR gate, and the other input is connected to the scan enable.
[0107] Please see Figure 5 , Figure 5 This embodiment of the present application provides a schematic block diagram of a grid-distributed ICG control device for executing the aforementioned grid-distributed ICG control method. The grid-distributed ICG control device can be configured on a server.
[0108] like Figure 5 As shown, the grid-distributed ICG control device 400 includes:
[0109] The pre-scan netlist generation module 410 is used to acquire target chips for testing and generate pre-scan netlists based on each target chip.
[0110] ICG list determination module 420 is used to divide the original chip layout of the target chip into at least one grid region according to the pre-scan netlist, and obtain the clock gating unit (ICG) list corresponding to each grid region.
[0111] The target scan netlist generation module 430 is used to obtain controllable logic units (CLUs) according to each of the ICG lists, generate CLU scan chains according to each of the CLUs, and generate a target scan netlist according to the CLU scan chains.
[0112] ICG control module 440 is used to assign each of the CLUs to each of the grid regions according to the target scan netlist, and control each ICG in the ICG list through the CLUs in each of the grid regions.
[0113] Furthermore, the target scanning netlist generation module 430 includes:
[0114] The chip physical size determination unit is used to generate a preliminary layout and routing scheme through the pre-scanned netlist and the original chip layout, and to determine the chip physical size of the target chip through the layout and routing scheme;
[0115] A grid region division unit is used to divide the original chip layout into at least one grid region based on a preset rectangular grid algorithm and the chip physical dimensions;
[0116] The ICG list generation unit is used to extract each ICG cell in each of the grid regions and generate the ICG list based on each of the ICG cells.
[0117] Furthermore, the target scanning netlist generation module 430 includes:
[0118] A CLU instantiation unit is used to instantiate the CLU from a preset unit library according to the ICG list in each of the grid regions;
[0119] The CLU scan chain generation unit is used to cascade the scan input and scan output terminals of each instantiated CLU in sequence to generate the CLU scan chain;
[0120] The target scan netlist generation unit is used to generate the target scan netlist according to the preset scan logic and the CLU scan chain.
[0121] Furthermore, the target scanning netlist generation module 430 includes:
[0122] CLU allocation unit, used to apply position constraints to the CLU according to the target scan netlist, and allocate the CLU to the grid region corresponding to the CLU based on the position constraints;
[0123] A control ICG unit is used to establish the connection relationship between the CLU and each of the ICGs, and to control each of the ICGs through the CLU based on the connection relationship.
[0124] It should be noted that those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the above-described apparatus and modules can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0125] The aforementioned device can be implemented as a computer program, which can be used in, for example... Figure 6 It runs on the computer device shown.
[0126] Please see Figure 6 , Figure 6 This is a schematic block diagram illustrating the structure of a computer device according to an embodiment of this application. The computer device may be a server.
[0127] See Figure 6 The computer device includes a processor, memory, and network interface connected via a system bus, wherein the memory may include non-volatile storage media and internal memory.
[0128] Non-volatile storage media can store operating systems and computer programs. These computer programs include program instructions that, when executed, cause the processor to perform any grid-distributed ICG control method.
[0129] The processor provides computing and control capabilities, supporting the operation of the entire computer device.
[0130] Internal memory provides an environment for the execution of computer programs in non-volatile storage media. When executed by a processor, the computer program enables the processor to perform any grid-distributed ICG control method.
[0131] This network interface is used for network communication, such as sending assigned tasks. Those skilled in the art will understand that... Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0132] It should be understood that the processor can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among these, a general-purpose processor can be a microprocessor or any conventional processor.
[0133] In one embodiment, the processor is configured to run a computer program stored in memory to perform the following steps:
[0134] Obtain the target chip for testing, and generate a pre-scan netlist based on each target chip;
[0135] The original chip layout of the target chip is divided into at least one grid region according to the pre-scan netlist, and the clock gating unit (ICG) list corresponding to each grid region is obtained.
[0136] The controllable logic unit (CLU) is obtained according to each of the ICG lists, a CLU scan chain is generated according to each CLU, and a target scan netlist is generated according to the CLU scan chain.
[0137] Each CLU is assigned to each grid region according to the target scan netlist, and each ICG in the ICG list is controlled by the CLU in each grid region.
[0138] In one embodiment, the original chip layout of the target chip is divided into at least one grid region according to the pre-scan netlist, and a clock gating unit (ICG) list corresponding to each grid region is obtained, for the purpose of:
[0139] A preliminary placement and routing scheme is generated using the pre-scanned netlist and the original chip layout, and the physical dimensions of the target chip are determined using the placement and routing scheme.
[0140] Based on a preset rectangular grid algorithm and the chip's physical dimensions, the original chip layout is divided into at least one grid region;
[0141] Extract each ICG cell from each of the grid regions, and generate the ICG list based on each of the ICG cells.
[0142] In one embodiment, a controllable logic unit (CLU) is obtained according to each of the ICG lists, a CLU scan chain is generated according to each CLU, and a target scan netlist is generated according to the CLU scan chain, for the purpose of:
[0143] The CLU is instantiated from a preset cell library according to the ICG list in each of the grid regions;
[0144] The scan input and scan output terminals of each instantiated CLU are cascaded sequentially to generate the CLU scan chain;
[0145] The target scan netlist is generated according to the preset scan logic and the CLU scan chain.
[0146] In one embodiment, each CLU is assigned to each of the grid regions according to the target scan netlist, and each ICG in the ICG list is controlled by the CLU in each of the grid regions, to achieve the following:
[0147] Position constraints are applied to the CLU according to the target scan netlist, and the CLU is assigned to the mesh region corresponding to the CLU based on the position constraints;
[0148] Establish the connection relationship between the CLU and each of the ICGs, and control each of the ICGs through the CLU based on the connection relationship.
[0149] The embodiments of this application also provide a computer-readable storage medium storing a computer program, the computer program including program instructions, and the processor executing the program instructions to implement any of the grid-distributed ICG control methods provided in the embodiments of this application.
[0150] The computer-readable storage medium may be an internal storage unit of the computer device described in the foregoing embodiments, such as the hard disk or memory of the computer device. The computer-readable storage medium may also be an external storage device of the computer device, such as a plug-in hard disk, SmartMedia Card (SMC), Secure Digital (SD) card, or Flash Card equipped on the computer device.
[0151] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A grid-distributed ICG control method, characterized in that, include: Obtain the target chip for testing, and generate a pre-scan netlist based on each target chip; The original chip layout of the target chip is divided into at least one grid region according to the pre-scan netlist, and the clock gating unit (ICG) list corresponding to each grid region is obtained. The controllable logic unit (CLU) is obtained according to each of the ICG lists, a CLU scan chain is generated according to each CLU, and a target scan netlist is generated according to the CLU scan chain. According to the target scan netlist, each CLU is assigned to each of the grid regions, and each ICG in the ICG list is controlled by the CLU in each of the grid regions; The step of generating a CLU scan chain based on each CLU and generating a target scan netlist based on the CLU scan chain includes: The scan input and scan output terminals of each instantiated CLU are cascaded sequentially to generate the CLU scan chain; The target scan netlist is generated according to the preset scan logic and the CLU scan chain.
2. The grid-distributed ICG control method according to claim 1, characterized in that, The step of dividing the original chip layout of the target chip into at least one grid region according to the pre-scan netlist and obtaining the clock gating unit (ICG) list corresponding to each grid region includes: A preliminary placement and routing scheme is generated using the pre-scanned netlist and the original chip layout, and the physical dimensions of the target chip are determined using the placement and routing scheme. Based on a preset rectangular grid algorithm and the chip's physical dimensions, the original chip layout is divided into at least one grid region; Extract each ICG cell from each of the grid regions, and generate the ICG list based on each of the ICG cells.
3. The grid-distributed ICG control method according to claim 1, characterized in that, The step of obtaining the controllable logic unit (CLU) according to each of the ICG lists includes: The CLU is instantiated from a preset cell library based on the ICG list in each of the grid regions.
4. The grid-distributed ICG control method according to claim 1, characterized in that, The step of assigning each CLU to each grid region according to the target scan netlist, and controlling each ICG in the ICG list through the CLU in each grid region, includes: Position constraints are applied to the CLU according to the target scan netlist, and the CLU is assigned to the mesh region corresponding to the CLU based on the position constraints; Establish the connection relationship between the CLU and each of the ICGs, and control each of the ICGs through the CLU based on the connection relationship.
5. A grid-distributed ICG control structure, characterized in that, include: At least one grid region, each of the grid regions being a division of the original chip layout based on the target chip; At least one controllable logic unit (CLU), each CLU being deployed in one of the grid regions, is used to control the test enable port of each clock gate unit (ICG) in the grid region; A scan chain structure, consisting of at least one of the CLUs connected sequentially, is used to control the ICG and perform embedded deterministic testing; The CLU includes: A scan trigger, wherein the input terminal of the scan trigger is connected to the scan input signal, the clock terminal of the scan trigger is connected to the scan-capture clock, and the reset terminal of the scan trigger is connected to the test reset signal; A multiplexer, wherein the first input terminal of the multiplexer is grounded, the second input terminal of the multiplexer is connected to the output terminal of the scan trigger, and the selection terminal of the multiplexer is connected to the scan mode control signal; The OR gate has its first input connected to the output of the multiplexer, its second input connected to the scan enable signal, and its output connected to the test enable port of the ICG.
6. The grid-distributed ICG control structure according to claim 5, characterized in that, The output of the CLU is also connected to the scan input of the next-level CLU.
7. A grid-distributed ICG control device, characterized in that, include: A pre-scan netlist generation module is used to acquire target chips for testing and generate pre-scan netlists based on each target chip. The ICG list determination module is used to divide the original chip layout of the target chip into at least one grid region according to the pre-scan netlist, and obtain the clock gating unit (ICG) list corresponding to each grid region. The target scan netlist generation module is used to obtain controllable logic units (CLUs) according to each of the ICG lists, generate CLU scan chains according to each of the CLUs, and generate a target scan netlist according to the CLU scan chains. The ICG control module is used to assign each of the CLUs to each of the grid regions according to the target scan netlist, and control each ICG in the ICG list through the CLUs in each of the grid regions; The target scan netlist generation module includes: The CLU scan chain generation unit is used to cascade the scan input and scan output terminals of each instantiated CLU in sequence to generate the CLU scan chain; The target scan netlist generation unit is used to generate the target scan netlist according to the preset scan logic and the CLU scan chain.
8. A computer device, characterized in that, The computer device includes a memory and a processor; The memory is used to store computer programs; The processor is configured to execute the computer program and, in executing the computer program, implement the grid-distributed ICG control method as described in any one of claims 1 to 4.
9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, causes the processor to implement the grid-distributed ICG control method as described in any one of claims 1 to 4.