算力芯片及其物理设计方法、三维集成电路芯片
By optimizing the layout and routing of computing chips through a hierarchical design approach, the problems of long iteration time and low efficiency of top-level routing in traditional design methods are solved, achieving high density utilization and timing convergence, and optimizing clock delay and offset.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUNMMIO SCIENCE & TECHNOLOGY (BEIJING) CO LTD
- Filing Date
- 2026-01-09
- Publication Date
- 2026-07-17
AI Technical Summary
Traditional flattened design methods have excessively long iteration times when designing computing chips, making it difficult to achieve ultimate optimization. Furthermore, the layout results of different computing units lead to lower efficiency of top-level routing strategies, increasing design complexity and difficulty.
A hierarchical design approach is adopted, including layout and routing design for the computing unit layer, computing group layer, and top layer. The layout and routing design of each design layer is optimized by performing the first layout and routing at the computing unit layer, flattening and deleting routing at the computing group layer, and performing the third layout and routing at the top layer.
It achieves high density utilization and timing convergence, optimizes clock delay and clock skew, and improves the efficiency and quality of chip design.
Smart Images
Figure CN121920305B_ABST