Driving circuit, driving method and display device
By using an adjustment module connected to the control terminal of the transistor in the gate driver integrated circuit, precise switching between negative and positive levels is achieved, solving the problem of transistor threshold voltage drift, extending transistor lifespan, and improving the stability and display accuracy of the driving circuit.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HKC CORP LTD
- Filing Date
- 2026-03-18
- Publication Date
- 2026-04-24
AI Technical Summary
In existing gate-driven integrated circuits, the threshold voltage of transistors undergoes irreversible drift under prolonged exposure to high DC stress and switching stress, leading to a decline in display panel performance.
The adjustment module is connected to the control terminal of the transistor. By inputting precise negative and positive level signals, the transistor is prevented from operating at high voltage for a long time. Multiple adjustment transistors are used to achieve precise level switching and coordinate control signals to reduce threshold voltage drift.
It effectively reduces the threshold voltage drift of transistors, extends the working life of transistors, improves the stability and accuracy of driving circuits, and enhances display consistency and precision.
Smart Images
Figure CN121922060A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of display technology, and more specifically to a driving circuit, driving method, and display device. Background Technology
[0002] Currently, with the increasing demand for ultra-narrow bezels, high screen-to-body ratios, and low costs in smartphones, gate drive integration technology has become a standard configuration for display panels. This technology directly integrates the gate scanning drive circuit onto the array substrate of the display panel, replacing external drive chips, thus simplifying the structure and achieving a stylish design with narrow bezels on all four sides. However, the gate drive integrated circuit in the factory is basically composed of amorphous silicon transistors. Transistors with pull-down or reset functions in the gate drive integrated circuit need to withstand high DC stress and switching stress for a long time during use, which can cause irreversible drift (usually forward drift) of the threshold voltage of these transistors. Summary of the Invention
[0003] The purpose of this invention is to provide a driving circuit, driving method, and display device that improves the threshold voltage drift of transistors.
[0004] To achieve the objectives of this invention, the following technical solution is provided: In a first aspect, the present invention provides a driving circuit, including a first transistor, a second transistor, a third transistor, and an adjustment module. The input terminal of the adjustment module is used to input a first signal, the first signal including a first negative level and a first positive level. The output terminal of the adjustment module is connected to the control terminals of the first transistor and the second transistor. The first terminal of the first transistor is connected to the control terminal of the third transistor. The second terminal of the third transistor is used to input a first timing signal. The first terminal of the third transistor is used to connect to the first terminal of the second transistor and a pixel unit. The second terminals of the first transistor and the second terminal of the second transistor are both used to input a first low-level signal. The first control terminal of the adjustment module is used to output the first negative level when receiving a negative level signal. The second control terminal of the adjustment module is also used to output the first positive level when receiving a positive level signal. The absolute value of the first negative level is less than a preset proportion of the first positive level.
[0005] The first signal is input through the input terminal of the adjustment module. The output terminal of the adjustment module is connected to the control terminals of the first transistor and the second transistor. The first terminal of the first transistor is connected to the control terminal of the third transistor. The second terminal of the third transistor is used to input the first timing signal. The first terminal of the third transistor is used to connect to the first terminal of the second transistor and the pixel unit. The second terminals of the first transistor and the second terminal of the second transistor are used to input the first low-level signal. The first control terminal of the adjustment module is used to output the first negative level when receiving the negative level signal. The second control terminal of the adjustment module is also used to output the first positive level when receiving the positive level signal. The absolute value of the first negative level is less than a preset proportion of the first positive level. The adjustment module outputs the first positive level and the first negative level according to the positive and negative level signals received by the control terminal. The absolute value of the first negative level is less than a preset proportion of the first positive level. Since the output terminal of the adjustment module is connected to the control terminals of the first transistor and the second transistor, it can avoid the control terminals of the first transistor and the second transistor from working at the first positive level voltage for a long time, reduce the threshold voltage drift of the first transistor and the second transistor, and extend the working life of the first transistor and the second transistor.
[0006] In one possible example, the adjustment module includes a first adjustment transistor and a second adjustment transistor. The control terminal of the first adjustment transistor is used to input a (n+4)th level signal, and the control terminal of the second adjustment transistor is used to input the (n+4)th level signal. The first adjustment transistor is used to output a first negative level when it receives the negative level signal at its control terminal, and the second adjustment transistor is used to output a first positive level when it receives the positive level signal at its control terminal. The second terminal of the first adjustment transistor is used to input the first signal, and the second terminal of the second adjustment transistor is used to input the first signal. The first terminal of the first adjustment transistor and the first terminal of the second adjustment transistor are both connected to the control terminals of the first and second transistors.
[0007] The control terminal of the first regulating transistor receives the (n+4)th level signal, and the control terminal of the second regulating transistor also receives the (n+4)th level signal. The first regulating transistor outputs a first negative level when it receives a negative level signal, and the second regulating transistor outputs a first positive level when it receives a positive level signal. The second terminal of both the first and second regulating transistors is used to input the first signal. The first and second terminals of both transistors are connected to their respective control terminals. Since the first regulating transistor outputs a first negative level when it receives a negative level signal, and the second regulating transistor outputs a first positive level when it receives a positive level signal, precise switching between the first negative and first positive levels can be achieved using the same (n+4)th level signal. This avoids circuit malfunctions caused by level output deviations and improves the stability and accuracy of the drive circuit.
[0008] In one possible example, the adjustment module includes a third adjustment transistor and a fourth adjustment transistor. The control terminals of both the third and fourth adjustment transistors are used to input the first timing signal, which includes the negative level signal and the positive level signal. The third adjustment transistor is used to output the first positive level when its control terminal receives the negative level signal, and the fourth adjustment transistor is used to output the first negative level when its control terminal receives the positive level signal. The second terminal of the third adjustment transistor is used to input the first positive level, and the second terminal of the fourth adjustment transistor is used to input the first negative level. The first terminals of the third and fourth adjustment transistors are connected to the control terminals of the first and second transistors, respectively.
[0009] The first timing signal is input to the control terminals of both the third and fourth regulating transistors, and the second terminals are input to the first positive and first negative levels, respectively. The first terminals are connected to the control terminals of the first and second transistors. The third regulating transistor is used to output the first positive level when it receives a negative level signal at its control terminal, and the fourth regulating transistor is used to output the first negative level when it receives a positive level signal at its control terminal. This enables precise switching between the first negative and first positive levels, avoids circuit malfunctions caused by level output deviations, and improves the working stability and accuracy of the drive circuit.
[0010] In one possible example, the driving circuit further includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. The second terminal of the fourth transistor is used to input a first high-level signal, and the control terminal of the fourth transistor is used to input a (n-4)th level signal. The first terminal of the fourth transistor is connected to the first terminal of the fifth transistor, the control terminal of the sixth transistor, the first terminal of the seventh transistor, the first terminal of the first transistor, and the control terminal of the third transistor. The control terminal of the fourth transistor is used to input the (n-4)th level signal, and the control terminal of the fifth transistor is used to input the (n+4)th level signal. The second terminals of the fifth transistor, the sixth transistor, and the seventh transistor are all used to input the first low-level signal. The first terminal of the sixth transistor is connected to the output terminal of the adjustment module, the control terminal of the first transistor, and the control terminal of the second transistor. The control terminal of the seventh transistor is used to input a reset signal.
[0011] The second terminal of the fourth transistor is used to input the first high-level signal, and the control terminal of the fourth transistor is used to input the (n-4)th level signal. The first terminal of the fourth transistor is connected to the first terminal of the fifth transistor, the control terminal of the sixth transistor, the first terminal of the seventh transistor, the first terminal of the first transistor, and the control terminal of the third transistor. The control terminal of the fourth transistor is used to input the (n-4)th level signal, and the control terminal of the fifth transistor is used to input the (n+4)th level signal. The second terminals of the fifth transistor, the sixth transistor, and the seventh transistor are all used to input the first low-level signal. The first terminal of the sixth transistor is connected to the output terminal of the adjustment module, the control terminal of the first transistor, and the control terminal of the second transistor. The control terminal of the seventh transistor is used to input the reset signal. By using the coordinated control of the (n-4)th level signal, the (n+4)th level signal, and the reset signal, the first terminal of the first transistor and the control terminal of the third transistor can be adjusted. At the same time, the reset signal can control the seventh transistor to clear residual charge in the circuit, prevent driving deviation caused by charge accumulation, improve the driving accuracy and display consistency of the pixel unit, and extend the service life of the driving circuit.
[0012] In one possible example, the driving circuit further includes an eighth transistor, the second terminal of which is used to input the first low-level signal, the control terminal of which is used to input a touch signal, and the first terminal of which is connected to the first terminal of the third transistor, the first terminal of the second transistor, and the pixel unit.
[0013] The second terminal of the eighth transistor is used to input a first low-level signal, and the control terminal of the eighth transistor is used to input a touch signal. The first terminal of the eighth transistor is connected to the first terminal of the third transistor, the first terminal of the second transistor, and the pixel unit. Since the control terminal of the eighth transistor inputs the touch signal, the touch function is realized. The second terminal inputs the first low-level signal, and the first terminal is connected to the first terminal of the third transistor, the first terminal of the second transistor, and the pixel unit, thus realizing the driving function. This configuration realizes the integration of driving function and touch function.
[0014] In one possible example, the adjustment module further includes a first auxiliary transistor and a second auxiliary transistor. The second terminal of the first auxiliary transistor is connected to the control terminal of the first auxiliary transistor and is used to input the first high level. The first terminal of the first auxiliary transistor is connected to the first terminal of the second auxiliary transistor and the control terminal of the first adjustment transistor. The second terminal of the second auxiliary transistor is used to input the first low level signal, and the control terminal of the second auxiliary transistor is used to input the (n+4)th level signal. The driving circuit also includes a first auxiliary transistor and a second auxiliary transistor. The second terminal of the first auxiliary transistor is connected to the control terminal of the first auxiliary transistor and is used to input a first high level. The first terminal of the first auxiliary transistor is connected to the first terminal of the second auxiliary transistor and the control terminal of the first regulating transistor. The second terminal of the second auxiliary transistor is used to input a first low level signal. The control terminal of the second auxiliary transistor is used to input the (n+4)th level signal. The first auxiliary transistor and the second auxiliary transistor form an inverter, so that the first auxiliary transistor, the second auxiliary transistor and other transistors in the driving circuit are all of the same type, simplifying the complexity of the circuit.
[0015] Secondly, embodiments of this application provide a driving method applied to a driving circuit as described in the first aspect or any embodiment of the first aspect. The driving circuit includes a first transistor, a second transistor, a third transistor, and an adjustment module. The input terminal of the adjustment module is used to input a first signal, which includes a first negative level and a first positive level. The output terminal of the adjustment module is connected to the control terminals of both the first transistor and the second transistor. The first terminal of the first transistor is connected to the control terminal of the third transistor. The second terminal of the third transistor is used to input a first timing signal. The first terminal of the third transistor is connected to both the first terminal of the second transistor and a pixel unit. The second terminals of both the first transistor and the second transistor are used to input a first low-level signal. The method includes: The first control terminal of the adjustment module outputs the first negative level when receiving a negative level signal. When the second control terminal of the adjustment module receives a positive level signal, it outputs the first positive level, and the absolute value of the first negative level is less than the first positive level of a preset ratio.
[0016] In one possible example, the adjustment module includes a first adjustment transistor and a second adjustment transistor. The control terminal of the first adjustment transistor is used to input a (n+4)th level signal, and the control terminal of the second adjustment transistor is used to input the (n+4)th level signal. The second terminal of the first adjustment transistor is used to input the first signal, and the second terminal of the second adjustment transistor is also used to input the first signal. The first terminals of the first and second adjustment transistors are all connected to the control terminals of the first and second transistors. The method further includes: When the first regulating transistor receives the negative level signal at its control terminal, it outputs the first negative level. When the second regulating transistor receives the positive level signal at its control terminal, it outputs the first positive level.
[0017] In one possible example, the adjustment module includes a third adjustment transistor and a fourth adjustment transistor. The control terminals of both the third and fourth adjustment transistors are used to input the first timing signal, which includes the negative level signal and the positive level signal. The second terminal of the third adjustment transistor is used to input the first positive level, and the second terminal of the fourth adjustment transistor is used to input the first negative level. The first terminals of the third and fourth adjustment transistors are connected to the control terminals of the first and second transistors, respectively. The method further includes: When the third regulating transistor receives the negative level signal at its control terminal, it outputs the first positive level. When the fourth regulating transistor receives the positive level signal at its control terminal, it outputs the first negative level.
[0018] Thirdly, according to an embodiment of this application, a display device includes a timing controller and a driving circuit as described in the first aspect or any embodiment of the first aspect. The timing controller is electrically connected to the driving circuit and is used to transmit a first timing signal of the driving circuit to the driving circuit. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0020] Figure 1 This is a schematic diagram illustrating an application scenario of a driving method according to one embodiment. Figure 2 This is a schematic diagram of the structure of a prior art driving circuit according to one embodiment; Figure 3 This is a schematic diagram of the structure of a first driving circuit according to one embodiment; Figure 4 This is a timing diagram of a first driving circuit according to one embodiment; Figure 5 This is a schematic diagram of the structure of a second driving circuit according to one embodiment; Figure 6 This is a schematic diagram of the first negative level reference margin of a first driving circuit in one embodiment; Figure 7 This is a high-level reference margin when the first negative level of the first driving circuit in one embodiment is set to -3V; Figure 8 This is a schematic diagram of the structure of a third driving circuit in one embodiment; Figure 9 This is a timing diagram of a third driving circuit in one embodiment; Figure 10 This is a schematic diagram of the structure of a fourth driving circuit in one embodiment; Figure 11 This is a flowchart illustrating a driving method of one embodiment; Figure 12 This is a schematic diagram of the structure of a display device according to one embodiment.
[0021] Explanation of reference numerals in the attached figures: 101-User, 102-Display device, 103-Server, 201-First transistor, 202-Second transistor, 203-Third transistor, 204-Fourth transistor, 205-Fifth transistor, 206-Sixth transistor, 207-Seventh transistor, 208-Eighth transistor, 209-First capacitor, 21-Regulation module, 210-First regulating transistor, 211-Second regulating transistor, 212-Third regulating transistor, 213-Fourth regulating transistor, 214-First auxiliary transistor, 215-Second auxiliary transistor, 1201-Timing controller, 1202-Driver circuit, 1203-Processor, 1204-Memory, 1205-Program. Detailed Implementation
[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0023] It should be noted that when a component is said to be "fixed" to another component, it can be directly on the other component or it can be in a middle component. When a component is said to be "connected" to another component, it can be directly connected to the other component or it may be in a middle component.
[0024] Unless otherwise defined, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used in this invention includes any and all combinations of one or more of the associated listed items. Without conflict, the following embodiments and features described herein can be combined with each other.
[0025] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.
[0026] The terms “1” and “2”, etc., in this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such processes, methods, products, or apparatus.
[0027] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0028] Please see Figure 1 , Figure 1 This is a schematic diagram illustrating an application scenario of a driving method provided in an embodiment of this application. For example... Figure 1 As shown in the diagram, this application scenario includes a user 101, a display device 102, and a server 103. Optionally, the display device 102 may be a thin-film transistor liquid crystal display (TFT-LCD), and this application does not limit the structure of the display device 102. Optionally, one user 101 may use multiple display devices 102. Optionally, one user 101 may use multiple servers 103. Optionally, multiple display devices 102 may transmit data with one server 103.
[0029] Optionally, server 103 can be a standalone server or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDN), and big data and artificial intelligence platforms. Server 103 can also be implemented through a server cluster composed of multiple sub-servers. Display device 102, such as a computer, may have an operating system including but not limited to Linux, Unix, and Windows series systems (such as Windows XP, Windows 7, etc.).
[0030] It should be noted that, Figure 1 The number and form of each device in the system shown are for illustrative purposes only and do not constitute a limitation on the embodiments of this application.
[0031] The following describes the driving method provided in the embodiments of this application. The driving method can be executed by the display device 102, which can be implemented by software and / or hardware, and can generally be integrated into the display device 102 or the server 103.
[0032] Please refer to Figure 2 Currently, with the increasing demand for ultra-narrow bezels, high screen-to-body ratios, and low costs in smartphones, gate drive integration technology has become a standard configuration for display panels. This technology directly integrates the gate scanning drive circuit onto the array substrate of the display panel, replacing external drive chips, thus simplifying the structure and achieving a stylish design with narrow bezels on all four sides. However, the gate drive integrated circuit in the factory is basically composed of amorphous silicon transistors. Transistors with pull-down or reset functions in the gate drive integrated circuit need to withstand high DC stress and switching stress for a long time during use, which can cause irreversible drift (usually forward drift) of the threshold voltage of these transistors.
[0033] Please refer to Figure 3 , Figure 3 This is a schematic diagram of the first structure of a driving circuit provided in an embodiment of this application. Figure 3 As shown, the drive circuit includes a first transistor 201, a second transistor 202, a third transistor 203, a fourth transistor 204, a fifth transistor 205, a sixth transistor 206, a seventh transistor 207, an eighth transistor 208, a first capacitor 209, an adjustment module 21, a first adjustment transistor 210, and a second adjustment transistor 211. The drive circuit includes the first transistor, the second transistor, the third transistor, and the adjustment module. Please refer to... Figure 3 and Figure 4 The input terminal of the adjustment module is used to input a first signal, which includes a first negative level and a first positive level. The output terminal of the adjustment module is connected to the control terminal of the first transistor and the control terminal of the second transistor. The first terminal of the first transistor is connected to the control terminal of the third transistor. The second terminal of the third transistor is used to input a first timing signal. The first terminal of the third transistor is used to connect to the first terminal of the second transistor and the pixel unit. The second terminals of the first transistor and the second terminal of the second transistor are both used to input a first low-level signal. The first control terminal of the adjustment module is used to output a first negative level when receiving a negative level signal. The second control terminal of the adjustment module is also used to output a first positive level when receiving a positive level signal. The absolute value of the first negative level is less than a preset proportion of the first positive level.
[0034] Optionally, the (n-4)th level signal is the input signal of this level, the (n+4)th level signal is the reset signal of this level, the first positive level is a constant high voltage signal, which can be set to 17V, and the first negative level is a reference voltage, which can be adjusted according to the gate-source voltage difference of the first transistor 201 and the second transistor 202.
[0035] Optionally, in this application, the control terminal is the gate, the first terminal is the source, and the second terminal is the drain. Optionally, the transistor includes an N-type transistor and a P-type transistor, with the source and drain of the N-type transistor and the P-type transistor being opposite.
[0036] The first signal is input through the input terminal of the adjustment module. The output terminal of the adjustment module is connected to the control terminals of the first transistor and the second transistor. The first terminal of the first transistor is connected to the control terminal of the third transistor. The second terminal of the third transistor is used to input the first timing signal. The first terminal of the third transistor is used to connect to the first terminal of the second transistor and the pixel unit. The second terminals of the first transistor and the second terminal of the second transistor are used to input the first low-level signal. The first control terminal of the adjustment module is used to output the first negative level when receiving the negative level signal. The second control terminal of the adjustment module is also used to output the first positive level when receiving the positive level signal. The absolute value of the first negative level is less than a preset proportion of the first positive level. The adjustment module outputs the first positive level and the first negative level according to the positive and negative level signals received by the control terminal. The absolute value of the first negative level is less than a preset proportion of the first positive level. Since the output terminal of the adjustment module is connected to the control terminals of the first transistor and the second transistor, it can avoid the control terminals of the first transistor and the second transistor from working at the first positive level voltage for a long time, reduce the threshold voltage drift of the first transistor and the second transistor, and extend the working life of the first transistor and the second transistor.
[0037] In one possible example, the adjustment module includes a first adjustment transistor and a second adjustment transistor. The control terminal of the first adjustment transistor is used to input a signal of level n+4. The control terminal of the second adjustment transistor is also used to input a signal of level n+4. The first adjustment transistor is used to output a first negative level when it receives a negative level signal at its control terminal. The second adjustment transistor is used to output a first positive level when it receives a positive level signal at its control terminal. The second terminal of the first adjustment transistor is used to input a first signal. The first terminal of the first adjustment transistor and the first terminal of the second adjustment transistor are both connected to the control terminals of the first and second transistors.
[0038] Optional, please refer to Figure 6 and Figure 7 , Figure 6 The first negative level reference margin range is mainly measured by the minimum gate-source voltage difference of the first transistor 201 and the second transistor 202. Optionally, the minimum voltage of the first negative level in the figure is -3V. Figure 7 This is the high-level reference margin when the first negative level is set to -3V. Optionally, the high-level reference margin is 17 to 12V, which is within the normal operating range.
[0039] The control terminal of the first regulating transistor receives the (n+4)th level signal, and the control terminal of the second regulating transistor also receives the (n+4)th level signal. The first regulating transistor outputs a first negative level when it receives a negative level signal, and the second regulating transistor outputs a first positive level when it receives a positive level signal. The second terminal of both the first and second regulating transistors is used to input the first signal. The first and second terminals of both transistors are connected to their respective control terminals. Since the first regulating transistor outputs a first negative level when it receives a negative level signal, and the second regulating transistor outputs a first positive level when it receives a positive level signal, precise switching between the first negative and first positive levels can be achieved using the same (n+4)th level signal. This avoids circuit malfunctions caused by level output deviations and improves the stability and accuracy of the drive circuit.
[0040] In one possible example, please refer to Figure 8 and Figure 9 The adjustment module includes a third adjustment transistor and a fourth adjustment transistor. The control terminals of the third and fourth adjustment transistors are both used to input a first timing signal. The first timing signal includes a negative level signal and a positive level signal. The third adjustment transistor is used to output a first positive level when it receives a negative level signal at its control terminal. The fourth adjustment transistor is used to output a first negative level when it receives a positive level signal at its control terminal. The second terminal of the third adjustment transistor is used to input the first positive level, and the second terminal of the fourth adjustment transistor is used to input the first negative level. The first terminals of the third and fourth adjustment transistors are all connected to the control terminals of the first and second transistors.
[0041] Optional, please refer to Figure 10 Except for the fourth regulating transistor 213, which is a P-type transistor, all the others are N-type transistors. Figure 8 The comparison shows that a second timing signal has been added.
[0042] The first timing signal is input to the control terminals of both the third and fourth regulating transistors, and the second terminals are input to the first positive and first negative levels, respectively. The first terminals are connected to the control terminals of the first and second transistors. The third regulating transistor is used to output the first positive level when it receives a negative level signal at its control terminal, and the fourth regulating transistor is used to output the first negative level when it receives a positive level signal at its control terminal. This enables precise switching between the first negative and first positive levels, avoids circuit malfunctions caused by level output deviations, and improves the working stability and accuracy of the drive circuit.
[0043] In one possible example, the driving circuit further includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. The second terminal of the fourth transistor is used to input a first high-level signal, and the control terminal of the fourth transistor is used to input a level n-4 signal. The first terminal of the fourth transistor is connected to the first terminal of the fifth transistor, the control terminal of the sixth transistor, the first terminal of the seventh transistor, the first terminal of the first transistor, and the control terminal of the third transistor. The control terminal of the fourth transistor is used to input a level n-4 signal, and the control terminal of the fifth transistor is used to input a level n+4 signal. The second terminals of the fifth transistor, the sixth transistor, and the seventh transistor are all used to input a first low-level signal. The first terminal of the sixth transistor is connected to the output terminal of the adjustment module, the control terminal of the first transistor, and the control terminal of the second transistor. The control terminal of the seventh transistor is used to input a reset signal.
[0044] The second terminal of the fourth transistor is used to input the first high-level signal, and the control terminal of the fourth transistor is used to input the (n-4)th level signal. The first terminal of the fourth transistor is connected to the first terminal of the fifth transistor, the control terminal of the sixth transistor, the first terminal of the seventh transistor, the first terminal of the first transistor, and the control terminal of the third transistor. The control terminal of the fourth transistor is used to input the (n-4)th level signal, and the control terminal of the fifth transistor is used to input the (n+4)th level signal. The second terminals of the fifth transistor, the sixth transistor, and the seventh transistor are all used to input the first low-level signal. The first terminal of the sixth transistor is connected to the output terminal of the adjustment module, the control terminal of the first transistor, and the control terminal of the second transistor. The control terminal of the seventh transistor is used to input the reset signal. By using the coordinated control of the (n-4)th level signal, the (n+4)th level signal, and the reset signal, the first terminal of the first transistor and the control terminal of the third transistor can be adjusted. At the same time, the reset signal can control the seventh transistor to clear residual charge in the circuit, prevent driving deviation caused by charge accumulation, improve the driving accuracy and display consistency of the pixel unit, and extend the service life of the driving circuit.
[0045] In one possible example, the driving circuit also includes an eighth transistor, the second terminal of which is used to input a first low-level signal, the control terminal of which is used to input a touch signal, and the first terminal of which is connected to the first terminal of the third transistor, the first terminal of the second transistor, and the pixel unit.
[0046] The second terminal of the eighth transistor is used to input a first low-level signal, and the control terminal of the eighth transistor is used to input a touch signal. The first terminal of the eighth transistor is connected to the first terminal of the third transistor, the first terminal of the second transistor, and the pixel unit. Since the control terminal of the eighth transistor inputs the touch signal, the touch function is realized. The second terminal inputs the first low-level signal, and the first terminal is connected to the first terminal of the third transistor, the first terminal of the second transistor, and the pixel unit, thus realizing the driving function. This configuration realizes the integration of driving function and touch function.
[0047] In one possible example, the adjustment module further includes a first auxiliary transistor and a second auxiliary transistor. The second terminal of the first auxiliary transistor is connected to the control terminal of the first auxiliary transistor and is used to input a first high level. The first terminal of the first auxiliary transistor is connected to the first terminal of the second auxiliary transistor and the control terminal of the first adjustment transistor. The second terminal of the second auxiliary transistor is used to input a first low level signal, and the control terminal of the second auxiliary transistor is used to input the (n+4)th level signal.
[0048] Optional, please refer to Figure 5 It includes a first transistor 201, a second transistor 202, a third transistor 203, a fourth transistor 204, a fifth transistor 205, a sixth transistor 206, a seventh transistor 207, an eighth transistor 208, a first capacitor 209, an adjustment module 21, a first adjustment transistor 210 and a second adjustment transistor 211, a first auxiliary transistor 214 and a second auxiliary transistor 215. The first auxiliary transistor 214 and the second auxiliary transistor 215 constitute an inverter structure. Figure 5 All transistors in the circuit are N-type transistors. The inverter used inverts the (n+4)th level signal input to the first regulating transistor 210, thus eliminating the need for P-type transistors. This structural design does not change the timing operation of the original circuit.
[0049] The adjustment module also includes a first auxiliary transistor and a second auxiliary transistor. The second terminal of the first auxiliary transistor is connected to the control terminal of the first auxiliary transistor and is used to input a first high level. The first terminal of the first auxiliary transistor is connected to the first terminal of the second auxiliary transistor and the control terminal of the first adjustment transistor. The second terminal of the second auxiliary transistor is used to input a first low level signal. The control terminal of the second auxiliary transistor is used to input the (n+4)th level signal. The first auxiliary transistor and the second auxiliary transistor form an inverter, so that the first auxiliary transistor, the second auxiliary transistor and other transistors in the driving circuit are all of the same type, simplifying the complexity of the circuit.
[0050] Optionally, in one possible example, the driving circuit further includes a first capacitor, one end of which is connected to the first terminal of the fourth transistor, the first terminal of the fifth transistor, the control terminal of the sixth transistor, the first terminal of the seventh transistor, the first terminal of the first transistor, and the control terminal of the third transistor, and the other end of which is connected to the first terminal of the eighth transistor, the first terminal of the third transistor, the first terminal of the second transistor, and the pixel unit.
[0051] One end of the first capacitor is connected to the first end of the fourth transistor, the first end of the fifth transistor, the control terminal of the sixth transistor, the first end of the seventh transistor, the first end of the first transistor, and the control terminal of the third transistor. The other end of the first capacitor is connected to the first end of the eighth transistor, the first end of the third transistor, the first end of the second transistor, and the pixel unit. The energy storage and filtering characteristics of the first capacitor are used to stabilize the level signal and effectively suppress level fluctuations and noise interference.
[0052] Optional, please refer to Figure 3 and Figure 4 Before time t3, the (n+4)th stage signal is low voltage, turning on the first regulating transistor of the P-type transistor. The QB point is then connected to the first negative level, determined by the gate-source voltage difference between the first and second transistors. The minimum voltage provided by the first negative level is -3V, which is sufficient to output a normal waveform. That is, when the gate-source voltage difference between the first and second transistors is greater than or equal to 8V, it can normally turn on for reset operation. During the pre-charge phase (times t1 and t2), the QB point can be pulled down more easily than before (from -3V to -11V). At time t3, during the reset phase of this drive circuit, the (n+4)th stage signal is high voltage, and the Q point is normally pulled down to the first low level. The first positive level is input to the QB point, turning on the first and second transistors, pulling down the Q point and the output signal to the first... Low level; because this is the Q point, the stage where the output signal has just been reset, a momentary high voltage needs to be input to the QB point to strongly conduct the first and second transistors and pull down the Q point and the output signal (QB point is 17V); at time t4, the holding stage is the stage where the first and second transistors work for a long time. At this time, the signal of the n+4th stage is low voltage, the first regulating transistor is turned on, and the second regulating transistor is turned off. That is, the first negative level is input to the QB point to reach the control terminals of the first and second transistors (QB point is -3V). At this time, the gate-source voltage difference of the first and second transistors is the minimum of 8V, which is much smaller than the previous 28V. This can prevent the first and second transistors from being under extremely high gate-source voltage difference for a long time, reduce their threshold voltage offset, and extend the working life of the first and second transistors.
[0053] Optional, please refer to Figure 8 and Figure 9The input to point QB is controlled by the first timing signal, which determines the first positive level and the first negative level. Before time t3, i.e., during the pre-charge phase, point Q is at a high level, pulling point QB down to the first low level. At this time, the first and second transistors are off. At time t3, the (n+4)th stage signal is high voltage, pulling point Q down to the first low level. At this time, the first timing signal is low, and the first positive level inputs a high level to point QB. This instantaneously makes the first and second transistors strongly conduct, pulling point Q and the output signal down to the first low level. At time t4 and thereafter, the switching between high and low levels of the first timing signal causes the first negative level and the first positive level to alternately input signals to point QB, causing the voltage at point QB to switch between 17V and -3V. The first and second transistors can still continuously turn on to pull down point Q and the output signal. Their gate-source voltage difference switches between 28V and -8V. Compared to the first and second transistors operating at a gate-source voltage difference of 28V for a long time, this setting can greatly reduce the threshold voltage drift of the first and second transistors and improve their working life.
[0054] Please refer to Figure 11 , Figure 11 This is a flowchart illustrating a driving method provided in an embodiment of this application. Taking the application of this driving method to a display device as an example, the display device may include a server or electronic device. The driving method is applied to the driving circuit described above. The driving circuit includes a first transistor, a second transistor, a third transistor, and an adjustment module. The input terminal of the adjustment module is used to input a first signal, which includes a first negative level and a first positive level. The output terminal of the adjustment module is connected to the control terminals of both the first and second transistors. The first terminal of the first transistor is connected to the control terminal of the third transistor. The second terminal of the third transistor is used to input a first timing signal. The first terminal of the third transistor is connected to both the first terminal of the second transistor and a pixel unit. The second terminals of both the first and second transistors are used to input a first low-level signal. The driving method includes the following steps S1101-S1102, wherein... S1101: The first control terminal of the adjustment module outputs a first negative level when receiving a negative level signal; S1102: When the second control terminal of the adjustment module receives a positive level signal, it outputs a first positive level, and the absolute value of the first negative level is less than the first positive level of the preset ratio.
[0055] In one possible example, the adjustment module includes a first adjustment transistor and a second adjustment transistor. The control terminal of the first adjustment transistor is used to input the (n+4)th level signal, and the control terminal of the second adjustment transistor is also used to input the (n+4)th level signal. The second terminal of the first adjustment transistor is used to input the first signal, and the first terminal of both the first and second adjustment transistors is connected to the control terminals of both transistors. The method further includes: When the first regulating transistor receives a negative level signal at its control terminal, it outputs a first negative level. When the second regulating transistor receives a positive level signal at its control terminal, it outputs a first positive level.
[0056] In one possible example, the adjustment module includes a third adjustment transistor and a fourth adjustment transistor. The control terminals of both the third and fourth adjustment transistors are used to input a first timing signal, which includes a negative level signal and a positive level signal. The second terminal of the third adjustment transistor is used to input a first positive level signal, and the second terminal of the fourth adjustment transistor is used to input a first negative level signal. The first terminals of the third and fourth adjustment transistors are connected to the control terminals of the first and second transistors, respectively. The method further includes: When the third regulating transistor receives a negative level signal at its control terminal, it outputs a first positive level. When the fourth regulating transistor receives a positive level signal at its control terminal, it outputs the first negative level.
[0057] Please refer to Figure 12 , Figure 12 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 12 As shown, the display device 102 includes a timing controller 1201, a driving circuit 1202, a processor 1203, a memory 1204, and at least one program 1205. The at least one program is stored in the memory and configured to be executed by the processor. The processor controls the timing controller to issue signals. The timing controller is electrically connected to the driving circuit and is used to transmit a first timing signal from the driving circuit to the driving circuit. The program includes instructions for performing the following steps: The first control terminal of the adjustment module outputs a first negative level when receiving a negative level signal; When the second control terminal of the adjustment module receives a positive level signal, it outputs a first positive level, and the absolute value of the first negative level is less than the first positive level of a preset ratio.
[0058] In one possible example, the processor outputs a first negative level when it receives a negative level signal at the control terminal of the first regulating transistor; the processor outputs a first positive level when it receives a positive level signal at the control terminal of the second regulating transistor.
[0059] In one possible example, the processor outputs a first positive level when it receives a negative level signal at the control terminal of the third regulating transistor; and outputs a first negative level when it receives a positive level signal at the control terminal of the fourth regulating transistor.
[0060] Those skilled in the art will understand that, for ease of explanation, Figure 4 Only one memory and processor are shown in the illustration. In a real terminal or server, multiple processors and memories may exist. Memory can also be called storage medium or storage device, etc., and this application does not limit this.
[0061] It should be understood that in this application, the processor can be a Central Processing Unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor can also be a general-purpose microprocessor, graphics processing unit (GPU), or one or more integrated circuits to execute relevant programs to achieve the functions required by the embodiments of this application.
[0062] The processor can also be an integrated circuit chip with signal processing capabilities. In implementation, each step of this application can be completed through integrated logic circuits in the processor hardware or instructions in software form. The aforementioned processor can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The steps of the methods disclosed in the embodiments of this application can be directly manifested as execution by a hardware decoding processor, or execution by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the functions required by the units included in the methods, apparatus, and storage media of the embodiments of this application.
[0063] It should also be understood that the memory mentioned in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Specifically, non-volatile memory can be read-only memory (ROm), programmable read-only memory (PROm), erasable programmable read-only memory (EPROm), electrically erasable programmable read-only memory (EEPROm), or flash memory. Volatile memory can be random access memory (RAm), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRRAM), Synchronous Dynamic Random Access Memory (SDRAm), Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRRAM), Synchlink Dynamic Random Access Memory (SLDRRAM), and Direct Rambus Random Access Memory (DRRAM). The memory can also be a Compact Disc Read-Only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), disk storage media, or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures that can be accessed by a computer, but is not limited thereto. The memory can exist independently and be connected to the processor via a bus. Alternatively, the memory can be integrated with the processor. The memory can store programs, and when the program stored in the memory is executed by the processor, the processor performs the various steps of the method determined in the above embodiments of this application.
[0064] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, the memory (storage module) is integrated into the processor. It should be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.
[0065] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.
[0066] In implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software. The steps of the method disclosed in the embodiments of this application can be directly implemented by a hardware processor, or by a combination of hardware and software modules within the processor. The software modules can reside in mature storage media in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. Since this storage medium is located in memory, the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method; to avoid repetition, these will not be described in detail here.
[0067] Those skilled in the art will recognize that the various illustrative logical blocks (ILBs) and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.
[0068] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented, in whole or in part, as a computer-programmed program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a processor, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic) or wireless (e.g., infrared, wireless, microwave, etc.) means, or from one website, computer, server, or data center to a mobile phone processor via a wired means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive), etc.
[0069] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.
Claims
1. A driving circuit, characterized in that, The system includes a first transistor, a second transistor, a third transistor, and an adjustment module. The input terminal of the adjustment module is used to input a first signal, which includes a first negative level and a first positive level. The output terminal of the adjustment module is connected to the control terminals of the first transistor and the second transistor. The first terminal of the first transistor is connected to the control terminal of the third transistor. The second terminal of the third transistor is used to input a first timing signal. The first terminal of the third transistor is used to connect to the first terminal of the second transistor and a pixel unit. The second terminals of the first transistor and the second transistor are both used to input a first low-level signal. The first control terminal of the adjustment module is used to output the first negative level when receiving a negative level signal. The second control terminal of the adjustment module is also used to output the first positive level when receiving a positive level signal. The absolute value of the first negative level is less than a preset proportion of the first positive level.
2. The driving circuit according to claim 1, characterized in that, The adjustment module includes a first adjustment transistor and a second adjustment transistor. The control terminal of the first adjustment transistor is used to input the (n+4)th level signal, and the control terminal of the second adjustment transistor is used to input the (n+4)th level signal. The first adjustment transistor is used to output the first negative level when it receives the negative level signal at its control terminal, and the second adjustment transistor is used to output the first positive level when it receives the positive level signal at its control terminal. The second terminal of the first adjustment transistor is used to input the first signal, and the second terminal of the second adjustment transistor is used to input the first signal. The first terminal of the first adjustment transistor and the first terminal of the second adjustment transistor are all connected to the control terminals of the first transistor and the second transistor.
3. The driving circuit according to claim 1, characterized in that, The adjustment module includes a third adjustment transistor and a fourth adjustment transistor. The control terminals of the third and fourth adjustment transistors are both used to input the first timing signal. The first timing signal includes the negative level signal and the positive level signal. The third adjustment transistor is used to output the first positive level when it receives the negative level signal at its control terminal, and the fourth adjustment transistor is used to output the first negative level when it receives the positive level signal at its control terminal. The second terminal of the third adjustment transistor is used to input the first positive level, and the second terminal of the fourth adjustment transistor is used to input the first negative level. The first terminals of the third and fourth adjustment transistors are connected to the control terminals of the first and second transistors, respectively.
4. The driving circuit according to any one of claims 1 to 3, characterized in that, The driving circuit further includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. The second terminal of the fourth transistor is used to input a first high-level signal, and the control terminal of the fourth transistor is used to input a level n-4 signal. The first terminal of the fourth transistor is connected to the first terminal of the fifth transistor, the control terminal of the sixth transistor, the first terminal of the seventh transistor, the first terminal of the first transistor, and the control terminal of the third transistor. The control terminal of the fourth transistor is used to input the level n-4 signal, and the control terminal of the fifth transistor is used to input the level n+4 signal. The second terminals of the fifth transistor, the sixth transistor, and the seventh transistor are all used to input the first low-level signal. The first terminal of the sixth transistor is connected to the output terminal of the adjustment module, the control terminal of the first transistor, and the control terminal of the second transistor. The control terminal of the seventh transistor is used to input a reset signal.
5. The driving circuit according to claim 4, characterized in that, The driving circuit further includes an eighth transistor, the second terminal of which is used to input the first low-level signal, the control terminal of which is used to input a touch signal, and the first terminal of which is connected to the first terminal of the third transistor, the first terminal of the second transistor, and the pixel unit.
6. The driving circuit according to claim 5, characterized in that, The adjustment module further includes a first auxiliary transistor and a second auxiliary transistor. The second terminal of the first auxiliary transistor is connected to the control terminal of the first auxiliary transistor and is used to input the first high level. The first terminal of the first auxiliary transistor is connected to the first terminal of the second auxiliary transistor and the control terminal of the first adjustment transistor. The second terminal of the second auxiliary transistor is used to input the first low level signal, and the control terminal of the second auxiliary transistor is used to input the (n+4)th level signal.
7. A driving method, characterized in that, The driving method is applied to a driving circuit as described in any one of claims 1 to 6, the driving circuit comprising a first transistor, a second transistor, a third transistor, and an adjustment module. The input terminal of the adjustment module is used to input a first signal, the first signal including a first negative level and a first positive level. The output terminal of the adjustment module is connected to the control terminals of both the first transistor and the second transistor. The first terminal of the first transistor is connected to the control terminal of the third transistor. The second terminal of the third transistor is used to input a first timing signal. The first terminal of the third transistor is connected to both the first terminal of the second transistor and a pixel unit. The second terminals of both the first transistor and the second transistor are used to input a first low-level signal. The method includes: The first control terminal of the adjustment module outputs the first negative level when receiving a negative level signal. When the second control terminal of the adjustment module receives a positive level signal, it outputs the first positive level, and the absolute value of the first negative level is less than the first positive level of a preset ratio.
8. The driving method according to claim 7, characterized in that, The adjustment module includes a first adjustment transistor and a second adjustment transistor. The control terminal of the first adjustment transistor is used to input the (n+4)th level signal, and the control terminal of the second adjustment transistor is used to input the (n+4)th level signal. The second terminal of the first adjustment transistor is used to input the first signal, and the second terminal of the second adjustment transistor is used to input the first signal. The first terminal of the first adjustment transistor and the first terminal of the second adjustment transistor are all connected to the control terminals of the first transistor and the second transistor. The method further includes: When the first regulating transistor receives the negative level signal at its control terminal, it outputs the first negative level. When the second regulating transistor receives the positive level signal at its control terminal, it outputs the first positive level.
9. The driving method according to claim 7, characterized in that, The adjustment module includes a third adjustment transistor and a fourth adjustment transistor. The control terminals of both the third and fourth adjustment transistors are used to input the first timing signal, which includes the negative level signal and the positive level signal. The second terminal of the third adjustment transistor is used to input the first positive level signal, and the second terminal of the fourth adjustment transistor is used to input the first negative level signal. The first terminals of the third and fourth adjustment transistors are connected to the control terminals of the first and second transistors, respectively. The method further includes: When the third regulating transistor receives the negative level signal at its control terminal, it outputs the first positive level. When the fourth regulating transistor receives the positive level signal at its control terminal, it outputs the first negative level.
10. A display device, characterized in that, It includes a timing controller and a drive circuit as described in any one of claims 1 to 6, wherein the timing controller is electrically connected to the drive circuit and is used to transmit a first timing signal of the drive circuit to the drive circuit.