A multi-exchange structure based parallel switch and data exchange method

Abstract

This invention discloses a switch and data switching method based on parallel multi-switching structures. The switch utilizes multiple switching structures in parallel cooperation, dividing large-scale port data interaction into multiple processing levels. On the input side, a data queue organization method based on output port targets is adopted, completing basic ordering before data enters the switching structure. Furthermore, limited-capacity data temporary storage units are set at key nodes within the switching structure. In addition, the switch employs a concurrent injection and synchronous reception data transmission mechanism, ensuring that data is sent in parallel through multiple switching structures only when the input port accumulates enough data to meet the parallel transmission conditions for the same output port within the same time window. This switch can achieve parallel data transmission and improve switching throughput while ensuring data order consistency, even with a small number of ports and a relatively simple switching structure.

Description

Technical Field

[0001] This invention belongs to the field of computer network and data exchange technology, specifically relating to a switch and data exchange method based on a multi-switching structure in parallel. Background Technology

[0002] With the development of artificial intelligence computing, high-performance computing, and high-speed interconnect technologies, the demand for data exchange between computing devices is constantly increasing. Especially in application scenarios such as accelerator interconnects, board-level interconnects, and on-chip or inter-chip switching, although the overall number of ports is relatively limited, the amount of data to be transmitted per unit time increases significantly, placing higher demands on the throughput and timing controllability of the switching structure. Among existing switches or switching structures, the crossbar switching structure is widely used in switching scenarios with a small number of ports due to its advantages such as simple structure, deterministic path, and fixed delay. A typical crossbar structure uses multiplexing to select one output port for each input port at any given time to establish a direct connection, thereby completing data transmission. When the port size is small, this structure has the advantages of simple implementation and clear control logic.

[0003] However, traditional single-crossbar switching structures have inherent limitations in data concurrency. In any given clock cycle, each input port can typically only send one data transmission to one output port; even if multiple output ports are idle, they cannot be simultaneously utilized by the same input port. This "one-in, one-out" transmission method can easily lead to low utilization of switching resources in applications with a small number of ports but high data flow, limiting further improvements in overall throughput performance.

[0004] To address the limitations of switching structures in terms of throughput and concurrency, a common solution is to increase the overall bandwidth by raising the operating frequency of the switching structure or expanding the data bit width per transmission. For example, increasing the clock frequency of the crossbar switching structure allows for more data exchanges per unit time; or increasing the data channel width carries more data in each transmission. While these solutions can improve peak throughput to some extent, they also introduce problems such as increased power consumption, timing convergence difficulties, and increased physical implementation complexity, especially under high-frequency or large-bit-width conditions, which places high demands on circuit design and manufacturing processes.

[0005] Another solution is to introduce multi-level or multi-plane switching structures, expanding a single switching structure into a multi-level interconnected network, such as a multi-level Clos network or a multi-plane cross-connection structure, to increase the overall number of parallel paths in the system. This type of solution improves overall switching capacity by distributing traffic across different switching levels and is suitable for switching systems with large port counts. However, multi-level switching structures typically require complex scheduling and arbitration mechanisms to avoid path conflicts, and can easily introduce unpredictable transmission delays when data travels through different switching paths. Furthermore, in multi-path or multi-plane switching structures, to ensure data integrity, a reordering mechanism is usually required at the output end to rearrange data from different paths to restore the original data order. This reordering mechanism generally relies on additional buffer resources, sequence number marking, and control logic, which not only increases hardware resource consumption but may also introduce additional processing latency.

[0006] In switching scenarios with a limited number of ports, techniques exist to improve link utilization by setting up multiple queue structures at the input or output ends and combining them with complex arbitration algorithms. However, such techniques often require sophisticated scheduling and control logic, and their implementation complexity is not perfectly matched to the system scale. In applications with a limited number of ports but high requirements for latency and determinism, it is difficult to balance performance and implementation cost.

[0007] The challenge lies in addressing issues such as high implementation complexity, significant risk of data out-of-order processing, or uncontrollable latency when the number of ports is limited and the switching structure should not be overly complex. Summary of the Invention

[0008] The technical problem to be solved by this invention is to provide an improved switch that addresses the shortcomings and deficiencies of existing technologies. This switch can achieve parallel data transmission and improve switching throughput while ensuring data order consistency, even with a small number of ports and a relatively simple switching structure.

[0009] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0010] A switch, the switch comprising multiple input ports, N switching structures, N output ports, and a manager;

[0011] Each input port includes an address resolution module and N data channels that correspond one-to-one with the output port. The input port is configured to receive data packets sent by external devices. The address resolution module is configured to parse the data packets to obtain the target output port and several data units, and to allocate the data units to the data channels corresponding to the target output port.

[0012] When the number of data units arranged in one of the data channels of one of the input ports reaches N, the manager controls the path connection between the data channel and each switching structure so that N data units are sent to the corresponding target output port through each switching structure.

[0013] When the path between the data channel and each switching structure is connected, the parallel transmission of N data units within the data channel can be achieved, thereby realizing parallel data transportation and improving the switching throughput.

[0014] In some implementations, each of the switching structures includes multiple output nodes;

[0015] The manager also categorizes and counts the data units arriving at the output nodes of each switching structure. When the number of data units corresponding to the same target output port reaches N, the manager controls the path connection between each switching structure and the target output port, so that the corresponding target output port synchronously receives N data units. Through this synchronous reception mechanism, data order consistency can be guaranteed, thereby solving the out-of-order problem in the prior art without increasing the complexity of the switching structure.

[0016] In some implementations, each of the switching structures further includes multiple input nodes;

[0017] When the number of data units arranged in one data channel of one of the input ports reaches N, the manager controls the N data units in that data channel to be sent sequentially to the input nodes of each switching structure within multiple consecutive clock cycles in the same time window. Sending N data units in parallel within the same time window enables parallel data transmission, while sending them sequentially within multiple consecutive clock cycles ensures data order. The clock cycles are very short, thus minimizing processing delays.

[0018] In some implementations, each input node and output node is configured with a node cache unit;

[0019] When at least one input node's buffer unit in each switching structure is empty, the manager controls the path connection between the data channel and each switching structure, and writes the data unit into the node buffer unit of that input node. That is, when no data unit is stored in the input node of a switching structure, data units in the data channel can be transmitted to that input node of the switching structure. The manager provides input nodes for data units to be sent in real time and effectively based on the buffer status of the input nodes.

[0020] In some implementations, when a data unit at an input node is transmitted to an output node, the manager clears the node cache unit of the input node and writes the data unit into the node cache unit of the output node.

[0021] When a data unit at an input node is transmitted to the corresponding target output port, the manager clears the node buffer unit of that output node. Within the switching structure, after a data unit is transmitted from the input node to the output node and further to the target output port, the buffers of both the input and output nodes are cleared to promptly increase efficiency for the next write and transmission.

[0022] In some implementations, the manager is pre-configured with input node information tables and output node information tables for each switching structure;

[0023] The input node information table includes the switching structure number where each input node is located, the input port number corresponding to each input node, the output port number corresponding to each input node, and the status of the node buffer unit of each input node.

[0024] The output node information table includes the switching structure number of each output node, the input port number corresponding to each output node, the output port number corresponding to each output node, and the status of the node buffer unit of each output node.

[0025] In some implementations, each of the input ports is provided with an information recording module, which is used to record the information of the data unit when the data unit is written to the node cache unit of the input node;

[0026] The information includes the input port number of the data unit, the target output port number, and the correspondence between the data unit and the switching structure;

[0027] The information recording module reports the information to the manager for management.

[0028] In some implementations, the states of the node buffer units of the input node and the node buffer units of the output node can be as follows:

[0029] Idle state: The node's cache unit is empty and can receive new data units;

[0030] Occupied Status: The node cache unit has already stored data units, and new data units are prohibited from being written to overwrite it;

[0031] Locked state: The data unit in the node buffer unit has reached the available position on the output side, but is temporarily prohibited from being output in advance by the synchronization mechanism of the output port, waiting for data from other switching structures to be sent to the output node to output N data units concurrently.

[0032] In some implementations, the manager sends N data units to input nodes in N switching structures where all N node buffer units are empty, based on the input node information table.

[0033] During synchronous reception, the manager sends reception control information to the target output port;

[0034] The receiving control information includes the input port numbers corresponding to the N data units to be received and the sequential numbering information of the N data units in each switching structure;

[0035] The target output port activates the corresponding switching structure paths in a specific order based on the received control information. This control further ensures data sequence consistency.

[0036] In some implementations, each of the output ports includes a data channel that corresponds one-to-one with the input port;

[0037] The target output port determines the data channel of the corresponding output port to be received based on the input port numbers of N data units;

[0038] Each of the output ports is equipped with a multiplexer;

[0039] The target output port controls the multiplexer to open the corresponding data channel path according to the sequential numbering information of N data units in each switching structure.

[0040] In some implementations, when the path between the data channel and each switching structure is open, each data unit occupies only one input node in each switching structure;

[0041] During the synchronous reception, each output port is connected to one output node in each switching structure.

[0042] In some implementations, N switching structures are set up independently to carry concurrent data transmission from the input ports within the same time window. While physically independent, these N switching structures enable concurrent data transmission.

[0043] In some implementations, when the number of data units arranged in two or more data channels reaches N, the manager first determines the transmission order of the data channels, and then transmits the N data units of the corresponding data channels in parallel to each switching structure according to that order. This further ensures that the data is transmitted in parallel in an ordered manner. The transmission order can be determined based on polling, priority, or a preset strategy, etc.

[0044] In some implementations, each input port is equipped with a quantity detection module, which is used to detect the number of data units arranged in each data channel of the input port in real time. When the number of data units arranged in one of the data channels reaches N, concurrent transmission can be initiated.

[0045] In some implementations, the number of input ports is 2-10. For example, there can be 2, 3, 4, 5, 6, 7, 8, 9, or 10 input ports. The number of input ports may differ from the number of switching structures or the number of output ports. Having a smaller number of input ports does not increase the hardware cost of the switch.

[0046] In some implementations, N is 2-10. The number of switching structures and output ports can be 2, 3, 4, 5, 6, 7, 8, 9, or 10.

[0047] In some implementations, the number of input ports, output ports, and switching structures are the same.

[0048] The present invention also provides a method for data exchange using the aforementioned switch, the method comprising the following steps:

[0049] S1: The input port receives data packets sent by an external device. The address resolution module of the input port parses the data packets to obtain the target output port and several data units, and allocates the data units to the data channel of the input port corresponding to the target output port.

[0050] S2: When the number of data units arranged in one of the data channels of one of the input ports reaches N, the manager controls the path between the data channel and N switching structures to be connected, and sends the N data units to the N switching structures respectively;

[0051] S3: Each switching structure includes multiple output nodes; the manager also classifies and counts the data units arriving at the output nodes of each switching structure. When the number of data units corresponding to the same target output port reaches N, the manager controls the path between each switching structure and the target output port to ensure that the corresponding target output port receives N data units synchronously.

[0052] Due to the application of the above technical solution, the present invention has the following advantages compared with the prior art:

[0053] The data transmission switching architecture of the present invention can achieve parallel data transmission and improve switching throughput while ensuring data order consistency, even with a small number of ports and a relatively simple switching structure.

[0054] This invention can overcome the limitation of concurrency capacity of a single switching structure in the prior art under the condition of low number of ports. In application scenarios with dense data flow, this invention can make full use of the internal bandwidth resources of the switching structure and effectively improve the overall throughput.

[0055] This invention can guarantee the data receiving order at the architecture level under the condition of parallel transmission of multiple switching structures, without the need to introduce reordering buffers and supporting control logic at the output end, thus avoiding reliance on reordering mechanisms and thus not increasing system complexity or causing transmission delay.

[0056] This invention enables the orderly and controllable reception of multiple data streams at the output port in a parallel switching structure, solving the problem of uncontrollable timing of output port reception under parallel conditions in the prior art.

[0057] This invention enables parallel transmission of multiple data in scenarios with a low number of ports without significantly increasing scheduling complexity and hardware resource costs, while ensuring high switching throughput and low cost. Attached Figure Description

[0058] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0059] Figure 1 This is a schematic diagram of a concurrent switch architecture in an embodiment of the present invention;

[0060] Figure 2 This is a schematic diagram of queue management and concurrency logic during data transmission in an embodiment of the present invention. Detailed Implementation

[0061] In application scenarios with a small number of ports but high data exchange density per unit time, the existing switching architecture mainly suffers from the following technical problems.

[0062] First, traditional crossbar-based switching architectures have inherent limitations in concurrent transmission capabilities. These architectures typically employ a single multiplexing mechanism, meaning that within the same clock cycle, each input port can only establish one valid transmission path to an output port. Even if the input port has completed data classification and is capable of sending data to multiple output ports simultaneously, it cannot utilize multiple switching paths in parallel. This "one-time data" transmission mode easily leads to idle bandwidth resources within the switching architecture in scenarios with a low number of ports, thus limiting overall throughput.

[0063] Secondly, when introducing multi-switching or multi-plane structures to improve throughput, existing technologies often struggle to maintain data order consistency. When data is transmitted in parallel through different switching structures and ultimately converges at the same output port, the order in which data arrives at the output port is uncertain due to differences in contention states, arbitration results, and transmission delays along each switching path, easily leading to out-of-order issues. To address this problem, existing technologies typically require additional reordering buffers and control logic at the output end to rearrange the data and restore its original order.

[0064] However, reordering mechanisms themselves incur significant implementation costs. On one hand, reordering requires additional cache resources and sequence number management logic, increasing hardware area and power consumption. On the other hand, the waiting and decision-making operations introduced during the reordering process increase data transmission latency, diminishing the performance gains from parallel transmission. These costs are particularly pronounced in applications with a limited number of ports and high requirements for latency and determinism.

[0065] Finally, existing technologies often lack unified constraints on the timing of data transmission and reception across multiple switching structures. Since data is typically transmitted "through" within the switching structure, once the path is established, the data is immediately forwarded, and the switching nodes themselves lack the ability to regulate the data flow. This makes it difficult to achieve synchronous reception of multiple data streams at the output end in parallel switching structures, further exacerbating out-of-order delivery and arbitration complexity issues.

[0066] Therefore, how to achieve parallel transmission of multiple data in a low-port-count switching scenario without significantly increasing the complexity of the switching structure, while ensuring that the data is received in a predetermined order at the output end without requiring additional reordering, has become a key technical challenge to be solved in the existing technology.

[0067] To address this, the present invention provides a parallel, ordered data transmission switching architecture based on multiple switching structures, and solves the aforementioned technical problems using the following technical means:

[0068] First, this invention introduces a switching architecture design that involves parallel collaboration of multiple switching structures. This invention introduces a hierarchical switching architecture into the switch, dividing the data interaction of large-scale ports into multiple layers for processing. By grouping ports and establishing corresponding data interaction relationships between different layers, data is prioritized for switching within a local area, and then forwarded to a higher layer when needed, thereby adapting to the high-concurrency data interaction requirements between large-scale computing devices.

[0069] Secondly, this invention employs a data queue organization method based on the target output port on the input side. On the input port side, this invention classifies and queues data to be transmitted according to the target output port, ensuring that data from the same output port direction forms an ordered queue on the input side. This method completes basic ordering before the data enters the switching structure, laying the foundation for maintaining data order under subsequent parallel transmission conditions.

[0070] Furthermore, this invention employs a flow control and arbitration mechanism based on data buffer units within the switching structure. This invention sets up capacity-limited data buffer units at key nodes within the switching structure for temporary data storage during parallel switching. These buffer units coordinate the arrival timing of data from different switching structures, enabling parallel data transmission to form a controlled reception rhythm at the output side, rather than being immediately forwarded in a pass-through manner.

[0071] Finally, this invention employs a unique data transmission mechanism based on concurrent injection and synchronous reception. This invention controls the data to be transmitted in parallel via multiple switching structures within the same time window only when the input port side accumulates enough data to meet the parallel transmission conditions for the same output port. On the output port side, data reception is triggered only when data from multiple switching structures arrives at the predetermined reception position, thereby achieving synchronous reception of multiple data streams.

[0072] By employing the above-mentioned technical means, the present invention can achieve parallel transmission of multiple data while embedding sequence control into the switching structure and data receiving mechanism, avoiding reliance on complex scheduling algorithms or high-cost reordering modules, thereby achieving high-concurrency and low-complexity data exchange in scenarios with a low number of ports.

[0073] This invention utilizes multiple parallel switching structures, enabling the same input port to concurrently transmit multiple data units to different switching structures under predetermined conditions. Furthermore, by introducing single-data-unit buffers at the switching nodes in conjunction with an in-order reception mechanism at the output ports, it achieves efficient parallel data transmission and guaranteed sequential consistency without introducing complex global reordering logic. This solution is particularly suitable for high-speed data paths within chips, such as internal switching modules corresponding to high-speed interconnect protocols like PCI Express (PCIe) and Compute Express Link (CXL), as well as on-chip interconnect paths between multi-functional modules.

[0074] The data transmission switching architecture of this invention is applicable to data switching and on-chip interconnection scenarios within integrated circuits, and is particularly suitable for switching systems with a relatively small number of ports but high requirements for concurrent data transmission capabilities, deterministic transmission timing, and hardware implementation complexity. Furthermore, the switching structure of this invention does not rely on large-capacity buffers or complex centralized schedulers; its structure is clear and highly scalable. The number of input ports, output ports, and parallel switching structures can be flexibly configured according to actual application needs, thus making it suitable for on-chip switching systems of different sizes.

[0075] In practical applications, this invention can be used in the data exchange structures within system-on-a-chip (SoC), switching control chips, interconnect bridge chips, and multi-interface control chips to realize data forwarding and scheduling between multiple input ports and multiple output ports. In the above scenarios, after address resolution, data needs to be quickly exchanged within the chip according to the target port. However, traditional single-switch structures are difficult to fully utilize parallel transmission capabilities with a low port scale and are prone to introducing complex reordering and arbitration logic.

[0076] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0077] It should be noted that the terms "comprising" and "having" and any variations thereof in the specification and claims of this invention are intended to cover non-exclusive inclusion. For example, a process, method, apparatus, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such processes, methods, products or devices.

[0078] like Figure 1-2 As shown, this embodiment provides a switch based on a multi-switching structure in parallel, and a data switching method based on the switch.

[0079] The switch includes multiple input ports, N switching structures, N output ports, and a manager. Each input port includes an address resolution module and N data channels corresponding one-to-one with the output port. The input port is configured to receive data packets sent by external devices. The address resolution module is configured to parse the data packets to obtain the target output port and several data units, and allocate the data units to the data channels corresponding to the target output port. When the number of data units arranged in one data channel of one input port reaches N, the manager controls the path connection between that data channel and each switching structure, so that N data units are sent to the corresponding target output port through each switching structure. When the path connection between the data channel and each switching structure is established, parallel transmission of N data units within the data channel can be achieved, thereby realizing parallel data transport and improving the switching throughput.

[0080] Furthermore, each of the aforementioned switching structures includes multiple output nodes. The manager also classifies and counts the data units arriving at the output nodes of each switching structure. When the number of data units corresponding to the same target output port reaches N, the manager controls the path connection between each switching structure and the target output port, so that the corresponding target output port synchronously receives N data units. Through this synchronous reception mechanism, data order consistency can be guaranteed, thereby solving the out-of-order problem in the prior art without increasing the complexity of the switching structure.

[0081] Furthermore, each of the aforementioned switching structures also includes multiple input nodes. When the number of data units arranged in one data channel of one of the input ports reaches N, the manager controls the N data units in that data channel to be sequentially sent to the input nodes of each switching structure within multiple consecutive clock cycles in the same time window. Parallel transmission of N data units within the same time window enables parallel data transmission, while sequential transmission within multiple consecutive clock cycles ensures data order. The clock cycle time is very short, thus minimizing processing delays.

[0082] Furthermore, each input node and output node is configured with a node buffer unit. When at least one input node's node buffer unit in each switching structure is empty, the manager controls the path connection between the data channel and each switching structure, and writes the data unit into the node buffer unit of that input node. That is, when no data unit is stored in the input node of a switching structure, the data unit in the data channel can be transmitted to that input node of the switching structure. The manager provides input nodes for data units to be sent in real time and effectively based on the buffer status of the input nodes.

[0083] Furthermore, when a data unit at an input node is transmitted to an output node, the manager clears the node buffer of the input node and writes the data unit to the node buffer of the output node; when a data unit at an input node is transmitted to the corresponding target output port, the manager clears the node buffer of the output node. Within the switching structure, after a data unit is transmitted from the input node to the output node and further to the target output port, the buffers of both the input and output nodes are cleared to promptly increase efficiency for the next write and transmission.

[0084] Furthermore, the manager is pre-configured with input node information tables and output node information tables for each switching structure. The input node information table includes the switching structure number of each input node, the input port number corresponding to each input node, the output port number corresponding to each input node, and the status of the node buffer unit of each input node. The output node information table includes the switching structure number of each output node, the input port number corresponding to each output node, the output port number corresponding to each output node, and the status of the node buffer unit of each output node. The relevant information for the input and output nodes of each switching structure is uploaded to the manager in a timely manner. The manager manages this information and ensures the consistency of data order after switching output, preventing out-of-order issues.

[0085] Furthermore, each input port is equipped with an information recording module. This module records information about the data unit when it is written to the node buffer of the input node. This information includes the input port number, the target output port number, and the correspondence between the data unit and the switching structure. The information recording module reports this information to the manager for management. After data units are concurrently transmitted to the switching structure, the corresponding information is promptly recorded and reported to the manager.

[0086] Furthermore, the node buffer units of both the input and output nodes have states of idle, occupied, or locked. In the idle state, the node buffer unit is empty and can receive new data units. In the occupied state, the node buffer unit already stores data units, preventing new data units from overwriting them. In the locked state, the data units in the node buffer unit have reached a usable position on the output side, but are temporarily prevented from being output prematurely by the output port's synchronization mechanism, waiting for data from other switching structures to arrive at the output node for concurrent output of N data units.

[0087] Furthermore, based on the input node information table, the manager sends N data units to input nodes in N switching structures where all N node buffer units are empty. During synchronous reception, the manager sends reception control information to the target output port. The reception control information includes the input port numbers corresponding to the N data units to be received and the sequence number information of the N data units in each switching structure. The target output port opens the corresponding switching structure path according to the reception control information in the appropriate order. This control further ensures data sequence consistency.

[0088] Furthermore, each of the output ports includes a data channel that corresponds one-to-one with the input port; the target output port determines the data channel of the corresponding output port to be received based on the input port numbers of the N data units; each of the output ports is provided with a multiplexer; the target output port controls the multiplexer to open the corresponding data channel path in sequence according to the sequential numbering information of the N data units in each switching structure.

[0089] Furthermore, when the data channel is connected to each switching structure, each data unit occupies only one input node in each switching structure; during synchronous reception, each output port is connected to one output node in each switching structure. That is, the switching structure is controlled using node admission levels.

[0090] Furthermore, the N switching structures are set up independently to carry concurrent data transmission from the input ports within the same time window. While physically independent, these N switching structures enable concurrent data transmission.

[0091] Furthermore, when the number of data units arranged in two or more data channels reaches N, the manager first determines the transmission order of the data channels, and then transmits the N data units of the corresponding data channels in parallel to each switching structure according to this order. This further ensures that the data is transmitted in parallel in an ordered manner. The transmission order can be determined based on polling, priority, or a preset strategy, etc.

[0092] Furthermore, each input port is equipped with a quantity detection module, which is used to detect the number of data units arranged in each data channel of the input port in real time. When the number of data units arranged in one of the data channels reaches N, concurrent transmission can be started.

[0093] Furthermore, the number of input ports is 2-10. For example, the number of input ports can be 2, 3, 4, 5, 6, 7, 8, 9, or 10. The number of input ports can be the same as or different from the number of switching structures, and can also be the same as or different from the number of output ports. Preferably, all three are the same. Having a smaller number of input ports does not increase the hardware cost of the switch. The number N of switching structures and output ports can be 2-10, for example, both can be 2, 3, 4, 5, 6, 7, 8, 9, or 10. Having the same number of switching structures and output ports ensures that each switching structure can handle concurrent data transmission, further improving the switch's throughput.

[0094] When using this switch for data exchange, the data exchange method includes the following steps:

[0095] S1: The input port receives data packets sent by an external device. The address resolution module of the input port parses the data packets to obtain the target output port and several data units, and allocates the data units to the data channel of the input port corresponding to the target output port.

[0096] S2: When the number of data units arranged in one of the data channels of one of the input ports reaches N, the manager controls the path between the data channel and N switching structures to be connected, and sends the N data units to the N switching structures respectively;

[0097] S3: Each switching structure includes multiple output nodes; the manager also classifies and counts the data units arriving at the output nodes of each switching structure. When the number of data units corresponding to the same target output port reaches N, the manager controls the path between each switching structure and the target output port to ensure that the corresponding target output port receives N data units synchronously.

[0098] like Figure 1 and Figure 2 As shown, another embodiment of the present invention provides a more detailed parallel switch based on a multi-switching structure and a corresponding data switching method.

[0099] The following embodiments use a switch with 3 input ports, 3 output ports, and 3 switching structures as an example. However, it should be understood that the number of input ports, output ports, and switching structures is merely an example and does not represent a limitation on the number of input ports, output ports, and switching structures in the switch of this invention. The number of input ports, output ports, and switching structures can be adjusted according to actual application requirements.

[0100] like Figure 1As shown, the switch includes 3 input ports, 3 output ports, and 3 switching structures positioned between the input and output ports. The input and output ports are connected according to a predetermined structural rule, forming a parallel data transmission hierarchy with multiple switching structures within the switching system. The 3 switching structures are configured independently to carry concurrent data transmission from the input ports within the same time window.

[0101] The switch consists of an input port processing layer, a parallel transmission layer of the switching structure, and an output port receiving and processing layer. Each layer is responsible for data processing and forwarding at different stages. Thus, with a small number of ports, higher data transmission efficiency can be achieved through the parallel switching structure, and data exchange can be completed while ensuring the consistency of data order.

[0102] The following section details the structure and switching methods of a switch, using the steps outlined in the data exchange process:

[0103] Step 1: Data processing at the input port

[0104] like Figure 1 As shown, the switch includes 3 input ports (input ports *0, *1, *2), 3 output ports (output ports #0, #1, #2), and 3 parallel switching structures (switching structure 0, switching structure 1, switching structure 2).

[0105] Each input port is configured with multiple data queues (data channels) in the direction of the output port, and each data queue (data channel) corresponds to one output port.

[0106] 1.1 Input port data packet reception and address resolution

[0107] Taking input port *0 as an example, when data enters input port *0 from an external device, the address resolution module inside input port *0 first parses the data packet and extracts the target output port number.

[0108] like Figure 1 As shown, after the data packet in input port *0 is parsed, its target output port may be output port #0, output port #1, or output port #2.

[0109] 1.2. Division of the First-Level Switching Domain

[0110] like Figure 1 As shown, input port *0 has at least three data queues internally, labeled as follows:

[0111] Queue #0: Corresponds to output port #0;

[0112] Queue #1: Corresponds to output port #1;

[0113] Queue #2: Corresponds to output port #2.

[0114] When the address resolution module determines that the target output port of a data packet is output port #0, the data packet is split into data units and written into queue #0 of input port *0;

[0115] When the target output port is output port #1 or output port #2, write it into the corresponding queue #1 or queue #2 respectively.

[0116] 1.3 Detection of the number of data units in the input queue

[0117] The input port performs real-time detection of the number of data units in each data queue.

[0118] like Figure 1 As shown in queue #0 of input port *0, when this queue has three consecutive data units buffered (represented by black squares) (i.e., when its number is the same as the number of output ports), the queue is determined to meet the trigger condition for a concurrent transmission. This trigger condition corresponds one-to-one with the three parallel switching structures set in the switch.

[0119] 1.4 Determination of Concurrent Transmission Trigger and Correspondence between Data Units and Switching Structure

[0120] Once queue #0 of input port *0 meets the aforementioned concurrent transmission conditions, input port *0 sequentially retrieves the three data units from queue #0 within multiple consecutive clock cycles in the same time window and sends them to different switching structures in order. For example, the following correspondence can be used, but this is only an example and other correspondences are possible, as long as the three data units are sent to three different switching structures respectively:

[0121] The first data unit is sent to exchange structure 0;

[0122] The second data unit is sent to switching structure 1;

[0123] The third data unit is sent to switching structure 2.

[0124] Specifically, the manager determines the correspondence based on whether the input node buffers in exchange structures 0, 1, and 2 can be written to data units. For example, if there is an empty input node in exchange structure 0, the first data unit can be sent to that input node. Similarly, the second and third data units are sent to the empty input nodes in exchange structures 1 and 2, respectively.

[0125] Although the three data units mentioned above logically constitute a concurrent transmission, they still enter different switching structures in a sequential manner in time, thus forming a concurrent but ordered data entry relationship within the switching system.

[0126] 1.5. Recording and Manager Feedback of Exchanged Structure Sequence Numbers

[0127] During the concurrent transmission process described above, input port *0 records the exchange structure number that each data unit enters, generating exchange structure sequence number information to describe the internal sequence relationship of the three data units in that group.

[0128] This sequence numbering information includes, but is not limited to:

[0129] The corresponding input port number for this concurrent transmission (e.g., input port * 0);

[0130] Target output port number (e.g., output port #0);

[0131] The correspondence between data units and switching structures (e.g., 1st data unit → switching structure 0, 2nd data unit → switching structure 1, 3rd data unit → switching structure 2).

[0132] The aforementioned sequence number information is reported to the manager for unified maintenance and serves as the basis for controlling the internal multiplexer (MUX) of the output port when receiving data in subsequent output ports.

[0133] Specifically, such as Figure 2 As shown, output port #0 sequentially opens its internal receiving channels *0, *1, and *2 according to the sequential numbering information, receiving data units from switching structure 0, switching structure 1, and switching structure 2 respectively, thereby ensuring that data will not be out of order under concurrent transmission conditions.

[0134] 1.6. Arbitration instructions for transmission in multi-queue scenarios

[0135] When multiple queues at input port *0 (such as queue #0 and queue #1) simultaneously meet the concurrent transmission condition (each queue contains at least 3 data units), such as Figure 2 As shown in the process, the input port first determines the sending order, for example, by polling, prioritization, or a preset strategy. Then, it sends data to multiple queues to be sent concurrently according to this order. However, each concurrent transmission is strictly limited to three data units within the same queue to avoid data from different output port directions being mixed and sent, which could disrupt the order.

[0136] Step 2: Composition and Scale Setting of Parallel Switching Structure

[0137] Step two describes the configuration of the parallel switching structure, node buffering, and data buffering and synchronization mechanisms under concurrent transmission conditions. Step two includes the following sub-steps:

[0138] 2.1 The structure and scale of parallel switching architecture

[0139] In this embodiment, the switch is equipped with three independent and parallel switching structures, which are referred to as switching structure 0, switching structure 1 and switching structure 2 respectively.

[0140] Each switching structure is a 3×3 crossbar switching structure, used to implement arbitrary connections between the three input ports and the three output ports.

[0141] The three sets of switching structures mentioned above are physically independent and exist in parallel on the data path, used to carry the parallel transmission of each group of three data units formed in step one.

[0142] 2.2 Connection constraints between input ports and switching structure (single interface occupancy rules)

[0143] To maintain the simplicity and controllability of the switching structure, the connection relationship between the ports and the switching structure is restricted in this embodiment as follows:

[0144] For any input port (input port *0, *1, *2), it is connected to each set of switching structures by only one input interface (input node); that is, input port *i occupies only one input port in switching structure k, and is not allowed to occupy multiple input ports.

[0145] For any output port (output port #0, #1, #2), it is connected to only one output interface (output node) with each set of switching structures; that is, output port #j occupies only one output port in switching structure k, and is not allowed to occupy multiple output ports.

[0146] This connection constraint ensures that each switching structure maintains a fixed port mapping relationship, avoiding structural complexity caused by "the same port occupying the port resources of multiple switching structures".

[0147] 2.3 Setting up single data unit caching at the exchange node (unit caching rules)

[0148] In each switching structure, a node buffer unit is set at the crosspoint between the input and output ports. This node buffer unit is used to store only one data unit. Its storage capacity can be, for example, a single data unit, that is, each node buffer can store at most one data unit to provide storage efficiency. Of course, the storage capacity can also be multiple data units, but only one data unit is allowed to be used at a time. In this case, the storage efficiency will be reduced, resulting in a slight waste of storage space.

[0149] A node cache unit must have at least the following states:

[0150] Idle state: The node cache is empty and can receive new data units;

[0151] Occupied Status: The node cache has already stored data units, and new data units are prohibited from being written to overwrite them;

[0152] Locked state: The data unit in the node buffer unit has reached the available position on the output side, but is temporarily prohibited from being output in advance by the synchronization mechanism of the output port, waiting for data from other switching structures to arrive at the output node to output three data concurrently.

[0153] By introducing a single data buffer at the cross node, data can "stay" within the exchange structure, thus creating conditions for synchronous reception under a parallel structure.

[0154] 2.4 Input-side injection and node cache write control (node-level admission)

[0155] When step one triggers concurrent transmission of a certain output direction queue of a certain input port *i, the three data units are respectively assigned to switching structures 0 / 1 / 2 (the order in which the data from the three input ports are concurrently transmitted to these three switching structures is not consistent), and the target output port is set as output port #j.

[0156] In each switching structure k, the write operation from input port *i to output port #j must satisfy:

[0157] The node cache for the corresponding node (i, j) is in an idle state;

[0158] The switching structure k allows the establishment of a path from input port *i to output port #j during the current clock cycle.

[0159] When the conditions are met, input port *i writes the data unit allocated to the switching structure k into the node cache of node (i, j) in the switching structure k, and sets the node cache status to occupied.

[0160] If the node cache is occupied, the data unit corresponding to the exchange structure k must not be written to, and the input port will remain waiting or the manager will return "non-injectable" feedback to ensure that the node cache is not overwritten.

[0161] 2.5 Node Status Reporting and Manager Status Maintenance (The Foundation of Node Regulation)

[0162] The manager maintains the state information of node caches within the parallel switching structure. Due to the relatively small number of nodes, it provides good control over the nodes along the path. Whenever a node completes a write or release of its cache, the switching structure reports at least the following information to the manager:

[0163] Exchange structure number k (0 / 1 / 2);

[0164] Enter port number *i;

[0165] Target output port number #j;

[0166] Node cache status (idle / occupied / locked).

[0167] Under normal circumstances, the switching structure automatically opens nodes to establish pathways to the target ports that need to be routed to. This routing itself is not congested by the three routing paths. Therefore, based on this basic function, cached data units are used to regulate latency to achieve concurrent data transmission and improve data transfer efficiency. The manager then maintains the node cache status of each switching structure in a unified manner, determining whether any data on the current node's arbitration path is being occupied and affecting transmission, providing a status basis for subsequent synchronous release and sequential reception at the output end.

[0168] 2.6 Synchronization Alignment and Waiting Mechanism for Concurrent Data Groups (Core Node Control)

[0169] For a set of concurrent data sent from the same input port *i to the same output port #j (corresponding to three data units entering switching structures 0 / 1 / 2 respectively), due to the possible differences in the internal propagation speeds of the three switching structures, the following situation may occur:

[0170] The node cache (i, j) of structure 0 is occupied and the data is ready to be output;

[0171] The corresponding node buffer (i, j) of swap structure 1 or swap structure 2 has not yet entered the output state or has not been occupied.

[0172] To avoid data out of order, this embodiment stipulates that the output of the three data units of the output port #j must meet the condition of "all three are present", that is, the three data units of the output port are allowed to enter the output port receiving stage only when the switching structures 0 / 1 / 2 are all in the "output-ready" state at the target node (i, j).

[0173] Therefore, when the node buffer (i, j) of any switching structure k reaches the output state first, the manager puts a lock / wait control on the node buffer, making it enter the locked state and prohibiting the data units of the switching structure k from being output in advance; the manager will only release the lock after the corresponding node buffers of the other two switching structures also reach the output state, allowing the three switching structures to enter the output stage synchronously.

[0174] It is worth noting that the above wait control only applies to the "same concurrent data group on the same output port #j" and does not require global wait.

[0175] 2.7 Principle of Independent Driving to Avoid Blocking Other Output Ports

[0176] When output port #j locks the relevant node cache while waiting for all three to be ready, this locking behavior only applies to:

[0177] The node buffer (·, j) corresponding to output port #j, and the exchange structure number 0 / 1 / 2 associated with this concurrent data group.

[0178] For other output ports (e.g., output port #p, p≠j), the write, output, and release processes of their corresponding node buffers are not affected by the above locking and can still be driven by their own data arrival and reception timing, thereby avoiding the suppression of throughput of other output ports due to the synchronous waiting of a single output port.

[0179] 2.8 Conditions for Node Cache Release and Injection of the Next Set of Data

[0180] Once a data unit in a node's cache is allowed to enter the output port's receive phase and is successfully retrieved, the node's cache state changes from occupied to idle.

[0181] Once the node cache is freed up, the swap structure allows writes to be pushed to that node, thus ensuring data consistency and order controllability under a single-node, single-data-unit cache.

[0182] Step 3: Output port data reception and multiplexing path control

[0183] Step 3 describes the process by which the output port, under the control of the manager, receives concurrent data from multiple switching structures in sequence and writes it into the internal queue of the output port. Step 3 includes the following sub-steps:

[0184] 3.1 Receive control information sent by the output port receiver manager

[0185] When a set of concurrent data corresponding to a certain output port (e.g., output port #j) meets the output conditions in the switching structure, the manager sends receive control information to that output port.

[0186] The received control information includes at least:

[0187] The identifier of the concurrent data group to be received (data packet descriptor, parsed by the address resolution module of the input port);

[0188] The input port number corresponding to the concurrent data group;

[0189] The sequential numbering information of each data unit in the concurrent data group within the exchange structure.

[0190] The sequence number information is used to indicate the opening order of each switching structure path when the output port receives the three concurrent data units in the group.

[0191] 3.2. Output port determines the target receiving queue

[0192] Output port #j has multiple receive queues internally, which are used to buffer data from different input ports.

[0193] After receiving the receive control information from the manager, output port #j determines the receive queue corresponding to the input port number and uses it as the target write queue for this concurrent data group.

[0194] 3.3. The output ports are controlled to open multiplexer channels in the order instructed by the manager.

[0195] Output port #j has an internal multiplexer (MUX) for selecting among multiple switching output paths.

[0196] When receiving concurrent data groups, output port #j controls the multiplexer to open the corresponding path in sequence according to the switching structure sequence number information issued by the manager.

[0197] For example, if the manager instructs that the three data units in the concurrent data group come from switching structure 0, switching structure 1, and switching structure 2 respectively, and their sequential numbering is 0→1→2, then the output port will sequentially open the switching structure 0, 1, and 2 paths corresponding to the multiplexer in the continuous receiving sequence, so that the output port can read data from the corresponding switching structure in a predetermined order.

[0198] 3.4. Ordered reception and writing of concurrent data to the output queue

[0199] During the process of the multiplexer paths being opened sequentially, the output port #j reads data units from the node buffer of the corresponding switching structure and writes the data units sequentially into the target receiving queue determined in step 2 according to the order specified by the manager.

[0200] Because the output ports strictly control the opening order of the channels according to the sequence number provided by the manager, even though the data is transmitted in parallel within the switching system, it is still received at the output ports in the same order as the input ports, thus avoiding the problem of out-of-order data under concurrent transmission conditions.

[0201] 3.5. Receiving completion feedback and releasing node cache status.

[0202] Once output port #j has finished receiving the three concurrent data units in the group and successfully written them into the corresponding receive queue, the output port sends a reception completion feedback message to the manager.

[0203] After receiving the feedback information, the manager updates the status of the node cache in the corresponding exchange structure, restoring the relevant node cache from an occupied or locked state to an idle state, thereby allowing subsequent data to continue to enter the exchange structure for processing.

[0204] The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A switch, characterized by: The switch includes multiple input ports, N switching structures, N output ports, and a manager; Each input port includes an address resolution module and N data channels that correspond one-to-one with the output port. The input port is configured to receive data packets sent by external devices. The address resolution module is configured to parse the data packets to obtain the target output port and several data units, and to allocate the data units to the data channels corresponding to the target output port. When the number of data units arranged in one of the data channels of one of the input ports reaches N, the manager controls the path connection between the data channel and each switching structure so that N data units are sent to the corresponding target output port through each switching structure. Each of the switching structures includes multiple output nodes; the manager also classifies and counts the data units arriving at the output nodes of each switching structure. When the number of data units corresponding to the same target output port reaches N, the manager controls the path between each switching structure and the target output port to be connected, so that the corresponding target output port can simultaneously receive N data units. Each of the aforementioned switching structures also includes multiple input nodes; When the number of data units arranged in one of the data channels of one of the input ports reaches N, the manager controls the N data units in the data channel to be sent sequentially to the input nodes of each switching structure in multiple consecutive clock cycles within the same time window. N switching structures are set up independently to carry concurrent data transmission from the input ports within the same time window.

2. The switch of claim 1, wherein: Each input node and output node is configured with a node cache unit; When at least one input node's node cache unit in each switching structure is empty, the manager controls the path connection between the data channel and each switching structure, and writes the data unit into the node cache unit of that input node.

3. The switch of claim 2, wherein: When a data unit at an input node is transmitted to an output node, the manager clears the node cache unit of the input node and writes the data unit into the node cache unit of the output node. When the data unit at the input node is transmitted to the corresponding target output port, the manager clears the node buffer unit of that output node.

4. The switch of claim 2, wherein: The manager is pre-configured with input node information tables and output node information tables for each switching structure; The input node information table includes the switching structure number where each input node is located, the input port number corresponding to each input node, the output port number corresponding to each input node, and the status of the node buffer unit of each input node. The output node information table includes the switching structure number of each output node, the input port number corresponding to each output node, the output port number corresponding to each output node, and the status of the node buffer unit of each output node.

5. The switch of claim 4, wherein: The manager sends N data units to the input nodes of the N exchange structures, where all N node buffer units are empty, according to the input node information table. During synchronous reception, the manager sends reception control information to the target output port; The receiving control information includes the input port numbers corresponding to the N data units to be received and the sequential numbering information of the N data units in each switching structure; The target output port opens the corresponding switching structure path in a corresponding order according to the received control information.

6. The switch according to claim 5, characterized in that: Each of the output ports includes a data channel that corresponds one-to-one with the input port; The target output port determines the data channel of the corresponding output port to be received based on the input port numbers of the N data units; Each of the output ports is equipped with a multiplexer; The target output port controls the multiplexer to open the corresponding data channel path according to the sequential numbering information of N data units in each switching structure.

7. The switch of claim 1, wherein: When the path between the data channel and each switching structure is connected, each data unit occupies only one input node in each switching structure; During the synchronous reception, each output port is connected to one output node in each switching structure.

8. The switch of claim 1, wherein: When the number of data units arranged in two or more data channels reaches N, the manager first determines the transmission order of the data channels, and then transmits the N data units of the corresponding data channels in parallel to each switching structure according to the order.

9. The switch of claim 1, wherein: Each of the input ports is equipped with a quantity detection module, which is used to detect the number of data units arranged in each data channel of the input port in real time.

10. The switch of claim 1, wherein: The number of input ports is 2-10; and / or, N is 2-10; and / or, the number of input ports, output ports and switching structures are the same.

11. A method for data switching using the switch of any one of claims 1-10, characterized by: The method includes the following steps: S1: The input port receives data packets sent by an external device. The address resolution module of the input port parses the data packets to obtain the target output port and several data units, and allocates the data units to the data channel of the input port corresponding to the target output port. S2: When the number of data units arranged in one of the data channels of one of the input ports reaches N, the manager controls the path between the data channel and N switching structures to be connected, and sends the N data units to the N switching structures respectively; S3: Each switching structure includes multiple output nodes; the manager also classifies and counts the data units arriving at the output nodes of each switching structure. When the number of data units corresponding to the same target output port reaches N, the manager controls the path between each switching structure and the target output port to ensure that the corresponding target output port receives N data units synchronously.

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