Electric field regulated GaN enhancement mode device and method of manufacturing the same
By designing an electric field-controlled GaN enhancement device, combining a lateral gallium nitride structure with a vertical MOS cell, the problem of efficient integration of GaN and MOS devices on the same chip is solved. This achieves a combination of high-frequency and high-speed characteristics with low-power control, improving the device's response speed and reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HANGZHOU SPECTRUM SEMICON TECH CO LTD
- Filing Date
- 2026-03-25
- Publication Date
- 2026-07-21
AI Technical Summary
Existing technologies make it difficult to efficiently integrate GaN power devices and MOS controllers on the same chip to achieve compact, reliable, and easily controllable enhanced power devices, especially when high-frequency and high-performance requirements are difficult to meet.
The structure design of the electric field-modulated GaN enhancement device includes the coordinated layout of the lateral gallium nitride structure and the vertical MOS cell. The two-dimensional electron gas channel is modulated by the P-type gallium nitride layer, and the source and drain are combined with double N-well or double P-well to form ohmic contacts, which supports flexible configuration of NMOS and PMOS device types.
It achieves deep integration of GaN devices and MOS devices, improving response speed, current drive capability and integration density, enhancing threshold voltage stability and anti-interference capability, and reducing control power consumption, making it suitable for high-performance power and RF applications.
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Figure CN121924820B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of gallium nitride semiconductor technology, and in particular to an electric field-modulated GaN enhancement device and its fabrication method. Background Technology
[0002] Currently, gallium nitride (GaN) devices have shown significant advantages in high-frequency and high-power applications, but the realization of their enhancement-mode (normally off) structure usually relies on complex processes, such as grooved gate or P-type GaN gate technology. These methods face challenges in terms of threshold voltage stability, process controllability, and compatibility with existing silicon-based CMOS processes.
[0003] Furthermore, GaN devices alone are inefficient in low-voltage and logic control applications, while traditional silicon-based MOSFETs, although simple to drive, struggle to meet the demands of high frequency and high performance. How to efficiently integrate the high-frequency power characteristics of GaN with the low-power control capabilities of silicon-based MOSFETs on a single chip to achieve a compact, reliable, and easily controllable enhanced power device remains a significant technological challenge. Summary of the Invention
[0004] This invention provides an electric field-controlled GaN enhancement device and its fabrication method to solve existing technical problems. It solves the technical problem of how to efficiently integrate GaN power devices and MOS control devices on the same substrate and realize an electric field-controlled enhancement device with compact structure, normally off operation, high reliability and low control power consumption.
[0005] To solve the above-mentioned technical problems, according to one aspect of the present invention, more specifically, an electric field-controlled GaN enhancement device includes a substrate layer, a MOS cell and a gallium nitride structure located above the substrate layer, and a dielectric layer. The MOS cell has a diffusion layer, a well region, a source region and a MOS gate from bottom to top, wherein the two sides of the MOS gate include a MOS drain and a MOS source, respectively.
[0006] The gallium nitride structure, from bottom to top, includes a buffer layer, a gallium nitride layer, an aluminum gallium nitride barrier layer, and a gallium nitride gate, wherein the gallium nitride gate has a gallium nitride source and a gallium nitride drain on both sides.
[0007] The gallium nitride structure is distributed laterally, the MOS cells are distributed vertically, and the MOS cells are located to the right of the gallium nitride structure.
[0008] The gallium nitride drain is in direct contact with the MOS gate. One side of the gallium nitride source is electrically connected to a metal deposition layer one, and the left side of the MOS source is electrically connected to a metal deposition layer two. Doped silicon is disposed between the metal deposition layer one and the metal deposition layer two.
[0009] Furthermore, the dielectric layer is located between the MOS cell and the gallium nitride structure, the gallium nitride gate and the gallium nitride source, the gallium nitride gate and the gallium nitride drain, the MOS gate and the MOS drain, and the MOS gate and the MOS source.
[0010] The dielectric layer is located between the substrate layer and the first metal deposition layer, the doped silicon, and the second metal deposition layer.
[0011] Furthermore, the gallium nitride gate is located near the gallium nitride source.
[0012] Furthermore, the dielectric layer is located between the gallium nitride gate and the aluminum gallium nitride barrier layer.
[0013] Furthermore, a P-type gallium nitride layer is deposited between the gallium nitride gate and the aluminum gallium nitride barrier layer, and the bottom end of the P-type gallium nitride layer is in direct contact with the aluminum gallium nitride barrier layer, while its top end is in direct contact with the gallium nitride gate.
[0014] Furthermore, the well region in the MOS cell includes a P-well layer, and the source region in the MOS cell includes an N-well layer.
[0015] Furthermore, each MOS cell contains two N-well layers, and the two N-well layers are ohmic contacts with the MOS drain and MOS source, respectively.
[0016] Furthermore, the well region in the MOS cell includes an N-well layer two, and the source region in the MOS cell includes a P-well layer two.
[0017] Furthermore, each MOS cell contains two P-well layers, and the two P-well layers are ohmic contacts with the MOS drain and MOS source, respectively.
[0018] A method for fabricating an electric field-modulated GaN enhancement device specifically includes the following steps:
[0019] S1. A buffer layer, a gallium nitride layer and an aluminum gallium nitride barrier layer are epitaxially grown sequentially on the substrate layer to form a gallium nitride epitaxial structure.
[0020] S2. A gallium nitride gate region is defined on the aluminum gallium nitride barrier layer by photolithography and etching, and a dielectric layer is deposited in the region.
[0021] S3. A gallium nitride gate is fabricated on the dielectric layer, and gallium nitride source and gallium nitride drain are fabricated on the regions located on both sides of the gallium nitride gate on the aluminum gallium nitride barrier layer to form a gallium nitride structure.
[0022] S4. In the region on the right side of the gallium nitride structure on the substrate layer, a diffusion layer is formed by ion implantation or epitaxy, and a well region and a source region are formed in the diffusion layer.
[0023] S5. A MOS drain, a MOS gate, and a MOS source are respectively fabricated on the well region and the source region to form a MOS cell, wherein the MOS gate is in direct contact with the gallium nitride drain.
[0024] S6. A metal deposition layer one is prepared on one side of the gallium nitride source, a metal deposition layer two is prepared on the left side of the MOS source, and doped silicon is disposed between the metal deposition layer one and the metal deposition layer two.
[0025] S7. Deposit a dielectric layer in areas requiring insulation, including areas between MOS cells and gallium nitride structures, between electrodes, and between the substrate layer and the metal deposition layer.
[0026] S8. Perform annealing, planarization, and subsequent interconnection processes to complete the fabrication of the electric field-controlled GaN enhancement device.
[0027] This invention provides an electric field-modulated GaN enhancement device and its fabrication method. Compared with existing technologies, the advantages achieved by this method are:
[0028] 1. This invention achieves deep integration of the two devices in terms of electrical and structural aspects through the synergistic layout of the horizontal gallium nitride structure and the vertical MOS cell. It effectively combines the high-frequency and high-speed characteristics of GaN devices with the low-power control capability of MOS devices, thereby significantly improving the overall device response speed, current drive capability and integration density, and providing a compact and efficient solution for high-performance power and RF applications.
[0029] 2. By introducing a P-type gallium nitride layer between the gallium nitride gate and the aluminum gallium nitride barrier layer, the device of the present invention can form a hole accumulation layer under the gate, effectively modulate the two-dimensional electron gas channel, and realize the normally off enhanced operating mode. This not only improves the stability of the threshold voltage and reduces the gate leakage current, but also enhances the anti-interference capability and reliability of the device under high electric fields, making it more suitable for power switching scenarios with strict requirements for safety and stability.
[0030] 3. This invention optimizes the carrier injection and extraction path by forming an ohmic contact with the source and drain through double N-wells or double P-wells, improves the uniformity of current distribution, reduces on-resistance and hot carrier effect, and enhances the current driving capability and dynamic stability of the cell, which is beneficial for the device to maintain good performance under high current density and high frequency operating conditions.
[0031] 4. This invention supports flexible configuration of the well and source regions in MOS cells, is compatible with both NMOS and PMOS device types, realizes the controllability of carrier types and the adaptability of circuit design, facilitates functional combination and logic expansion in complex integrated circuits, and enhances the diversity and overall reliability of system integration.
[0032] 5. The preparation method provided by this invention is based on mature semiconductor process steps. Through sequential epitaxy, patterning, doping, electrode preparation and dielectric isolation, it realizes the efficient integration of GaN devices and MOS devices on the same substrate. It has good process compatibility, clear and controllable steps, which is conducive to improving the consistency of preparation, yield and feasibility of large-scale production, and has good industrial application prospects. Attached Figure Description
[0033] Figure 1 This is a schematic diagram of the structure of the present invention;
[0034] Figure 2 This is a front sectional view of Embodiment 1 of the present invention;
[0035] Figure 3 This is a front sectional view of Embodiment 2 of the present invention;
[0036] Figure 4 This is a top view of the present invention;
[0037] Figure 5 This is a cross-sectional view of the MOS in Embodiment 3 of the present invention;
[0038] Figure 6 This is a cross-sectional view of the MOS in Embodiment 4 of the present invention.
[0039] In the figure: 1. Substrate layer; 2. MOS cell; 3. Gallium nitride structure; 4. Dielectric layer; 5. Metal deposition layer one; 6. Doped silicon; 7. Metal deposition layer two; 201. Diffusion layer; 202. MOS drain; 203. MOS gate; 204. MOS source; 205. P-well layer one; 206. N-well layer one; 207. N-well layer two; 208. P-well layer two; 301. Gallium nitride source; 302. Gallium nitride gate; 303. Gallium nitride drain; 304. Buffer layer; 305. Gallium nitride layer; 306. Aluminum gallium nitride barrier layer; 307. P-type gallium nitride layer. Detailed Implementation
[0040] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0041] Example 1
[0042] like Figure 1 , Figure 2 , Figure 4As shown, according to one aspect of the present invention, an electric field-modulated GaN enhancement device is provided, including a substrate layer 1, a MOS cell 2 located above the substrate layer 1, a gallium nitride structure 3, and a dielectric layer 4. The MOS cell has a diffusion layer 201, a well region, a source region, and a MOS gate 203 from bottom to top, wherein the MOS gate 203 has a MOS drain 202 and a MOS source 204 on both sides.
[0043] The gallium nitride structure 3 comprises, from bottom to top, a buffer layer 304, a gallium nitride layer 305, an aluminum gallium nitride barrier layer 306, and a gallium nitride gate 302. The gallium nitride gate 302 has a gallium nitride source 301 and a gallium nitride drain 303 on both sides. The gallium nitride structure 3 is laterally distributed, and the MOS cell 2 is vertically distributed, with the MOS cell 2 located on the right side of the gallium nitride structure 3. The gallium nitride drain 303 is in direct contact with the MOS gate 203. One side of the gallium nitride source 301 is electrically connected to a metal deposition layer 5, and the left side of the MOS source 204 is electrically connected to a metal deposition layer 7. A doped silicon 6 is disposed between the metal deposition layer 5 and the metal deposition layer 7.
[0044] In this embodiment, dielectric layer 4 is located between MOS cell 2 and gallium nitride structure 3, gallium nitride gate 302 and gallium nitride source 301, gallium nitride gate 302 and gallium nitride drain 303, MOS gate 203 and MOS drain 202, and MOS gate 203 and MOS source 204; dielectric layer 4 is located between substrate layer 1 and metal deposition layer 5, doped silicon 6, and metal deposition layer 7. Gallium nitride gate 302 is located near gallium nitride source 301. Dielectric layer 4 is also located between gallium nitride gate 302 and aluminum gallium nitride barrier layer 306.
[0045] By employing a laterally distributed gallium nitride structure 3 and a vertically distributed MOS cell 2 in a coordinated layout, and achieving electrical coupling through direct contact between the gallium nitride drain and the MOS gate, while using a metal deposition layer and doped silicon to connect the gallium nitride source and the MOS source.
[0046] This design achieves an effective combination of the high-frequency and high-speed characteristics of GaN devices and the low-power control capabilities of MOS devices through structural integration and direct interconnection. This improves the overall device response speed, driving capability, and integration, while reducing parasitic effects and process complexity.
[0047] Example 2
[0048] like Figure 3As shown, an electric field-modulated GaN enhancement device includes a substrate layer 1, a MOS cell 2 located above the substrate layer 1, a gallium nitride structure 3, and a dielectric layer 4. The MOS cell has a diffusion layer 201, a well region, a source region, and a MOS gate 203 from bottom to top. The MOS gate 203 has a MOS drain 202 and a MOS source 204 on both sides. The gallium nitride structure 3 has a buffer layer 304, a gallium nitride layer 305, an aluminum gallium nitride barrier layer 306, and a gallium nitride gate 302 from bottom to top. The gallium nitride gate 302 has a gallium nitride source 301 and a gallium nitride drain 303 on both sides.
[0049] In this embodiment, a P-type gallium nitride layer 307 is deposited between the gallium nitride gate 302 and the aluminum gallium nitride barrier layer 306, and the bottom end of the P-type gallium nitride layer 307 is in direct contact with the aluminum gallium nitride barrier layer 306, and its top end is in direct contact with the gallium nitride gate 302.
[0050] By introducing a P-type gallium nitride layer between the gallium nitride gate and the aluminum gallium nitride barrier layer, this layer directly contacts both. Through the carrier modulation effect of the P-type gallium nitride, a hole accumulation layer can be formed under the gate, effectively modulating the two-dimensional electron gas channel, realizing a normally-off enhancement operating mode, significantly improving the threshold voltage stability of the device, reducing gate leakage current, and enhancing anti-interference capability, making it suitable for high-reliability power switching applications.
[0051] Example 3
[0052] like Figure 5 As shown, an electric field-modulated GaN enhancement device includes a substrate layer 1, a MOS cell 2 located above the substrate layer 1, a gallium nitride structure 3, and a dielectric layer 4. The MOS cell has a diffusion layer 201, a well region, a source region, and a MOS gate 203 from bottom to top. The MOS gate 203 has a MOS drain 202 and a MOS source 204 on both sides. The gallium nitride structure 3 has a buffer layer 304, a gallium nitride layer 305, an aluminum gallium nitride barrier layer 306, and a gallium nitride gate 302 from bottom to top. The gallium nitride gate 302 has a gallium nitride source 301 and a gallium nitride drain 303 on both sides.
[0053] In this embodiment, the well region in the MOS cell includes a P-well layer 205, and the source region in the MOS cell includes an N-well layer 206. There are two N-well layers 206 in a single MOS cell, and the two N-well layers 206 are in ohmic contact with the MOS drain 202 and the MOS source 204, respectively.
[0054] The MOS cell structure is optimized by using a P-well layer in the well region and an N-well layer in the source region, and a double N-well layer is set to form ohmic contacts with the MOS drain and source respectively.
[0055] This symmetrical double-well design provides a balanced carrier injection and extraction path, improves current distribution uniformity, reduces on-resistance and hot carrier effects, and enhances the current driving capability and dynamic stability of the cell, making it suitable for high current density operating scenarios.
[0056] Example 4
[0057] like Figure 6 As shown, an electric field-modulated GaN enhancement device includes a substrate layer 1, a MOS cell 2 located above the substrate layer 1, a gallium nitride structure 3, and a dielectric layer 4. The MOS cell has a diffusion layer 201, a well region, a source region, and a MOS gate 203 from bottom to top. The MOS gate 203 has a MOS drain 202 and a MOS source 204 on both sides. The gallium nitride structure 3 has a buffer layer 304, a gallium nitride layer 305, an aluminum gallium nitride barrier layer 306, and a gallium nitride gate 302 from bottom to top. The gallium nitride gate 302 has a gallium nitride source 301 and a gallium nitride drain 303 on both sides.
[0058] In this embodiment, the well region in the MOS cell includes an N-well layer 207, and the source region in the MOS cell includes a P-well layer 208. There are two P-well layers 208 in a single MOS cell, and the two P-well layers 208 are in ohmic contact with the MOS drain 202 and the MOS source 204, respectively.
[0059] This embodiment further expands the device type compatibility of MOS cells by using an N-well layer as the well region and a P-well layer as the source region, and also uses a double P-well layer to achieve ohmic contact with the electrode.
[0060] This complementary well structure supports PMOS behavior, enabling flexible control of carrier types, enhancing the device's compatibility and adaptability in complex circuits, and improving the functional diversity and overall reliability of integrated systems. It is especially suitable for applications requiring bipolar control.
[0061] Example 5
[0062] like Figure 1 As shown, a method for fabricating an electric field-controlled GaN enhancement device specifically includes the following steps:
[0063] S1. A buffer layer 304, a gallium nitride (GaN) layer 305, and an aluminum gallium nitride (AGaN) barrier layer 306 are sequentially epitaxially grown on substrate 1 to form a gallium nitride epitaxial structure. This step is based on the principle of heteroepitaxial growth. The buffer layer achieves lattice matching and stress relief. The GaN layer and the AGaN barrier layer form a heterojunction to create a two-dimensional electron gas channel, providing a high-performance electron transport foundation for GaN devices. It has the advantages of high structural quality and few interface states.
[0064] S2. The gallium nitride gate region is defined on the aluminum gallium nitride barrier layer 306 by photolithography and etching, and a dielectric layer 4 is deposited in the region. This step uses micro-nano patterning technology to accurately locate the gate region. The dielectric layer, as the gate insulating layer, can effectively control the channel electric field and suppress the gate leakage current. It has the characteristics of strong process controllability and excellent insulation performance.
[0065] S3. A gallium nitride gate 302 is fabricated on the dielectric layer 4, and a gallium nitride source 301 and a gallium nitride drain 303 are fabricated on the aluminum gallium nitride barrier layer 306 in the regions on both sides of the gallium nitride gate 302, respectively, to form a gallium nitride structure 3. This step completes the construction of the active region of the GaN device through electrode metallization. The relative positions of the source / drain and the gate optimize the electric field distribution, which has the advantages of low contact resistance and strong current driving capability.
[0066] S4. In the region to the right of the gallium nitride structure 3 on the substrate layer 1, a diffusion layer 201 is formed by ion implantation or epitaxy, and a well region and a source region are formed in the diffusion layer 201. This step realizes the integration of MOS device structure on the same substrate. The carrier type and concentration can be controlled by the doping process, which has the advantages of good process compatibility and high integration.
[0067] S5. Fabricate MOS drain 202, MOS gate 203 and MOS source 204 on the well region and source region respectively to form MOS cell 2, wherein MOS gate 203 is in direct contact with gallium nitride drain 303; this step realizes the electrical coupling between GaN device and MOS device through electrode fabrication and direct interconnection, and uses MOS gate to control GaN drain potential, which has the advantages of fast response speed and simple driving logic.
[0068] S6. A metal deposition layer 5 is prepared on one side of the gallium nitride source 301, and a metal deposition layer 7 is prepared on the left side of the MOS source 204. A doped silicon 6 is placed between the metal deposition layer 5 and the metal deposition layer 7. This step achieves electrical connection and potential balance between the sources of the two devices through metal interconnection and silicon doping, which has the advantages of low connection resistance and uniform current distribution.
[0069] S7. Deposit dielectric layer 4 in the areas requiring insulation, including the areas between MOS cell 2 and gallium nitride structure 3, between each electrode, and between substrate layer 1 and metal deposition layer; this step achieves insulation isolation between the device and the line through the dielectric layer, preventing short circuits and cross interference, and has the advantages of good isolation effect and high reliability.
[0070] S8. Annealing, planarization, and subsequent interconnection processes are performed to complete the fabrication of the electric field-controlled GaN enhancement device. This step activates the dopant through annealing, optimizes the surface morphology through planarization, and enables device extraction through interconnection, comprehensively improving the device's electrical performance and process yield. It has the advantages of stable performance and good fabrication consistency.
[0071] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.
Claims
1. An electric field-modulated GaN enhancement device, comprising a substrate layer (1), a MOS cell (2) located above the substrate layer (1), a gallium nitride structure (3), and a dielectric layer (4), characterized in that: The MOS cell has a diffusion layer (201), a well region, a source region and a MOS gate (203) from bottom to top, wherein the MOS gate (203) has a MOS drain (202) and a MOS source (204) on both sides. The gallium nitride structure (3) has a buffer layer (304), a gallium nitride layer (305), an aluminum gallium nitride barrier layer (306), and a gallium nitride gate (302) from bottom to top, wherein the gallium nitride gate (302) includes a gallium nitride source (301) and a gallium nitride drain (303) on both sides. In this case, on a plane parallel to the substrate, the source and drain electrodes of the gallium nitride structure (3) are laterally distributed, the source and drain electrodes of the MOS cell (2) are vertically distributed, and the MOS cell (2) is located on the right side of the gallium nitride structure (3). The gallium nitride drain (303) is in direct contact with the MOS gate (203). One side of the gallium nitride source (301) is electrically connected to a metal deposition layer one (5), and the left side of the MOS source (204) is electrically connected to a metal deposition layer two (7). A doped silicon (6) is disposed between the metal deposition layer one (5) and the metal deposition layer two (7).
2. The electric field-modulated GaN enhancement device according to claim 1, characterized in that: The dielectric layer (4) is located between the MOS cell (2) and the gallium nitride structure (3), the gallium nitride gate (302) and the gallium nitride source (301), the gallium nitride gate (302) and the gallium nitride drain (303), the MOS gate (203) and the MOS drain (202), and the MOS gate (203) and the MOS source (204); The dielectric layer (4) is located between the substrate layer (1) and the first metal deposition layer (5), the doped silicon (6), and the second metal deposition layer (7).
3. The electric field-modulated GaN enhancement device according to claim 1, characterized in that: The gallium nitride gate (302) is located on the side close to the gallium nitride source (301).
4. The electric field-modulated GaN enhancement device according to claim 1, characterized in that: The dielectric layer (4) is also located between the gallium nitride gate (302) and the aluminum gallium nitride barrier layer (306).
5. The electric field-modulated GaN enhancement device according to claim 1, characterized in that: A P-type gallium nitride layer (307) is deposited between the gallium nitride gate (302) and the aluminum gallium nitride barrier layer (306), and the bottom end of the P-type gallium nitride layer (307) is in direct contact with the aluminum gallium nitride barrier layer (306), and its top end is in direct contact with the gallium nitride gate (302).
6. The electric field-modulated GaN enhancement device according to claim 1, characterized in that: The well region in the MOS cell includes a P-well layer (205), and the source region in the MOS cell includes an N-well layer (206).
7. The electric field-modulated GaN enhancement device according to claim 6, characterized in that: There are two N-well layers (206) in a single MOS cell, and the two N-well layers (206) are in ohmic contact with the MOS drain (202) and the MOS source (204), respectively.
8. The electric field-modulated GaN enhancement device according to claim 1, characterized in that: The well region in the MOS cell includes an N-well layer 2 (207), and the source region in the MOS cell includes a P-well layer 2 (208).
9. The electric field-modulated GaN enhancement device according to claim 8, characterized in that: There are two P-well layers (208) in a single MOS cell, and the two P-well layers (208) are ohmic contacts with the MOS drain (202) and the MOS source (204), respectively.
10. A method for fabricating an electric field-controlled GaN enhancement device, characterized in that, The electric field-controlled GaN enhancement device according to any one of claims 1-9, wherein the fabrication method of the electric field-controlled GaN enhancement device specifically includes the following steps: S1. A buffer layer (304), a gallium nitride layer (305), and an aluminum gallium nitride barrier layer (306) are epitaxially grown sequentially on the substrate layer (1) to form a gallium nitride epitaxial structure; S2. A gallium nitride gate region is defined on the aluminum gallium nitride barrier layer (306) by photolithography and etching, and a dielectric layer (4) is deposited in the region. S3. A gallium nitride gate (302) is prepared on the dielectric layer (4), and a gallium nitride source (301) and a gallium nitride drain (303) are prepared on the aluminum gallium nitride barrier layer (306) in the regions located on both sides of the gallium nitride gate (302) to form a gallium nitride structure (3). S4. In the region on the right side of the gallium nitride structure (3) on the substrate layer (1), a diffusion layer (201) is formed by ion implantation or epitaxial process, and a well region and a source region are formed in the diffusion layer (201); S5. A MOS drain (202), a MOS gate (203), and a MOS source (204) are fabricated on the well region and the source region, respectively, to form a MOS cell (2), wherein the MOS gate (203) is in direct contact with the gallium nitride drain (303); S6. A metal deposition layer one (5) is prepared on one side of the gallium nitride source (301), a metal deposition layer two (7) is prepared on the left side of the MOS source (204), and a doped silicon (6) is provided between the metal deposition layer one (5) and the metal deposition layer two (7). S7. Deposit a dielectric layer (4) in the area requiring insulation and isolation. The dielectric layer (4) is located between the MOS cell (2) and the gallium nitride structure (3), the gallium nitride gate (302) and the gallium nitride source (301), the gallium nitride gate (302) and the gallium nitride drain (303), the MOS gate (203) and the MOS drain (202), and the MOS gate (203) and the MOS source (204). The dielectric layer (4) is located between the substrate layer (1) and the first metal deposition layer (5), the doped silicon (6), and the second metal deposition layer (7). S8. Perform annealing, planarization, and subsequent interconnection processes to complete the fabrication of the electric field-controlled GaN enhancement device.