Semiconductor package with copper-plated source pad and method of manufacturing same
By employing multiple small, separate electroplated copper source pads in the field-effect transistor, the problems of gate bus damage and warping in traditional designs are solved, achieving more stable semiconductor packaging manufacturing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ALPHA & OMEGA SEMICON INT LP
- Filing Date
- 2025-10-20
- Publication Date
- 2026-04-24
Smart Images
Figure CN121925150A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor packaging and fabrication technology, and in particular to a semiconductor package with copper-plated source pads and its manufacturing method. Background Technology
[0002] Traditional field-effect transistors (FETs) have relatively fixed shapes and sizes of unplated source pads. This results in a narrow area surrounding the gate bus, increasing the likelihood of electrical short circuits. Consequently, no protective measures are applied to the gate bus. The gate bus is susceptible to damage from pressure on the source metal clips.
[0003] This invention discloses a semiconductor package with multiple small, separate, electroplated copper source pads. It reduces FET warpage after the electroplating process. It also reduces semiconductor package warpage after chip bonding. The aluminum layer thickness at the wafer top can be reduced from 4-7 micrometers to 2-3 micrometers. Summary of the Invention
[0004] The purpose of this invention is to provide a semiconductor package with copper-plated source pads and a method for manufacturing the same, which can solve the problems of gate bus damage and warping during processing caused by the relatively fixed shape and size of the source pads in traditional field-effect transistors (FETs).
[0005] To achieve the above objectives, the present invention provides a semiconductor package with copper-plated source pads, comprising:
[0006] A lead frame;
[0007] A field-effect transistor (FET) is mounted to a lead frame. The FET includes:
[0008] The top surface of the FET has a gate bus, a gate electrode, and a source electrode, the source electrode comprising:
[0009] The first source pad on the first side of the gate bus; and
[0010] The second source pad on the second side of the gate bus, which is opposite to the first side of the gate bus; and
[0011] The FET has a drain electrode on its bottom surface;
[0012] A copper layer, comprising:
[0013] Two or more copper segments are attached to the top surface of the first source pad;
[0014] Two or more copper segments attached to the top surface of the second source pad; and
[0015] A copper bus segment that covers a predetermined portion of the gate bus and is electrically isolated from the gate bus;
[0016] A source metal clip electrically connects the source electrode to the source pin of the lead frame; and
[0017] A molded package that encloses most of the FET, copper layer, source metal clip, and lead frame.
[0018] Optionally, the semiconductor package further includes:
[0019] A gate copper segment covering the gate electrode.
[0020] Optionally, the semiconductor package further includes:
[0021] The gate metal clip electrically connects the gate electrode to the gate pin of the lead frame.
[0022] Optionally, the semiconductor package further includes:
[0023] Bonding wires that electrically connect the gate electrode to the lead frame.
[0024] Optionally, the copper layer is formed by an electroplating process.
[0025] Optionally, the first source pad, the second source pad, and the gate electrode are not covered by nickel-gold or nickel-palladium-gold.
[0026] Optionally, the area of the top surface of each of the two or more first copper regions accounts for 5% to 25% of the top surface area of the semiconductor package; and
[0027] In the case of two or more second copper regions, the area of the top surface of each copper region accounts for 5% to 25% of the top surface area of the semiconductor package.
[0028] Optionally, the gate bus is directly connected to the gate electrode.
[0029] Optionally, the bus copper segment covers part of the first source pad and part of the second source pad.
[0030] Optionally, the semiconductor package is a metal-oxide-semiconductor field-effect transistor.
[0031] The present invention also provides a method for manufacturing multiple semiconductor packages, the method comprising the following steps:
[0032] Provide a wafer comprising:
[0033] Multiple field-effect transistors, each FET including:
[0034] Located on its top surface are the corresponding gate bus, the corresponding gate electrode, and the corresponding source electrode, the source electrode including:
[0035] A first source pad located on the first side of the gate bus; and
[0036] A second source pad located on the second side of the gate bus, opposite to the first side; and
[0037] The corresponding drain electrode located on its bottom surface;
[0038] A seed layer is formed on the top surface of the wafer;
[0039] A photoresist layer is formed on the top surface of the seed layer;
[0040] Multiple patterned lines and multiple openings are formed in the photoresist layer;
[0041] Electroplating copper on multiple open seed layers, including:
[0042] Two or more first copper regions attached to the top surface of the first source pad;
[0043] Two or more second copper regions attached to the top surface of the second source pad;
[0044] A gate copper region covering the corresponding gate electrode; and
[0045] A bus copper region that covers a predetermined portion of the corresponding gate bus and is electrically isolated from the gate bus;
[0046] Remove residual photoresist layer;
[0047] Remove residual seed layer;
[0048] Grind the back side of the wafer to form a thinned wafer;
[0049] Multiple discrete FETs are formed using a cutting process;
[0050] Multiple discrete FETs are mounted onto the lead frame;
[0051] Install the corresponding source metal clips in multiple source metal clips, and electrically connect the corresponding source electrode of each discrete FET to the lead frame;
[0052] This forms a molded package that encapsulates multiple discrete FETs, a copper-plated layer, multiple source metal clips, and most of the lead frame; and
[0053] Multiple semiconductor packages are formed by applying a cutting and separation process.
[0054] Optionally, the method further includes the following steps:
[0055] After installing the corresponding source metal clip, install the corresponding gate metal clip from the multiple gate metal clips, and electrically connect the corresponding gate electrode of each discrete FET to the lead frame.
[0056] Optionally, the method further includes the following steps:
[0057] After installing the corresponding source metal clips, install the corresponding bonding wires from among multiple bonding wires to electrically connect the corresponding gate electrode of each discrete FET to the lead frame.
[0058] Optionally, the electroplated copper fills multiple openings.
[0059] Optionally, the first source pad, the second source pad, and the corresponding gate electrode are not covered by nickel-gold or nickel-palladium-gold.
[0060] Optionally, the area of the top surface of each of the two or more first copper regions accounts for 5% to 25% of the top surface area of the corresponding semiconductor package; and
[0061] In the case of two or more second copper regions, the area of the top surface of each copper region accounts for 5% to 25% of the top surface area of the corresponding semiconductor package.
[0062] Optionally, each of the multiple semiconductor packages is a metal-oxide-semiconductor field-effect transistor.
[0063] In summary, compared with the prior art, the present invention has the following beneficial effects:
[0064] 1. The semiconductor package with copper-plated source pads and its manufacturing method provided by the present invention have multiple small, separate, copper-plated source pads. It not only improves the warpage problem of FET after electroplating process, but also improves the warpage problem of semiconductor package after chip bonding process.
[0065] 2. The semiconductor package with copper-plated source pads and its manufacturing method provided by the present invention can reduce the thickness of the aluminum layer on the top of the wafer from 4-7 micrometers to 2-3 micrometers. Attached Figure Description
[0066] Figure 1A This is a perspective view of a semiconductor package in an example of the present invention.
[0067] Figure 1B This is a perspective view of another semiconductor package in an example of the present invention.
[0068] Figure 2 A perspective view showing a field-effect transistor (FET) in an example of the present invention.
[0069] Figure 3 This is a perspective view showing a copper-plated FET in an example of the present invention.
[0070] Figure 4 This represents a process flow diagram for developing semiconductor packaging in an example of the present invention.
[0071] Figure 5A In the example of this invention Figure 4 Perspective views of the corresponding steps in the process shown. Figure 5B , 5C 5D, 5E, 5F, 5G, 5H, 5I, 5J, 5K, 5L, 5M and 5N represent cross-sectional views seen from the direction perpendicular to the AA' plane.
[0072] Figure 6A , 6B 6C indicates that in the example of this invention Figure 4 The diagram shows a cross-sectional view of a portion of the process steps, including the gate bonding wires.
[0073] Figure 7A In the example of this invention, Figure 4 Perspective views of the corresponding steps in the process shown. Figure 7B , 7C 7D, 7E, 7F, 7G, 7H, 7I, 7J, 7K, 7L, 7M and 7N represent cross-sectional views seen vertically from the BB' plane. Detailed Implementation
[0074] Figure 1A This is a perspective view of the semiconductor package 100 in an example of the present invention. Figure 1B This is a perspective view showing another semiconductor package 102 in this embodiment of the invention. Semiconductor package 100 is similar to semiconductor package 102. For simplicity and clarity, Figure 1A The molded package 190 is shown in transparent (dashed) form, while... Figure 1B The molded package is not shown in the image. Figure 1A and Figure 1B One difference between them is, Figure 1A Includes gate metal clip 181, and Figure 1B Including bonding wire 183.
[0075] exist Figure 1A and Figure 1B In the semiconductor package 100, a lead frame 120 and a field-effect transistor (FET) 140 are included. Figure 3 The semiconductor package 100 comprises a copper layer 350, a source metal clip 170, and a molded package 190. In one example, the semiconductor package 100 is a metal-oxide-semiconductor field-effect transistor (MOSFET). In another example, the semiconductor package 102 is a MOSFET.
[0076] exist Figure 1A and Figure 1B In the middle, FET140 is mounted to lead frame 120. FET140 has on its top surface... Figure 2The gate bus 252, gate electrode 154, and source electrode 260 in the middle have on their bottom surface Figure 2 The drain electrode in the middle is 289. Figure 2 The gate bus 252 is directly connected to the gate electrode 154.
[0077] exist Figure 2 In this configuration, the source electrode 260 includes a first source pad 262 on a first side 202 of the gate bus 252; and a second source pad 272 on a second side 212 of the gate bus 252, the second side being opposite to the first side of the gate bus 252. The first source pad 262, the second source pad 272, and the gate electrode 154 are exposed through an opening window in the top passivation layer 210. The gate bus 252 is covered by the passivation layer 210.
[0078] In an example of the present invention, Figure 3 The copper layer 350 includes two or more copper segments 362 attached to the top surface of the first source pad 262; two or more copper segments 372 attached to the top surface of the second source pad 272; a gate copper segment 354 attached to the top surface of the gate electrode 154; and a bus copper segment 352 extending from a region of the first source pad near the gate bus to a region of the second source pad near the gate bus. The bus copper segment 352 covers a predetermined portion of the gate bus 252 along its length. The bus copper segment 352 is insulated from the gate bus 252 by a passivation layer 210 covering the gate bus. The bus copper segment 352 is connected to the top surface of the first source pad 262 (on the first side of the gate bus 252) and the top surface of the second source pad 272 (on the second side of the gate bus 252). In one example, the predetermined portion is 50% to 95% of the length of the gate bus 252. In another example, the predetermined portion is 70% to 90% of the length of the gate bus 252. In an example of the invention, Figure 3 The copper layer 350 is formed through an electroplating process. Although Figure 3 The code indicates three copper segments (copper segment 363, copper segment 365, and copper segment 367), but the number of copper segments may vary. Although Figure 3 The diagram shows three copper segments (copper segment 373, copper segment 375, and copper segment 377), but the number of copper segments may vary. Each copper segment is separated from its adjacent counterpart. Small, separated copper segments can reduce FET warpage after the electroplating process. It can also reduce semiconductor package warpage after the chip bonding process.
[0079] Figure 3 The size and thickness of the copper layer 350 may vary. The size and thickness of the copper layer 350 can be adjusted as needed to compensate for the resistance of different clip contact areas for chips of different sizes using clips of the same size.
[0080] In an example of the invention, source clip 170 electrically connects source electrode 260 to lead frame 120. Molded package 190 encloses FET 140, copper layer 350, source clip 170, and a majority portion of lead frame 120. In one example, "majority" means more than 50%.
[0081] In an example of the present invention, the semiconductor package 100 further includes a portion located between the FET 140 and the lead frame 120. Figure 5I Metallization layer 589 in the middle.
[0082] In one example, semiconductor package 100 also includes a gate metal clip 181 that electrically connects the gate electrode 154 to the lead frame 120. Molded package 190 also encloses the gate metal clip 181. In another example, semiconductor package 102 also includes a bonding wire 183 that electrically connects the gate electrode 154 to the lead frame 120. Molded package also encloses the bonding wire 183.
[0083] The first source pad 262, the second source pad 272, and the gate electrode 154 are not covered by nickel-gold (NiAu) or nickel-palladium-gold (NiPdAu). In one example of the invention, the first source pad 262, the second source pad 272, the gate electrode 154, and the gate bus 252 comprise an aluminum layer with a thickness of less than 4 micrometers, preferably 0.5-2.5 micrometers.
[0084] The area of the respective top surface of each of the two or more copper segments 362 ranges from 5% to 25% of the top surface area of the semiconductor package 100. The area of the respective top surface of each of the two or more copper segments 372 also ranges from 5% to 25% of the top surface area of the semiconductor package 100.
[0085] In an example of the invention, for the sake of compactness, the first side surfaces 332 of two or more copper segments 362 are coplanar. The second side surfaces 334 of two or more copper segments 362 are coplanar. The second side surfaces 334 of two or more copper segments 362 are opposite to the first side surfaces 332 of two or more copper segments 362. The first side surfaces 336 of two or more copper segments 372 are coplanar. The second side surfaces 338 of two or more copper segments 372 are opposite to the first side surfaces 336 of two or more copper segments 372. The top side surface of a selective one (copper segment 363) of two or more copper segments 362 and the top side surface of a selective one (copper segment 373) of two or more copper segments 372 are coplanar. The bottom side surface of a selective one (copper segment 367) of two or more copper segments 362 and the bottom side surface of a selective one (copper segment 377) of two or more copper segments 372 are coplanar.
[0086] Figure 4 This illustrates the process flow diagram for developing multiple semiconductor packages in this invention example. Figure 5A , 5B 5C, 5D, 5E, 5F, 5G, 5H, 5I, 5J, 5K, 5L, 5M, and 5N represent Figure 4 Cross-sectional view of the corresponding step in process 400. Figure 5A This represents a perspective view. Figure 5B , 5C 5D, 5E, 5F, 5G, 5H, 5I, 5J, 5K, 5L, 5M, and 5N represent from Figure 5A A cross-sectional view seen perpendicular to the AA' plane. Figure 7A , 7B 7C, 7D, 7E, 7F, 7G, 7H, 7I, 7J, 7K, 7L, 7M, and 7N represent Figure 4 Other cross-sectional views of the corresponding steps in process 400.
[0087] Figure 7A This represents a perspective view. Figure 7B , 7C 7D, 7E, 7F, 7G, 7H, 7I, 7J, 7K, 7L, 7M, and 7N represent from Figure 7A A cross-sectional view seen vertically from the BB' plane. Process 400 can begin with block 402.
[0088] For the sake of brevity, Figure 5A , 5B Only one FET is shown in 5C, 5D, 5E, 5F, 5G, 5H, 5I, 5K, 5L, and 5M, while Figure 5J and 5N Only two FETs are shown in the text. For the sake of brevity, Figure 7A , 7B 7C, 7D, 7E, 7F, 7G, 7H, 7I, 7K, 7L, and 7M represent only one FET, while Figure 7J and 7N Only two FETs are shown in the text.
[0089] In block 402, refer to Figure 5A and Figure 7A A wafer is provided. This wafer includes multiple FETs ( Figure 5A Only one FET 501 is shown in the diagram. FET 501 has a gate bus 552, a gate electrode 554, and a source electrode 560 on its top surface, and a drain electrode 587 on its bottom surface. The gate bus 552 is directly connected to the gate electrode 554.
[0090] The source electrode 560 includes a first source pad 562 on a first side 502 of the gate bus 552; and a second source pad 572 on a second side 512 of the gate bus 552, the second side being opposite to the first side of the gate bus 552. The first source pad 562, the second source pad 572, and the gate electrode 554 are exposed through a window in the top passivation layer 510. The gate bus 552 is covered by the passivation layer 510.
[0091] In block 404, refer to Figure 5B and Figure 7B This forms seed layer 523. Seed layer 523 covers the entire wafer. Block 404 can then proceed to block 406.
[0092] In block 406, refer to Figure 5C and Figure 7C A photoresist layer 527 is formed. Block 406 can then proceed to block 408.
[0093] In block 408, refer to Figure 5D and Figure 7D This creates multiple openings 533 (multiple openings 533 are exposed through a masking process; these openings are where copper plating is intended to take place). Block 408 can then proceed to block 410.
[0094] In block 410, refer to Figure 5E and Figure 7E A copper layer 531 is formed by an electroplating process. The copper layer 531 includes two or more copper segments 762 attached to the top surface of a first source pad 562; two or more copper segments 772 attached to the top surface of a second source pad 572; a gate copper segment 754 attached to the top surface of a gate electrode 554; and a bus copper segment 752 covering a predetermined portion of the gate bus 552 along its length. In one example, the predetermined portion is 50% to 95% of the length of the gate bus 552. In another example, the predetermined portion is 70% to 90% of the length of the gate bus 552. The bus copper segment 752 is insulated from the gate bus 552 by a passivation layer 510 covering the gate bus. In an example of the invention, the width of the bus copper segment 752 extends from a first source pad region near the gate bus to a second source pad region near the gate bus. The bus copper segment 752 may be wide enough to connect to the top surface of the first source pad 562 (on the first side of the gate bus 552) and the top surface of the second source pad 572 (on the second side of the gate bus 552).
[0095] refer to Figure 3 ,although Figure 3 The code indicates three copper segments (copper segment 363, copper segment 365, and copper segment 367), but the number of copper segments may vary. Although Figure 3The diagram shows three copper segments (copper segment 373, copper segment 375, and copper segment 377), but the number of copper segments may vary. Small, separated copper segments can reduce FET warpage after the electroplating process. It can also reduce semiconductor package warpage after the chip bonding process.
[0096] Still referencing Figure 3 In this example of the invention, for the sake of compactness, the first side surfaces 332 of two or more copper segments 362 are coplanar. The second side surfaces 334 of two or more copper segments 362 are coplanar. The second side surfaces 334 of two or more copper segments 362 are opposite to the first side surfaces 332 of two or more copper segments 362. The first side surfaces 336 of two or more copper segments 372 are coplanar. The second side surfaces 338 of two or more copper segments 372 are opposite to the first side surfaces 336 of two or more copper segments 372. The top side surface of a selective one (copper segment 363) of two or more copper segments 362 and the top side surface of a selective one (copper segment 373) of two or more copper segments 372 are coplanar. The bottom side surface of a selective one (copper segment 367) of two or more copper segments 362 and the bottom side surface of a selective one (copper segment 377) of two or more copper segments 372 are coplanar. Block 402 may then proceed to block 404.
[0097] The size and thickness of copper layer 531 may vary. The size and thickness of copper layer 531 can be adjusted as needed to compensate for the resistance of different clip contact areas for chips of different sizes using clips of the same size. Block 410 can then proceed to block 412.
[0098] In block 412, refer to Figure 5F and Figure 7F Remove the photoresist layer 527 to expose the sides of the copper layer 531. Block 412 can then proceed to block 414.
[0099] In block 414, refer to Figure 5G and Figure 7G Remove the seed layer 523, exposing a portion of the top surface 537 of FET 501. Block 414 can then proceed to block 416.
[0100] In block 416, refer to Figure 5H and Figure 7H A grinding process is applied to form a thinned FET503. Block 416 can then be followed by an optional block 418.
[0101] In optional block 418 (shown in dashed lines), refer to Figure 5I and Figure 7I A backside metallization process is applied to form a metallization layer 589. Optional block 418 can then proceed to block 420.
[0102] In block 420, refer to Figure 5J and Figure 7J A dicing process is applied along multiple dicing lines 506 to form multiple discrete devices 507. Block 420 can then proceed to block 422.
[0103] In block 422, refer to Figure 5K and Figure 7K Multiple separate devices 507 are mounted onto a lead frame 520, which includes a clip tray 521 and a chip tray 522. Block 422 can then proceed to block 424.
[0104] In block 424, refer to Figure 5L , Figure 6A and Figure 7L Install multiple source metal clips 791 ( Figure 7L ), multiple gate clips 591 ( Figure 5L ) or bond line 683 ( Figure 6A Multiple source metal clips 791 ( Figure 7L ), multiple gate clips 591 ( Figure 5L ) or bond line 683 ( Figure 6A The copper layer 531 is electrically connected to the lead frame 520. Each source metal clip is connected to one of two or more copper segments 362 and one of two or more copper segments 372 of the copper layer 531. Block 424 may then proceed to block 426.
[0105] In block 426, refer to Figure 5M , Figure 6B and Figure 7M Forming a molded package 590 ( Figure 5M ), Molded package 690 ( Figure 6B ) and molded package 790 ( Figure 7M The molded package 590 encapsulates multiple discrete devices 507, a copper layer 531, and multiple source metal clips 791. Figure 7L ), multiple gate clips 591 ( Figure 5L ), bonding wire 683 ( Figure 6A This includes block 426 and most of the lead frame 520. In one example, "most" means more than 50%. Block 426 can then proceed to block 428.
[0106] In block 428, refer to Figure 5N , Figure 6C and Figure 7N Apply monomerization process. Figure 5N In the process, a monomerization process is performed along multiple dicing lines 598 to cut connected semiconductor packages, forming multiple semiconductor packages 599. Figure 6CIn the process, a monomerization process is performed along multiple dicing lines 698 to cut connected semiconductor packages, forming multiple semiconductor packages 699. Figure 7N In this process, a monomerization process is performed along multiple dicing lines 798 to cut connected semiconductor packages, forming multiple semiconductor packages 799. In an example of the present invention, Figure 5N Multiple semiconductor packages 599, Figure 6C Multiple semiconductor packages 699 and Figure 7N Each of the multiple semiconductor packages in the 799 is a MOSFET.
[0107] Those skilled in the art will recognize that modifications to the embodiments disclosed herein are possible. For example, the total number of source pads may vary. Other modifications may occur to those skilled in the art, all of which are considered to be within the scope of the invention as defined in the claims.
Claims
1. A semiconductor package, characterized in that, include: A lead frame; A field-effect transistor is mounted to a lead frame, the field-effect transistor comprising: The top surface of the field-effect transistor has a gate bus, a gate electrode, and a source electrode, the source electrode comprising: The first source pad on the first side of the gate bus; and The second source pad on the second side of the gate bus, which is opposite to the first side of the gate bus; and The field-effect transistor has a drain electrode on its bottom surface; A copper layer, comprising: Two or more copper segments are attached to the top surface of the first source pad; Two or more copper segments attached to the top surface of the second source pad; and A copper bus segment that covers a predetermined portion of the gate bus and is electrically isolated from the gate bus; A source metal clip electrically connects the source electrode to the source pin of the lead frame; and A molded package that encloses most of the field-effect transistor, copper layer, source metal clip, and lead frame.
2. The semiconductor package as described in claim 1, characterized in that, Also includes: A gate copper segment covering the gate electrode.
3. The semiconductor package as described in claim 2, characterized in that, Also includes: The gate metal clip electrically connects the gate electrode to the gate pin of the lead frame.
4. The semiconductor package as described in claim 1, characterized in that, Also includes: Bonding wires that electrically connect the gate electrode to the lead frame.
5. The semiconductor package as described in claim 1, characterized in that, The copper layer is formed through an electroplating process.
6. The semiconductor package as described in claim 1, characterized in that, The first source pad, the second source pad, and the gate electrode are not covered by nickel-gold or nickel-palladium-gold.
7. The semiconductor package as described in claim 1, characterized in that, In one or more of the first copper regions, the area of the top surface of each copper region accounts for 5% to 25% of the top surface area of the semiconductor package; and In the case of two or more second copper regions, the area of the top surface of each copper region accounts for 5% to 25% of the top surface area of the semiconductor package.
8. The semiconductor package as described in claim 1, characterized in that, The gate bus is directly connected to the gate electrode.
9. The semiconductor package as described in claim 1, characterized in that, The bus copper segment covers part of the first source pad and part of the second source pad.
10. The semiconductor package as claimed in claim 1, characterized in that, The semiconductor package mentioned therein is a metal-oxide-semiconductor field-effect transistor.
11. A method for manufacturing a plurality of semiconductor packages, characterized in that, The method includes the following steps: Provide a wafer comprising: Multiple field-effect transistors, each field-effect transistor comprising: Located on its top surface are the corresponding gate bus, the corresponding gate electrode, and the corresponding source electrode, the source electrode including: A first source pad located on the first side of the gate bus; and A second source pad located on the second side of the gate bus, opposite to the first side; and The corresponding drain electrode located on its bottom surface; A seed layer is formed on the top surface of the wafer; A photoresist layer is formed on the top surface of the seed layer; Multiple patterned lines and multiple openings are formed in the photoresist layer; Electroplating copper on multiple open seed layers, including: Two or more first copper regions attached to the top surface of the first source pad; Two or more second copper regions attached to the top surface of the second source pad; A gate copper region covering the corresponding gate electrode; and A bus copper region that covers a predetermined portion of the corresponding gate bus and is electrically isolated from the gate bus; Remove residual photoresist layer; Remove residual seed layer; Grind the back side of the wafer to form a thinned wafer; Multiple discrete field-effect transistors are formed using a cutting process; Multiple discrete field-effect transistors are mounted onto a lead frame; Install the corresponding source metal clips in multiple source metal clips, and electrically connect the corresponding source electrode of each discrete field-effect transistor to the lead frame; This forms a molded package that encapsulates multiple discrete field-effect transistors, a copper-plated layer, multiple source metal clips, and most of the lead frame; and Multiple semiconductor packages are formed by applying a cutting and separation process.
12. The method as described in claim 11, characterized in that, It also includes the following steps: After installing the corresponding source metal clip, install the corresponding gate metal clip from the multiple gate metal clips, and electrically connect the corresponding gate electrode of each discrete field-effect transistor to the lead frame.
13. The method as described in claim 11, characterized in that, Further steps include: After installing the corresponding source metal clips, install the corresponding bonding wires from among multiple bonding wires to electrically connect the corresponding gate electrode of each discrete field-effect transistor to the lead frame.
14. The method as described in claim 11, characterized in that, Electroplated copper fills multiple openings.
15. The method as described in claim 11, characterized in that, The first source pad, the second source pad, and the corresponding gate electrode are not covered by nickel-gold or nickel-palladium-gold.
16. The method as described in claim 11, characterized in that, In one or more of the first copper regions, the area of the top surface of each copper region accounts for 5% to 25% of the top surface area of the corresponding semiconductor package; and In the case of two or more second copper regions, the area of the top surface of each copper region accounts for 5% to 25% of the top surface area of the corresponding semiconductor package.
17. The method as described in claim 11, characterized in that, Each of the multiple semiconductor packages is a metal-oxide-semiconductor field-effect transistor.