A timing-aware automated replacement method for circuit multi-threshold camouflaged cells

Abstract

The present application belongs to the field of integrated circuit security design, and relates to a timing-aware automatic replacement method for a circuit multi-threshold camouflage unit, comprising: obtaining an original circuit design netlist after layout and routing are completed, and a timing path set obtained through timing analysis, and setting a quantity constraint for replacement of the camouflage unit; constructing a multi-objective optimization model through a Lagrange multiplier method with maximization of circuit security as a target and the timing path and the quantity of replacement of the camouflage unit as constraints; solving the multi-objective optimization model through a hybrid algorithm combining constraint programming and simulated annealing to determine a logical node set in the circuit to be replaced by the multi-threshold camouflage unit; and replacing the multi-threshold camouflage unit in the circuit according to the logical node set. The present application is mainly applied to the post-engineering change stage of safety-critical chips, can improve the physical security of the chips without sacrificing the timing performance, and is fully compatible with mainstream electronic design automation tool chains.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit security design and relates to a timing-aware automated replacement method for multi-threshold spoofing units in circuits. Background Technology

[0002] Physical camouflage technology, as a proactive defense mechanism, obfuscates the mapping between layout structure and logical functions, becoming a key line of defense for protecting the core design secrets of chips. Multi-threshold camouflage units are logic gates that utilize multi-threshold transistors to achieve hardware camouflage effects.

[0003] The core of the multi-threshold camouflage unit lies in its physically indistinguishable design. All two-input basic logic units adopt the exact same physical layout, defining logic functions only through differences in the threshold voltage injection regions. In its implementation, the multi-threshold camouflage unit employs a symmetrical differential pull-down network structure. By changing the threshold voltage of the transistors, the same physical layout can implement all 16 types of two-input Boolean logic functions, including NAND2, NOR2, and XOR2, completely eliminating the possibility of distinguishing logic functions through layout imaging. Furthermore, the multi-threshold camouflage unit can be integrated as a standard combinational logic unit. During design, the layout is drawn according to standard cell specifications, and standard cell library files, including LEF and LIB library files, are extracted, allowing it to be directly used as a standardized unit in tools.

[0004] Despite the significant advantages of multi-threshold masquerading units in hardware security, their application in practical chip design still faces major challenges. Traditional masquerading unit replacement methods have bottlenecks; the placement of masquerading gates in the circuit relies entirely on engineer experience, making it difficult to scientifically balance security and timing performance, often leading to timing violations on critical paths or insufficient security coverage.

[0005] These limitations are particularly evident in complex ASIC design practices. For example, in the design of cryptographic chips, randomly replacing logic gates on the critical path may lead to setup time violations due to the special timing characteristics of the spoofing gates; while conservatively choosing to replace non-critical nodes makes it difficult to effectively protect sensitive areas such as key scheduling logic. Summary of the Invention

[0006] To address the aforementioned technical problems in the existing technology, this invention proposes a timing-aware automated replacement method for circuit multi-threshold masquerading units, the specific technical solution of which is as follows:

[0007] A timing-aware automated replacement method for multi-threshold masquerading units in a circuit includes the following steps:

[0008] Obtain the original circuit design netlist after placement and routing, and the timing path set obtained through static timing analysis. Set timing path constraints, wherein the timing overhead introduced by dummy cell replacement does not exceed the original margin of the corresponding timing path, and set the number of dummy cell replacements.

[0009] With the goal of maximizing circuit security and reducing the timing overhead introduced by camouflage unit replacement, a target optimization model is constructed with timing path constraints and camouflage unit replacement quantity constraints.

[0010] A hybrid algorithm combining constraint programming and simulated annealing is used to solve the target optimization model to determine the set of logic nodes in the circuit to be replaced with multi-threshold camouflage units, thus obtaining the optimal replacement solution.

[0011] Based on the optimal replacement solution, the replacement of multi-threshold masquerading units is performed in the circuit to obtain the ECO netlist.

[0012] Furthermore, when constructing the target optimization model, the timing path constraint and the constraint on the number of masquerading units are represented as penalty terms, the maximization of circuit security is represented as a security evaluation function, and the penalty terms and the security evaluation function are weighted and fused together using the Lagrange multiplier method to construct the target function.

[0013] Furthermore, the security evaluation function is constructed by integrating the logical function security metric, structural security metric, and positional contribution of nodes in the timing path of the original circuit design netlist, and the security evaluation function is used to quantify and score each node in the netlist.

[0014] Furthermore, the logical function security metric of the node is determined by the number of function mappings, the inconsistency coefficient, and the unit-level security complexity. The unit-level security complexity is determined by the functional coverage capabilities of the multi-threshold masquerading unit.

[0015] Furthermore, the constraint planning involves performing a temporal path constraint check on the current replacement solution. Specifically, it calculates the margin of all temporal paths corresponding to logical nodes in the current replacement solution. When the margin of any temporal path is lower than a preset value, it is determined to be a logical node that violates the temporal path constraint, and pruning is performed to exclude it from the current replacement solution.

[0016] Furthermore, a random perturbation operation is performed on the pruned replacement solution. Specifically, one selected camouflage unit is replaced with another candidate unit, and after generating a new replacement solution, the temporal path constraint check is continued.

[0017] Furthermore, the simulated annealing specifically involves: performing global optimization on the new replacement solution obtained after constrained programming, and accepting or rejecting the updated replacement solution according to the Monte Carlo criterion.

[0018] Furthermore, the timing, functional, and physical verification of the circuit design netlist after replacement based on the optimal replacement solution is performed.

[0019] Furthermore, the functionality was verified using the Formality tool to compare the consistency of the original functionality with the replaced netlist design in terms of functional behavior.

[0020] Furthermore, physical verification employs design rule checks and layout / circuit verification. Figure 1 Consistency test.

[0021] Beneficial effects:

[0022] This invention employs a hybrid algorithm combining constraint programming and simulated annealing, which significantly improves the search efficiency and optimality of the solution space, ensuring a better balance between security and temporal integrity in camouflage gate insertion.

[0023] The method of this invention covers a complete automated path from node identification, netlist update, physical routing to post-simulation verification, ensuring that each replaced logical node can be implemented accurately, efficiently and securely in the layout.

[0024] Through the process proposed in this invention, engineers can quickly deploy multi-threshold camouflage units without manually intervening in the physical implementation details, effectively addressing the physical security enhancement requirements in later engineering changes.

[0025] This invention can be applied to the later engineering change stage of safety-critical chips. It can fully make the highly confidential camouflage structure compatible with mainstream EDA processes without introducing additional clock logic or layout disturbances, taking into account security, timing integrity and design feasibility, and providing a quantifiable and automated solution for chip physical security deployment. Attached Figure Description

[0026] Figure 1 This is a flowchart of a timing-aware automated replacement method for a circuit multi-threshold masquerading unit according to an embodiment of the present invention;

[0027] Figure 2 This is a schematic diagram of the automated ECO implementation process that invokes the method of this invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and technical effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0029] like Figure 1 As shown, this embodiment discloses a timing-aware automated replacement method for multi-threshold masquerading units in circuits, specifically including the following steps:

[0030] Step 1: First, obtain and input the netlist G of the circuit design after placement and routing. This netlist is the physical structure basis for subsequent optimization operations. Simultaneously, import the set P of all timing paths obtained through Static Timing Analysis (STA) as the object of constraint checking. Pre-set the maximum number K of replacements for multi-threshold dummy cells to limit the replacement scale. Finally, input the Lagrange weights. This parameter is used to balance the proportion of security improvement and timing overhead in the objective function, defining the initial optimization bias.

[0031] Step 2: The objective function L is constructed by combining the security evaluation function and the timing penalty term.

[0032] The security evaluation function comprehensively considers node logical function security metrics, structural security metrics based on controllability and observability indicators, and positional contributions in critical temporal paths, etc., to quantify and score nodes, thus obtaining a security score. The temporal penalty term is obtained by transforming temporal path constraints into Lagrange multiplier form.

[0033] Specifically, to quantify the contribution of camouflage unit replacement to the overall circuit security, we first define the unit-level security complexity of the i-th node, i.e., the candidate camouflage unit, as follows: ,in, The inconsistency coefficient is used to characterize the indistinguishability of input and output between different candidate logic functions; This serves as the lower bound of the functional space dimension. This represents the minimum error tolerance allowed for attackers during the function identification process.

[0034] Furthermore, to reflect the structural importance of logic nodes in the circuit topology, the structural position weight of node i is defined as follows: ,in, , and Let represent the controllability and observability metrics of node i, respectively. For any temporal path p, its path-level security metric is defined as... ,in, For binary decision variables, This represents the structural position weight of the masquerading unit i on the timing path p. Since different paths correspond to parallel propagation branches and cannot be directly linearly added, the overall circuit security evaluation function is defined as follows: .

[0035] The timing penalty term represents the timing overhead introduced by masquerading unit replacement and participates in the construction of the objective function through Lagrange weights. Based on the aforementioned security evaluation function and constraints, the objective function of the objective optimization model is constructed as follows: , Represents a set of logical nodes.

[0036] For each candidate spoofing unit in the time-series path set P, calculate its sensitivity Sensi, expressed as follows: ,in It is the structural position weight of the camouflage unit; It is the unit-level security complexity, determined by the 16 functional coverage capabilities of the multi-threshold camouflage unit; It is the delay increment after replacing the unit; This represents the partial derivative of the objective function L with respect to the decision variables; This represents a small change in the binary decision variable xᵢ.

[0037] All candidate units are sorted from highest to lowest Sensi. A higher Sensi indicates a higher cost-effectiveness in terms of security improvement and timing overhead. This generates an initial replacement set, providing a high-quality starting point for subsequent iterations.

[0038] Step 3: Initialize the initial temperature T0 and the minimum temperature threshold Tmin of the simulated annealing (SA), with T0 set to 10.0 and Tmin set to 0.01; determine whether the current temperature T is less than Tmin: if it is, it means that the algorithm has converged sufficiently and the optimal replacement scheme is directly output; if it is not, proceed to the random perturbation stage of the constraint planning (CP) module in step 4.

[0039] Step 4: Analyze the logical node set of the current replacement scheme. Perform a random perturbation operation, specifically by replacing one selected camouflage unit with another candidate unit to generate a new replacement scheme, that is, to generate a new solution and expand the solution space accordingly, thereby avoiding getting trapped in local optima.

[0040] Step 5: Calculate the slack of all timing paths corresponding to the new solution. If any path does not satisfy... This indicates that the new solution violates the temporal path constraint, so the solution is directly excluded, and we return to step 4 to regenerate a new solution, where the set Includes all replaced masquerade units on path p. A flag is set to 1 if the i-th unit is masqueraded, and 0 otherwise; if all paths satisfy... This indicates that the new solution meets the timing requirements, and then it enters the Monte Carlo (Metropolis) criterion judgment stage of the simulated annealing (SA) module.

[0041] Step 6: Calculate the objective function increment ΔL between the new solution and the current optimal solution, and determine whether to accept the new solution based on the Metropolis criterion: If the increment is positive, it means that the overall benefit of the new solution is better, so it is accepted directly; if the increment is negative, in order to avoid getting trapped in a local optimum, the inferior solution will be accepted with probability p=exp(ΔL / T) based on the Metropolis criterion.

[0042] Step 7: If the new solution passes the Metropolis criterion, update the current optimal solution and record the set of replacement units, objective function value, and time margin data corresponding to the solution; if it fails, do not update and keep the current optimal solution.

[0043] Step 8: Update the temperature according to the cooling formula: T←T×α, where α is the cooling coefficient, usually taken as 0.95~0.995. By gradually reducing the temperature, the random disturbance amplitude in the later iterations is reduced, guiding the algorithm to converge toward the global optimal solution.

[0044] Step 9: When the temperature T passes the termination condition, the final optimal replacement scheme is output as the basis for the execution of multi-threshold masquerading unit replacement in the subsequent ECO process.

[0045] In summary, the core innovation of this invention lies in: constructing an objective optimization model using the Lagrange multiplier method, unifying the security maximization objective with temporal path constraints and replacement quantity constraints into a formal modeling framework; firstly, constructing an initial replacement set based on the sensitivity of camouflage unit nodes in the circuit design netlist; and then efficiently solving the problem using a hybrid algorithm of Constraint Programming (CP) and Simulated Annealing (SA). Specifically, the constraint programming mechanism performs temporal consistency checks on the nodes in the replacement set and prunes solutions that violate constraints. Based on this, a global search is performed using a simulated annealing strategy, and a new replacement set is accepted with a certain probability according to the Metropolis criterion based on the objective function increment. Simultaneously, a temperature reduction mechanism is used to gradually converge to the optimal node replacement geometry, thereby systematically finding the optimal balance between security and temporal performance, and achieving globally optimal scheduling for camouflage unit node selection.

[0046] In the initial stage of this invention's algorithm, the industry-standard PrimeTime tool is used to perform static timing analysis on the original circuit design, comprehensively extracting the timing path margin (slack), path delay, and node topology information of each logic gate in the design. Based on this, a candidate pool is selected. After the candidate pool is generated, a multi-dimensional security evaluation function is introduced to quantify and score each node. This security evaluation function comprehensively considers the following factors: the node's logical function security measure, the structural security measure based on controllability and observability indicators, and its positional contribution in critical timing paths. The logical function security measure of a node includes the number of function mappings, the inconsistency coefficient, and the unit-level security complexity. All scores will serve as the core input parameters of the optimization model to ensure the accurate quantification of security benefits. Based on these fundamental data, the timing hard constraints and substitution quantity constraints are transformed into penalty terms using the Lagrange multiplier method, and then weighted and fused with the security evaluation objective to construct a relaxation objective function, forming a multi-objective optimization mathematical model.

[0047] In solving the model of this invention, the constraint programming (CP) module is first used to construct an initial solution based on node sensitivity. Temporal path constraints and replacement quantity constraints are treated as hard constraints. The delay increment introduced by replacement must not exceed the original margin (slack) of each temporal path, and the replacement quantity of camouflage units must not exceed a preset upper limit K. Feasibility checks and pruning are performed on candidate solutions. Based on this, the simulated annealing (SA) module is used for a global search, and new solutions are accepted with a certain probability according to the Metropolis criterion based on the change in the objective function. Simultaneously, a temperature reduction mechanism is used to gradually converge to the optimal solution.

[0048] The Constraint Programming (CP) module efficiently prunes the solution space, quickly eliminating invalid solutions that violate core constraints and narrowing the search range. The Simulated Annealing (SA) module performs global optimization on the filtered feasible solution space and accepts or rejects new solutions according to the Metropolis criterion, avoiding getting trapped in local optima. After each iteration, a delay increment is calculated; if replacing a node causes the margin (Slack) of a critical temporal path to fall below a set value, pruning is performed. The entire process terminates after reaching the target number of camouflage units and satisfying the convergence condition, outputting the final ECO camouflage replacement solution set. This method significantly improves the search efficiency and optimality of the solution space, ensuring a better balance between security and temporal integrity in camouflage gate insertion.

[0049] At the engineering implementation level, to efficiently deploy the aforementioned "Lagrange modeling + CP-SA solution" masquerading node selection scheme into the actual chip design process, such as... Figure 2As shown, this invention designs and implements a complete ECO (Enhanced Operational Coding) process for multi-threshold camouflage units. This process incorporates the timing-aware automated replacement method described in this invention into a camouflage replacement point selection module and invokes it. This module is responsible for selecting the optimal logic node from the original design to replace it with a multi-threshold camouflage unit, thereby achieving the concealment of logic functions and the enhancement of circuit security. Specifically, the automated ECO implementation process is as follows:

[0050] S1: Using the design netlist after the layout and routing (PR) is completed as input, call the masquerade replacement point selection module to filter out the logical nodes that will be replaced with multi-threshold masquerade units.

[0051] S2: Read the generated ECO netlist using EDA tools, import the original layout and perform incremental routing (routeECO) to complete the layout and connection of camouflage units without destroying the original physical structure.

[0052] S3: After ECO placement and routing, the new netlist file is imported into the verification phase as the post-ECO design. It is also used for subsequent timing and functional integrity checks. In the verification phase: First, tools such as PrimeTime are used to perform a complete STA (Standard Operating Procedure) flow on the post-ECO design to ensure that the establishment and hold times of all critical paths meet the original design specifications, verifying that the insertion of dummy gates does not cause functional timing violations. Then, the Formality verification tool is used to compare the functional behavior of the original function and the post-ECO design, ensuring that logic dummy does not introduce logical errors or damage chip functionality. Finally, physical verification is performed, including Design Rule Check (DRC) and layout / circuit verification. Figure 1 LVS (Likelihood and Safety Check).

[0053] S4: After passing multiple verifications of functionality, timing, and physics, the system will export the final layout data as a standard GDS format file, which will be used directly as the back-end physical implementation result for chip manufacturing tape-out.

[0054] The above implementation process is closely integrated with the output of the camouflage replacement point selection module, covering a complete automated path from node identification, netlist update, physical routing to post-simulation verification, ensuring that each replaced logical node can be accurately, efficiently and securely implemented in the layout.

[0055] Through the process proposed in this invention, engineers can quickly deploy multi-threshold camouflage units without manually intervening in the physical implementation details, effectively addressing the physical security enhancement requirements in later engineering changes.

[0056] This invention ultimately enables the integration of highly secure camouflage structures into mainstream EDA processes without introducing additional clock logic or layout disturbances, balancing security, timing integrity, and design feasibility, and providing a quantifiable and automated solution for chip physical security deployment.

[0057] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any way. Although the implementation process of the present invention has been described in detail above, those skilled in the art can still modify the technical solutions described in the foregoing examples or make equivalent substitutions for some of the technical features. All modifications and equivalent substitutions made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A timing-aware automated replacement method for multi-threshold masquerading units in circuits, characterized in that, Includes the following steps: Obtain the original circuit design netlist after placement and routing, and the timing path set obtained through static timing analysis. Set timing path constraints, wherein the timing overhead introduced by dummy cell replacement does not exceed the original margin of the corresponding timing path, and set constraints on the number of dummy cell replacements. With the goal of maximizing circuit security and reducing the timing overhead introduced by camouflage unit replacement, and with timing path constraints and camouflage unit replacement quantity constraints as constraints, a target optimization model is constructed. A hybrid algorithm combining constraint programming and simulated annealing is used to solve the target optimization model to determine the set of logic nodes in the circuit to be replaced with multi-threshold camouflage units, thus obtaining the optimal replacement solution. Based on the optimal replacement solution, a replacement operation of the multi-threshold masquerading unit is performed in the circuit; When constructing the target optimization model, the timing path constraint and the constraint on the number of camouflage unit replacements are represented as penalty terms, the maximization of circuit security is represented as a security evaluation function, and the penalty terms and the security evaluation function are weighted and fused together using the Lagrange multiplier method to construct the target function. The security evaluation function is constructed by integrating the logical function security measure, structural security measure and position contribution of the nodes in the timing path of the original circuit design netlist, and the security evaluation function is used to quantify and score each node in the netlist. The constraint planning involves checking the temporal path constraints of the current replacement solution. Specifically, it calculates the margin of all temporal paths corresponding to logical nodes in the current replacement solution. When the margin of any temporal path is lower than a preset value, it is determined to be a logical node that violates the temporal path constraints, and pruning is performed to exclude it from the current replacement solution.

2. The method according to claim 1, characterized in that, The logical function security metric of the node is determined by the node's function mapping number, inconsistency coefficient, and unit-level security complexity. The unit-level security complexity is determined by the functional coverage capabilities of the multi-threshold masquerading unit.

3. The method according to claim 1, characterized in that, A random perturbation operation is performed on the pruned replacement solution. Specifically, one selected camouflage unit is replaced with another candidate unit, and after generating a new replacement solution, the temporal path constraint check is continued.

4. The method according to claim 1, characterized in that, The simulated annealing specifically involves: performing global optimization on the new replacement solution obtained after constrained programming, and accepting or rejecting the updated replacement solution according to the Monte Carlo criterion.

5. The method according to claim 1, characterized in that, The timing, functional, and physical verification of the circuit design netlist after replacement based on the optimal replacement solution is performed.

6. The method according to claim 5, characterized in that, The functionality was verified using the Formality tool, which compared the original functionality with the replaced netlist design in terms of functional behavior.

7. The method according to claim 5, characterized in that, The physical verification employs Design Rule Check (DRC) and Layout-to-Schematic (LVS) consistency check.

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