Device for improving bus common-mode voltage offset of a can transceiver, can transceiver

Abstract

This invention discloses a device and a CAN transceiver for improving common-mode voltage offset on the CAN transceiver bus. The device includes a main drive module, a common-mode clamping module, and a slope control module. The common-mode clamping module and the slope control module are connected between the CAN high-side (CANH) and CAN low-side (CANL). The output of the common-mode clamping module is connected to the common-mode feedback nodes of CANH and CANL. The main drive module generates a slope control signal according to a set timing control logic. The common-mode clamping module generates a common-mode clamping voltage at the common-mode feedback nodes of CANH and CANL. The slope control module generates a bias current based on the common-mode clamping voltage after the slope control enable signal is enabled, and generates a controllable discharge current path from CANH and CANL to the operational amplifier node based on the bias current and the slope control signal. Using this invention, the EMC characteristics of the CAN transceiver can be optimized, ensuring common-mode stability and system robustness.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and more specifically to a device for improving the common-mode voltage offset of a CAN transceiver bus and a CAN transceiver. Background Technology

[0002] CAN (Controller Area Network) is a high-performance, high-reliability, multi-master, real-time fieldbus protocol standard based on a broadcast mechanism and using differential signaling for serial communication. It allows nodes in the network (controllers, sensors, actuators, etc.) to communicate with each other without a central host control. The CAN bus has two logic states: dominant (representing logic 0) and recessive (representing logic 1). In the dominant state, the CAN transceiver actively drives the bus; in the recessive state, all transceivers do not actively drive the bus, and the bus is pulled to a common-mode level through terminating resistors.

[0003] In CAN bus communication, the transition from a dominant to a recessive state, known as D2R (Dominant-to-Recessive), is a major source of EMI (Electromagnetic Interference) due to the release of parasitic inductance energy caused by the instantaneous turn-off of the driver. To reduce EMI, existing technologies typically employ slope control, which slows down the bus voltage transition rate by controlling the turn-off speed of the driver transistors (including high-side PMOS and low-side NMOS transistors). However, in practical circuits, due to mismatches in drive capability, parasitic parameters, and differences in control signal paths, it is difficult to achieve perfectly synchronized turn-off between the high-side and low-side switches. This asynchrony leads to a serious problem: in the initial stage of the D2R transition, the current flowing through the driver transistors CANH (CAN high-side) and CANL (CAN low-side) becomes unbalanced, causing a momentary shift in the bus common-mode voltage. Figure 1 As shown. This instantaneous shift in common-mode voltage can cause the following problems: (1) Deterioration of EMC (Electromagnetic Compatibility) performance: generating additional common-mode noise and exacerbating electromagnetic radiation. (2) Affecting signal integrity: fluctuations in the common-mode point can interfere with the true waveform of the differential signal. Summary of the Invention

[0004] This invention provides a device and a CAN transceiver for improving the common-mode voltage offset of the CAN transceiver bus. It can improve the common-mode voltage offset of the CAN transceiver bus, optimize EMC (Electromagnetic Compatibility) characteristics, and ensure common-mode stability and system robustness.

[0005] On one hand, embodiments of the present invention provide a device for improving the common-mode voltage offset of a CAN transceiver bus. The device includes: a main drive module, a common-mode clamping module, and a slope control module; the common-mode clamping module and the slope control module are connected between the CAN high-side CANH and the CAN low-side CANL; the output terminal of the common-mode clamping module is connected to the common-mode feedback node VCM of the CANH and the CANL. The main drive module is used to generate CAN bus differential signals according to the set timing control logic; The common-mode clamping module is used to generate a common-mode clamping voltage at the common-mode feedback node VCM of the CANH and the CANL. The slope control module is used to generate a bias current after the slope control enable signal G_CTRL is enabled, and to generate a discharge current path with controllable magnitude from the CANH and CANL to the circuit operational amplifier node based on the bias current.

[0006] Optionally, the main drive module includes: a bias voltage generation unit, a high-side voltage drive array, and a low-side voltage drive array; the high-side voltage drive array includes multiple high-side voltage drive units connected in parallel; the low-side voltage drive array includes multiple low-side voltage drive units connected in parallel. The bias voltage generating unit is used to generate a high-side bias voltage for the high-side voltage driving array and a low-side bias voltage for the low-side voltage driving array. The high-side voltage drive array is configured to pull up the voltage of CANH to VDD-Vt based on the high-side bias voltage during the dominant state; during the transition from the dominant state to the recessive state, the voltage of the common-mode feedback node VCM is clamped to VDD / 2, and each high-side voltage drive unit is disconnected sequentially so that the voltage of CANH gradually approaches VDD / 2. The low-side voltage drive array is configured to pull down the voltage of the CANL to Vt based on the low-side bias voltage during the dominant state; during the transition from the dominant state to the recessive state, the voltage of the common-mode feedback node VCM is clamped to VDD / 2, and each low-side voltage drive unit is disconnected sequentially so that the voltage of the CANL gradually approaches VDD / 2. VDD is the power supply voltage, and Vt is the set voltage.

[0007] Optionally, the bias voltage generating unit includes a current mirror, a high-side bias unit, and a low-side bias unit; The current mirror is used to obtain the bias current; The high-side bias unit is used to generate the high-side bias voltage based on the bias current; The low-side bias unit is used to generate the low-side bias voltage based on the bias current.

[0008] Optionally, the high-side voltage driving unit includes a PMOS transistor and a high-side switch; the high-side switch is connected to the output terminal of the high-side bias unit and the gate of the PMOS transistor, respectively; the source of the PMOS transistor is connected to the power supply voltage, and the drain of the PMOS transistor is connected to the CANH; the low-side voltage driving unit includes an NMOS transistor and a low-side switch; the low-side switch is connected to the output terminal of the low-side bias unit and the gate of the NMOS transistor, respectively; the source of the NMOS transistor is grounded, and the drain of the NMOS transistor is connected to the CANL.

[0009] Optionally, the circuit further includes: a timing signal generation module, used to generate a first timing signal for controlling each high-side switch and a second timing signal for controlling each low-side switch according to the timing control signal TXD.

[0010] Optionally, the common-mode clamping module includes: an operational amplifier; The non-inverting input of the operational amplifier is connected to a reference voltage, and the inverting input and output of the operational amplifier are both connected to the common-mode feedback node VCM of the CANH and CANL.

[0011] Optionally, the common-mode clamping module further includes: a high-side clamping branch and a low-side clamping branch; The high-side clamping branch includes a first PMOS transistor PM1, a first NMOS transistor NM1, and a first switch TG1 connected sequentially between the CANH and the common-mode feedback node. The low-side clamping branch includes a second PMOS transistor PM2, a second NMOS transistor NM2, and a second switch TG2 connected sequentially between the CANL and the common-mode feedback node VCM. The first switch TG1 and the second switch TG2 are controlled by the slope control enable signal G_CTRL.

[0012] Optionally, the common-mode clamping module further includes a voltage divider unit; the voltage divider unit includes a first voltage divider resistor and a second voltage divider resistor connected in series between the power supply and ground, for generating the reference voltage VDD / 2 through voltage division.

[0013] Optionally, the slope control module includes: a high-side slope control unit and a low-side slope control unit; The high-side slope control unit includes: a first current path and a first voltage path; the low-side slope control unit includes: a second current path and a second voltage path; The first current path is used to generate a first current; The first voltage path is used to establish the gate-source voltage of the first PMOS transistor PM1 based on the first current when the first switch TG1 is turned on. The second current path is used to generate a second current; The second voltage path is used to establish the gate-source voltage of the second PMOS transistor PM2 based on the second current when the second switch TG2 is turned on.

[0014] Optionally, the first current path includes: a third resistor R3 connected in series between the source of the first PMOS transistor PM1 and the first current source, a third NMOS transistor NMOS3, and a fourth NMOS transistor NM4. The first voltage path includes: the third resistor R3 connected between the gate and source of the first PMOS transistor PM1; The second current path includes: a fifth resistor R5 connected in series between the source of the second PMOS transistor PM2 and the second current source, a fifth NMOS transistor NM5, and a sixth NMOS transistor NM6; The second voltage path includes the fifth resistor R5 connected between the gate and source of the second PMOS transistor PM2; The gate of the fourth NMOS transistor NM4 is connected to the gate of the sixth NMOS transistor NM6, and the source of the fourth NMOS transistor NM4 and the source of the sixth NMOS transistor NM6 are respectively connected to their respective bias current sources.

[0015] On the other hand, embodiments of the present invention also provide a CAN transceiver, including the aforementioned means for improving the common-mode voltage offset of the CAN transceiver bus.

[0016] The apparatus and CAN transceiver for improving the common-mode voltage offset of the CAN transceiver bus provided in this invention introduce a common-mode clamping circuit with active slope control capability. This circuit can force the CAN bus common-mode voltage to be stabilized near VDD / 2 during the critical transition period from dominant to recessive state of the CAN bus. At the same time, it releases the CAN bus from the dominant state to the recessive state in a controlled and gradual manner, thereby optimizing EMC characteristics while ensuring common-mode stability and system robustness. Attached Figure Description

[0017] Figure 1This is a schematic diagram illustrating the instantaneous shift in the common-mode voltage of the traditional CAN bus during the initial stage of D2R conversion. Figure 2 This is a schematic diagram of a traditional CAN transceiver circuit. Figure 3 This is a schematic diagram of a device for improving the common-mode voltage offset of a CAN transceiver bus provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the main drive module in one embodiment of the present invention; Figure 5 This is a schematic diagram of a timing signal generation module in an embodiment of the present invention; Figure 6 This is a schematic diagram of the common-mode clamping module and the slope control module in one embodiment of the present invention; Figure 7 This is a waveform diagram of the timing control logic when the TX signal changes from dominant to recessive in an embodiment of the present invention. Figure 8 This is a schematic diagram comparing the CANH, CANL, and common-mode voltage waveforms of the present invention and the prior art (without common-mode clamping) when the TX signal changes from dominant to recessive. Detailed Implementation

[0018] The principles and spirit of the invention will now be described with reference to exemplary embodiments shown in the accompanying drawings. It should be understood that these embodiments are described merely to enable those skilled in the art to better understand and implement the invention, and are not intended to limit the scope of the invention in any way.

[0019] In CAN bus communication, dominant and recessive states refer to two logic level states on the bus, defined by the differential voltage between the CANH and CANL wires. The dominant state typically corresponds to logic 0, and the recessive state typically corresponds to logic 1, at which point the CAN bus is in an "idle" or "released" state. Resistors on the CAN bus (i.e., terminating resistors) keep the two wires CANH and CANL at similar voltages. If no node actively drives the CAN bus, it remains in the recessive state. When any node on the CAN bus wants to send data, it puts the CAN bus into the dominant state, actively driving the bus by pulling CANH high and CANL low, thus generating a differential voltage. After data transmission is complete, the node stops driving the CAN bus, cutting off the drive current. At this point, the CAN bus needs to be passively "discharged" or "pulled back" to the common-mode voltage through the terminating resistor. During the D2R transition, CANH typically needs to drop from 3.5V to 2.5V, and CANL needs to rise from 1.5V to 2.5V. Because this is a passive release process, it is difficult to make the rates of change of CANH and CANL completely synchronized at the moment of transition. This asymmetry will cause a shift in the common-mode voltage, and if there is no common-mode clamping circuit to clamp its common-mode point near VDD / 2, common-mode noise will be generated.

[0020] The traditional solution is to connect a resistor between CANH and CANL, such as... Figure 2 As shown, its principle is as follows: the control signal TXD turns off the drive switches of the high-side PMOS transistor and the low-side NMOS transistor in a time-division manner. The power supply VDD generates the voltage VDD / 2 of the common-mode feedback node VCM through the voltage divider resistors R1 and R2, and then pulls the common-mode voltage of CANH and CANL to VDD / 2 through resistors R3 and R4.

[0021] This method has the following problems: When there is a large mismatch between the PMOS and NMOS power transistors, the current difference flowing through the PMOS and NMOS is significant. If the resistances R1, R2, R3, and R4 are large, it is difficult to clamp the common-mode voltages of CANH and CANL to VDD / 2. If the resistances R1, R2, R3, and R4 are small, a large current will always exist in resistors R1, R2, R3, and R4 when the CAN transceiver is working normally, resulting in additional high power consumption. Moreover, resistors R3 and R4 will shunt the current of the power transistors, reducing the current on the terminating resistor, thus affecting the performance of the CAN transceiver.

[0022] To address this, this invention provides a device for improving the common-mode voltage offset of a CAN transceiver bus. Based on the traditional time-division turn-off drive switch, a VDD / 2 common-mode clamping circuit with active slope control capability is introduced to force the bus common-mode voltage to stabilize near VDD / 2 during the critical transition period from dominant to recessive state. At the same time, the bus is released from the dominant state to the recessive state in a controlled and smooth manner, thereby optimizing EMC characteristics while ensuring common-mode stability and system robustness.

[0023] like Figure 3 The diagram shown is a structural schematic of a device for improving the common-mode voltage offset of a CAN transceiver bus provided in an embodiment of the present invention.

[0024] The device for improving the common-mode voltage offset of the CAN transceiver bus includes a main drive module 31, a common-mode clamping module 32, and a slope control module 33. The common-mode clamping module 32 and the slope control module 33 are connected between CANH and CANL, and the output of the common-mode clamping module 32 is connected to the common-mode feedback node VCM of CANH and CANL.

[0025] The main drive module 31 is used to generate CAN bus differential signals according to the set timing control logic; The common-mode clamping module 32 is used to generate a common-mode clamping voltage at the common-mode feedback node VCM of CANH and CANL; The slope control module 33 is used to generate a bias current after the slope control enable signal G_CTRL is enabled, and to generate a discharge current path with controllable magnitude from the CANH and CANL to the circuit operational amplifier node based on the bias current and the slope control signal.

[0026] The common-mode clamping module 32 mainly includes an operational amplifier. The non-inverting input of the operational amplifier is connected to a reference voltage, and the inverting input and output are connected to the common-mode feedback node VCM of CANH and CANL. The reference voltage is VDD / 2, where VDD is the power supply voltage.

[0027] In some embodiments, the reference voltage can be obtained by resistor voltage division. Accordingly, the common-mode clamping module 32 may further include a voltage divider unit. For example... Figure 3 As shown, the voltage divider unit includes a first voltage divider resistor R1 and a second voltage divider resistor R2 connected in series between the power supply and ground, used to generate the reference voltage VDD / 2 through voltage division. The resistance values ​​of R1 and R2 are the same.

[0028] Reference Figure 4 , Figure 4 A schematic diagram of the main drive module 31 in an embodiment of the present invention is shown.

[0029] In this embodiment, the main drive module 31 includes: a bias voltage generation unit 310, a high-side voltage drive array 311, and a low-side voltage drive array 312. The high-side voltage drive array 311 includes multiple high-side voltage drive units connected in parallel; the low-side voltage drive array 312 includes multiple low-side voltage drive units connected in parallel. Wherein: The bias voltage generation unit 310 is used to generate a high-side bias voltage Pbias for the high-side voltage drive array 311 and a low-side bias voltage Nbias for the low-side voltage drive array 312.

[0030] The high-side voltage drive array 311 is configured to pull up the voltage of CANH to VDD-Vt based on the high-side bias voltage Pbias during the dominant state; during the transition from the dominant state to the recessive state, the voltage of the common-mode feedback node VCM is clamped to VDD / 2, and each high-side voltage drive unit is disconnected in sequence so that the voltage of CANH gradually approaches VDD / 2.

[0031] The low-side voltage drive array 312 is configured to pull down the voltage of CANL to Vt based on the low-side bias voltage Nbias during the dominant state; during the transition from the dominant state to the recessive state, the voltage of the common-mode feedback node VCM is clamped to VDD / 2, and each low-side voltage drive unit is disconnected in sequence so that the voltage of CANL gradually approaches VDD / 2. Wherein, VDD is the power supply voltage, and Vt is the set voltage, which can be set as needed and adjusted according to the number of parallel high-side voltage drive units and the number of high-side voltage drive units.

[0032] In this embodiment of the invention, the number of parallel high-side voltage driving units and the number of high-side voltage driving units are the same.

[0033] Continue to refer to Figure 4 In some embodiments, the bias voltage generating unit 310 may include a current mirror, a high-side bias unit, and a low-side bias unit.

[0034] The current mirror is a diode-connected current mirror used to obtain the bias current. For example... Figure 4 As shown, the current mirror includes a current generation branch composed of PMOS transistors PM5, PM7, and NMOS transistor NM5, and a current mirroring branch composed of PMOS transistor PM8. The source of PM5 is connected to the power supply voltage VDD, and the gate and drain of PM5 are connected, and also connected to the source of PM7; the gate and drain of PM7 are connected, and also connected to the drain of NM5; the source of NM5 is grounded, and the gate of NM5 is connected to the reference voltage BIAS, thereby generating a bias current in the current generation branch. Correspondingly, PM5, PM6, PM7, and PM8 form a transconductance linear loop, obtaining this bias current through mirroring.

[0035] like Figure 4 As shown, the high-side bias unit can be implemented by a PMOS transistor PM6 connected to a diode, used to generate a high-side bias voltage Pbias based on the bias current; the low-side bias unit can be implemented by an NMOS transistor NM6 connected to a diode, used to generate a low-side bias voltage Nbias based on the bias current.

[0036] The high-side voltage drive array 311 includes multiple high-side voltage drive units, each of which includes a PMOS transistor and a high-side switch. For example... Figure 4 As shown, the high-side voltage drive array 311 includes m+1 (m is an integer greater than or equal to 0) PMOS transistors, namely P0, P1, ..., P2. m-1 ,P m Each PMOS transistor has a corresponding high-side switch kp, kp+1, ..., kp+m-1, kp+m. Each high-side switch is connected to the output terminal of the high-side bias unit (to receive the high-side bias voltage Pbias) and the gate of the corresponding PMOS transistor. The source of each PMOS transistor is connected to the power supply voltage VDD, and the drain of each PMOS transistor is connected to CANH through a first diode D1. These high-side switches form a high-side switch array, used to control the connection or disconnection of the corresponding PMOS transistor with the high-side bias voltage Pbias.

[0037] The low-side voltage drive array 312 includes multiple low-side voltage drive units, each of which includes an NMOS transistor and a low-side switch. For example... Figure 4 As shown, the low-side voltage drive array 312 includes m+1 NMOS transistors, namely N0, N1, ..., N m-1 N m The low-side switches kn, kn+1, ..., kn+m-1, kn+m are corresponding to each NMOS transistor. Each low-side switch is connected to the output terminal of the low-side bias unit (to access the low-side bias voltage Nbias) and the gate of the corresponding NMOS transistor. The source of the NMOS transistor is grounded, and the drain of each NMOS transistor is connected to CANL through the second diode D2.

[0038] During the dominant state, all the high-side switches kp,kp+1,…,kp+m-1,kp+m and all the low-side switches kn,kn+1,…,kn+m-1,kn+m are closed, pulling the CANH voltage up to VDD-Vt and pulling the CNHL voltage down to Vt. During the transition from the dominant to the recessive state, after the voltage of the common-mode feedback node VCM is clamped to VDD / 2, the first timing signal controls the sequential opening of each high-side switch in the high-side switch array, and simultaneously, the second timing signal controls the sequential opening of each low-side switch in the low-side switch array. The current falling on the terminating resistor gradually decreases to 0, ultimately causing the CAN bus voltage to reach VDD / 2.

[0039] During the process of releasing the bus from a dominant state to a recessive state, the voltages of CANH and CANL are adjusted in a smooth manner, which can stabilize the bus common-mode voltage at VDD / 2. This optimizes EMC characteristics while ensuring common-mode stability and system robustness.

[0040] The first timing signal and the second timing signal mentioned above can be generated by a delay signal generation module. The timing signal generation module can be integrated into the device for improving the common-mode voltage offset of the CAN transceiver bus in this embodiment of the invention, or it can be independent of the device. This embodiment of the invention does not limit this.

[0041] like Figure 5 The diagram shown is a structural schematic of a timing signal generation module in an embodiment of the present invention.

[0042] In this embodiment, the timing signal generation module 40 is used to generate a first timing signal for controlling each high-side switch and a second timing signal for controlling each low-side switch based on the timing control signal TXD. In a non-limiting embodiment, the timing signal generation module 40 can generate the first and second timing signals using multiple inverters and buffers.

[0043] like Figure 6 The diagram shown is a structural schematic of the common-mode clamping module and the slope control module in an embodiment of the present invention.

[0044] In this example, operational amplifier 320 further includes a high-side clamping branch and a low-side clamping branch. The non-inverting input of operational amplifier 320 is connected to a reference voltage, and both the inverting input and output of operational amplifier 320 are connected to the common-mode feedback node VCM of CANH and CANL.

[0045] The high-side clamping branch includes a first PMOS transistor PM1, a first NMOS transistor NM1, and a first switch TG1 connected sequentially between CANH and the common-mode feedback node VCM; the gate of NM1 is connected to the power supply voltage VDD.

[0046] The low-side clamping branch includes a second PMOS transistor PM2, a second NMOS transistor NM2, and a second switch TG2 connected sequentially between CANL and the common-mode feedback node VCM; the gate of NM2 is connected to the power supply voltage VDD.

[0047] The first switch TG1 and the second switch TG2 are controlled by the slope control enable signal G_CTRL.

[0048] In this embodiment, the common-mode clamping module 32 uses a high-performance Class AB operational amplifier, i.e., the output stage is a Class AB operational amplifier. Its non-inverting input is connected to a precise reference voltage VDD / 2, and its inverting input is connected to the common-mode feedback node VCM. The common-mode feedback node VCM is connected to CANH and CANL through PM1, NM1, TG1, PM2, NM2, and TG2. PM1 and PM2 are two large-size, matched PMOS transistors, and NM1 and NM2 are two large-size, matched NMOS transistors.

[0049] The slope control module 33 includes a high-side slope control unit and a low-side slope control unit; the high-side slope control unit includes a first current path and a first voltage path; the low-side slope control unit includes a second current path and a second voltage path. Wherein: The first current path is used to generate a first current. Correspondingly, the first voltage path is used to establish the gate-source voltage of the first PMOS transistor PM1 based on the first current when the first switch TG1 is turned on.

[0050] like Figure 6 As shown, in a non-limiting embodiment, the first current path includes a third resistor R3, a third NMOS transistor NM3, and a fourth NMOS transistor NM4, connected in series between the source of the first PMOS transistor PM1 and the first current source; the gate of NM3 is connected to the power supply voltage VDD, the drain of NM3 is connected to R3, the source of NM3 is connected to the drain of NM4, and the source of NM4 is connected to the first bias current source IBN1. The first voltage path includes a third resistor R3 connected in series between the gate and source of the first PMOS transistor PM1.

[0051] Similarly, the second current path is used to generate a second current. Correspondingly, the second voltage path is used to establish the gate-source voltage of the second PMOS transistor PM2 based on the second current when the second switch TG2 is turned on.

[0052] like Figure 6As shown, in a non-limiting embodiment, the second current path includes a fifth resistor R5, a fifth NMOS transistor NM5, and a sixth NMOS transistor NM6, connected in series between the source of the second PMOS transistor PM2 and the second current source; the gate of NM5 is connected to the power supply voltage VDD, the drain of NM5 is connected to R5, the source of NM5 is connected to the drain of NM6, and the source of NM6 is connected to the second bias current source IBN2. The second voltage path includes a fifth resistor R5 connected between the gate and source of the second PMOS transistor PM2.

[0053] It should be noted that the first bias current source IBN1 and the second bias current source IBN2 have the same magnitude.

[0054] Additionally, the gate of the fourth NMOS transistor NM4 is connected to the gate of the sixth NMOS transistor NM6. A fourth resistor R4 is connected between the third resistor R3 and ground, and a sixth resistor R6 is connected between the fifth resistor R5 and ground. R4 and R6 are used to set the gates of PM1 and PM2 to 0 after the slope control enable signal G_CTRL is invalidated.

[0055] exist Figure 6 In the illustrated embodiment, the source of the first PMOS transistor PM1 is connected to the drain of the first NMOS transistor NM1; the source of the second PMOS transistor PM2 is connected to the drain of the second NMOS transistor NM2.

[0056] The following is combined with Figure 6 and Figure 7 The working principle of the common mode clamping module and the slope control module in this embodiment is explained in detail. Figure 7 The diagram shows the waveform of the timing control logic when the TX signal changes from dominant to recessive in an embodiment of the present invention.

[0057] Reference Figure 6 and Figure 7 The process of a TX signal changing from dominant to recessive can include the following three stages: Phase 1 (t1): Clamp Establishment After the slope control enable signal G_CTRL is valid, the op-amp is enabled, and simultaneously, the two switches TG1 and TG2, as well as the two NMOS transistors NM4 and NM6, are turned on. At this time, the current from the first bias current source IBN1 draws current from the source of PM1 through NM3, NM4, and R1. PM1 is then turned on, and its gate-source voltage is established and equal to IBN1 × R3. The current from the second bias current source IBN2 draws current from the source of PM2 through NM5, NM6, and R2. At this time, PM2 is turned on, and its gate-source voltage is established and equal to IBN2 × R5. The 2.5V common-mode voltage output by operational amplifier 320 is applied to the CANH and CAHL ports. At this time, the drive current is shunted by the clamping circuit, and the current on the terminating resistor decreases. Therefore, at the end of stage t1, the voltages of CANH and CAHL will approach 2.5V.

[0058] Phase Two (t2): Controlled Discharge

[0059] After the slope control enable signal G_CTRL is valid, there is a delay (e.g., tens of ns) before the logic circuit sequentially disconnects the high-side and low-side switches in the main drive module 31. Simultaneously, the common-mode clamping module 32 stably controls the common-mode voltages of CANH and CANL at VDD / 2. As the high-side and low-side switches of the main drive module 31 sequentially disconnect, the CANH voltage begins to decrease, the CANL voltage begins to increase, and the CAN differential voltage decreases at a near-linear rate until it reaches 0.

[0060] It should be noted that the length of time t2 is related to the magnitude of the slope control. For example, when a smaller slope change is required, more high-side voltage drive units and low-side voltage drive units can be set; when a larger slope change is required, fewer high-side voltage drive units and low-side voltage drive units can be set. This embodiment of the invention does not limit this.

[0061] Phase 3 (t3): Release and Steady State

[0062] After the last high-side and low-side switches are opened, the differential voltage of the CAN bus decays to near zero. At this point, the slope control enable signal G_CTRL is turned off, thereby shutting down operational amplifier 320, as well as NM4 and NM6. Modules such as operational amplifier 320 cease operation. The bus is then completely taken over by the terminating resistor network and enters a steady-state recessive level.

[0063] Reference Figure 8 , Figure 8 This is a schematic diagram comparing the CANH, CANL, and common-mode voltage waveforms of the present invention and the prior art (without common-mode clamping) when the TX signal changes from dominant to recessive.

[0064] exist Figure 8 During the time periods t1 and t2 shown, the common-mode clamping module is turned on. Since the embodiment of the present invention uses a high-performance Class AB operational amplifier with very strong driving capability, the common-mode potentials of CANH and CANL can always be clamped to VDD / 2.

[0065] exist Figure 8 During the time intervals t1 and t2 shown, the slope control enable signal G_CTRL will turn on the two NMOS transistors NM4 and NM6, and simultaneously turn on TG1 and TG2. At this time, the current IBN1 from the first current source draws current from the source of PM1 through NM3, NM4, and R1. At this time, the gate-source voltage of PM1 is equal to IBN1 × R3, thus controlling the output current capability of PM1 by controlling its gate-source voltage. The current IBN2 from the second current source draws current from the source of PM2 through NM5, NM6, and R2. At this time, the gate-source voltage of PM2 is equal to IBN2 × R5, thus controlling the output current capability of PM2 by controlling its gate-source voltage.

[0066] pass Figure 8 The comparison shows that the traditional solution exhibits significant spikes in the common-mode voltage (dashed line) when the switch is turned off; while in the solution of this invention, the common-mode voltage can be stably maintained at VDD / 2 (solid line) throughout the entire conversion process, and the differential voltage edge is smooth.

[0067] The device for improving the common-mode voltage offset of the CAN transceiver bus provided in this invention introduces a common-mode clamping module with active slope control capability. During the critical transition period from dominant to recessive state of the CAN bus, it can force the common-mode voltage of the CAN bus to be stabilized near VDD / 2. At the same time, in coordination with independent slope control, it can smoothly release the CAN bus from the dominant state to the recessive state. Thus, while optimizing EMC characteristics, it ensures common-mode stability and system robustness, providing an excellent physical layer solution for high-speed, high-reliability CAN bus systems.

[0068] Accordingly, embodiments of the present invention also provide a CAN transceiver, including the aforementioned means for improving the common-mode voltage offset of the CAN transceiver bus.

[0069] In the description of the embodiments of the present invention, unless otherwise expressly specified and limited, ordinal numbers, such as "first," "second," etc., are used only to distinguish and describe related objects, and should not be construed as indicating or implying the relative importance or order between related objects. Furthermore, ordinal numbers do not represent the number of related objects.

[0070] In the description of the embodiments of this invention, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. Other quantifiers are similar.

[0071] The terms "or" and "and / or" used in this invention are used to describe the relationship between associated objects, indicating a non-exclusive inclusion. For example, "A and / or B" can include: "A alone", "B alone", or "A and B". Additionally, the character " / " in this document indicates that the preceding and following associated objects have an "or" relationship.

[0072] In the several embodiments provided by this invention, it should be understood that the disclosed circuits can be implemented in other ways. For example, the circuit embodiments described above are merely illustrative; for example, the division of modules is merely a logical functional division, and there may be other division methods in actual implementation, which this invention does not limit.

[0073] In the embodiments of the present invention, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0074] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one physical unit, or they can be separate physical units, or two or more units can be integrated into one unit. The integrated unit described above can be implemented in hardware or in the form of hardware and software functional units.

[0075] Although embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Any person skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments without departing from the spirit and scope of the present invention.

Claims

1. A device for improving the common-mode voltage offset of a CAN transceiver bus, characterized in that, The device includes: a main drive module, a common-mode clamping module, and a slope control module; the common-mode clamping module and the slope control module are connected between the CAN high-side CANH and the CAN low-side CANL; the output of the common-mode clamping module is connected to the common-mode feedback node (VCM) of the CANH and the CANL. The main drive module is used to generate CAN bus differential signals according to the set timing control logic; The common-mode clamping module employs a high-performance Class AB operational amplifier, with its non-inverting input connected to a precise reference voltage VDD / 2 and its inverting input connected to the common-mode feedback node (VCM). The common-mode clamping module is used to generate a common-mode clamping voltage at the common-mode feedback node (VCM) of the CANH and CANL. The slope control module is used to generate a bias current after the slope control enable signal (G_CTRL) is enabled, and to generate a discharge current path with controllable magnitude from the CANH and CANL to the circuit operational amplifier node based on the bias current.

2. The apparatus for improving the common-mode voltage offset of a CAN transceiver bus according to claim 1, characterized in that, The main drive module includes: a bias voltage generation unit, a high-side voltage drive array, and a low-side voltage drive array; the high-side voltage drive array includes multiple high-side voltage drive units connected in parallel; the low-side voltage drive array includes multiple low-side voltage drive units connected in parallel. The bias voltage generating unit is used to generate a high-side bias voltage for the high-side voltage driving array and a low-side bias voltage for the low-side voltage driving array. The high-side voltage drive array is configured to pull up the voltage of the CANH to VDD-Vt based on the high-side bias voltage during the dominant state; during the transition from the dominant state to the recessive state, the voltage of the common-mode feedback node (VCM) is clamped to VDD / 2, and each high-side voltage drive unit is disconnected sequentially so that the voltage of the CANH gradually approaches VDD / 2. The low-side voltage drive array is configured to pull down the voltage of the CANL to Vt based on the low-side bias voltage during the dominant state; during the transition from the dominant state to the recessive state, the voltage of the common-mode feedback node (VCM) is clamped to VDD / 2, and each low-side voltage drive unit is disconnected sequentially so that the voltage of the CANL gradually approaches VDD / 2. VDD is the power supply voltage, and Vt is the set voltage.

3. The apparatus for improving the common-mode voltage offset of a CAN transceiver bus according to claim 2, characterized in that, The bias voltage generating unit includes a current mirror, a high-side bias unit, and a low-side bias unit. The current mirror is used to obtain the bias current; The high-side bias unit is used to generate the high-side bias voltage based on the bias current; The low-side bias unit is used to generate the low-side bias voltage based on the bias current.

4. The apparatus for improving the common-mode voltage offset of a CAN transceiver bus according to claim 3, characterized in that: The high-side voltage driving unit includes a PMOS transistor and a high-side switch; the high-side switch is connected to the output terminal of the high-side bias unit and the gate of the PMOS transistor respectively; the source of the PMOS transistor is connected to the power supply voltage, and the drain of the PMOS transistor is connected to the CANH. The low-side voltage driving unit includes an NMOS transistor and a low-side switch; the low-side switch is connected to the output terminal of the low-side bias unit and the gate of the NMOS transistor, respectively; the source of the NMOS transistor is grounded, and the drain of the NMOS transistor is connected to the CANL.

5. The apparatus for improving the common-mode voltage offset of a CAN transceiver bus according to claim 4, characterized in that, The circuit also includes: The timing signal generation module is used to generate a first timing signal for controlling each high-side switch and a second timing signal for controlling each low-side switch based on the timing control signal (TXD).

6. The apparatus for improving the common-mode voltage offset of a CAN transceiver bus according to claim 2, characterized in that, The common-mode clamping module includes: an operational amplifier; The non-inverting input of the operational amplifier is connected to a reference voltage, and the inverting input and output of the operational amplifier are both connected to the common-mode feedback node (VCM) of the CANH and the CANL.

7. The apparatus for improving the common-mode voltage offset of a CAN transceiver bus according to claim 6, characterized in that, The common-mode clamping module further includes: a high-side clamping branch and a low-side clamping branch; The high-side clamping branch includes a first PMOS transistor (PM1), a first NMOS transistor (NM1), and a first switch (TG1) connected sequentially between the CANH and the common-mode feedback node. The low-side clamping branch includes a second PMOS transistor (PM2), a second NMOS transistor (NM2), and a second switch (TG2) connected sequentially between the CANL and the common-mode feedback node (VCM). The first switch (TG1) and the second switch (TG2) are controlled by the slope control enable signal (G_CTRL).

8. The apparatus for improving the common-mode voltage offset of a CAN transceiver bus according to claim 7, characterized in that, The common-mode clamping module further includes a voltage divider unit; the voltage divider unit includes a first voltage divider resistor and a second voltage divider resistor connected in series between the power supply and ground, used to generate the reference voltage VDD / 2 by voltage division.

9. The apparatus for improving the common-mode voltage offset of a CAN transceiver bus according to claim 7, characterized in that, The slope control module includes: a high-side slope control unit and a low-side slope control unit; The high-side slope control unit includes: a first current path and a first voltage path; the low-side slope control unit includes: a second current path and a second voltage path; The first current path is used to generate a first current; The first voltage path is used to establish the gate-source voltage of the first PMOS transistor (PM1) based on the first current when the first switch (TG1) is turned on. The second current path is used to generate a second current; The second voltage path is used to establish the gate-source voltage of the second PMOS transistor (PM2) based on the second current when the second switch (TG2) is turned on.

10. The apparatus for improving the common-mode voltage offset of a CAN transceiver bus according to claim 9, characterized in that, The first current path includes: a third resistor (R3) connected in series between the source of the first PMOS transistor (PM1) and the first current source, a third NMOS transistor (NMOS3), and a fourth NMOS transistor (NM4). The first voltage path includes the third resistor (R3) connected between the gate and source of the first PMOS transistor (PM1). The second current path includes: a fifth resistor (R5), a fifth NMOS transistor (NM5), and a sixth NMOS transistor (NM6) connected in series between the source of the second PMOS transistor (PM2) and the second current source. The second voltage path includes the fifth resistor (R5) connected between the gate and source of the second PMOS transistor (PM2); The gate of the fourth NMOS transistor (NM4) is connected to the gate of the sixth NMOS transistor (NM6), and the source of the fourth NMOS transistor (NM4) and the source of the sixth NMOS transistor (NM6) are respectively connected to their respective bias current sources.

11. A CAN transceiver, comprising means for improving the common-mode voltage offset of the CAN transceiver bus as described in any one of claims 1 to 10.

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