Method for improving high-speed signal impedance of via dense area of circuit board and ATE board

Abstract

The application relates to the field of high-speed chip testing, in particular to a method for improving high-speed signal impedance in a via dense area of a circuit board and an ATE board. The via dense area of the circuit board comprises a plurality of signal vias and a plurality of ground vias; the method comprises: connecting at least a part of the ground vias around the signal vias and / or signal lines in series on an inner layer of the via dense area of the circuit board; wherein the signal lines are led out from the signal vias. The application can effectively improve the high-speed signal impedance in the via dense area of the circuit board, so that the impedance value of the key signal lines meets the expectation.

Description

Technical Field

[0001] This invention relates to the field of high-speed chip testing, specifically to a method and ATE board for improving the high-speed signal impedance in densely via areas of a circuit board. Background Technology

[0002] With the continuous development of electronic technology, chips for next-generation information technology are required to integrate more functions and achieve higher computing performance and transmission rates. The continuous enrichment of chip functions is directly reflected in the significant increase in the complexity of its internal circuit structure. Correspondingly, the number of pins brought out by the chip also continues to increase, and the pin arrangement density is constantly improving.

[0003] In multilayer printed circuit board (PCB) design, vias are typically placed at the pad locations to achieve electrical connectivity between the chip's surface pads and the inner circuit layers. The increased number of chip pins and the reduced spacing result in a high-density array of surface pads, leading to a dense via region beneath and around the pads.

[0004] During actual production, processing, and testing, it was found that the circuit impedance in the densely via-covered areas exhibited significant deviations: the actual processed impedance in these areas was significantly lower than the theoretical design value, resulting in poor impedance consistency and continuity. This phenomenon directly affects the transmission quality of high-speed signals, easily leading to signal integrity issues such as signal reflection, timing deviations, and increased crosstalk, thereby reducing the stability and reliability of the circuit system.

[0005] How to effectively improve the deviation between the actual and theoretical impedance values ​​in densely via areas on printed circuit boards and enhance the integrity of high-speed signal transmission has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to overcome the defects of the prior art and provide a method for improving the high-speed signal impedance in densely via areas of a circuit board. It can effectively improve the high-speed signal impedance in densely via areas of a circuit board and make the impedance value of the key signal line meet the expectations.

[0007] To solve the above-mentioned technical problems, the technical solution of the present invention is as follows: a method for improving the high-speed signal impedance in a densely via region of a circuit board, wherein the densely via region of the circuit board includes multiple signal vias and multiple ground vias; the method includes: In the inner layer of a densely viad area on a circuit board, at least a portion of the ground vias are located around series signal vias and / or signal lines; wherein the signal lines are led out from the signal vias.

[0008] Furthermore, the inner layer of the densely viad area on the circuit board is specifically as follows: The inner layer with a copper coverage rate of less than the first threshold in the densely viad area of ​​the circuit board.

[0009] Furthermore, the method also includes: The copper coverage in densely via areas of the circuit board is greater than the first threshold but not greater than the second threshold.

[0010] Furthermore, at least a portion of the ground vias surrounding the serial signal vias and / or signal lines are specifically: Connect at least a portion of the ground vias around the signal vias and / or signal lines in series to form at least one series line.

[0011] Furthermore, the method for connecting the grounding vias in series is as follows: The pads of the grounding vias to be connected in series are fabricated and then connected by wires.

[0012] Furthermore, the densely via areas on the circuit board are used to connect the chip under test.

[0013] Furthermore, the types of chips to be tested include BGA packaged chips and their derivatives such as PBGA, CBGA, and TBGA packaged chips.

[0014] The present invention also relates to an ATE board, which improves the high-speed signal impedance in densely via regions of the circuit board using the aforementioned method for improving the high-speed signal impedance in densely via regions.

[0015] By adopting the above technical solution, this invention connects the existing grounding vias around the signal in series. The additional conductors and pads added by the series grounding vias together form an interception dam structure. This interception dam structure can limit the overflow of PP (adhesive sheet) into the blank areas of the substrate during the lamination process, thereby achieving controllable PP (adhesive sheet) thickness above the critical signal and ensuring that the impedance value of the critical signal line conforms to the calculated value. Furthermore, the interception dam structure formed by the additional conductors and pads near the critical signal due to the series grounding vias will not cause crosstalk to the signal. The grounding vias themselves have a signal shielding effect. This configuration actually improves the performance of the critical signal, thereby enhancing the quality of high-speed signal transmission and improving the overall performance of the chip.

[0016] Furthermore, the present invention can effectively increase the number of pads and wiring in the dense via area of ​​the circuit board on the inner layer, improve the copper coverage, thereby improving the flatness of the dense via area after multilayer board lamination, and further improving the quality. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a densely viad area on a circuit board. Figure 2 This is a schematic diagram of the via pads and conductors in the densely viad area of ​​a circuit board during the design phase and after actual fabrication. Figure 3 A schematic diagram of the inner layer of the densely via area on the circuit board before improvement; Figure 4 To improve the filling effect of the PP (adhesive sheet) on the substrate and conductive layer pattern; Figure 5 To improve the filling effect of the PP (adhesive sheet) on the substrate and conductive layer pattern; Figure 6 This is a schematic diagram of the inner layer of the densely via region on the circuit board in the embodiment. Figure 7 Impedance test diagram for an example; Figure 8 This is a schematic diagram of the inner layer of the densely via area on the circuit board in the comparative example. Figure 9 The impedance test diagram is a comparative example. in, Figure 2 In the diagram, (a) is a schematic diagram of the via pads and conductors in the dense via area of ​​the circuit board during the design stage, and (b) is a schematic diagram of the via pads and conductors in the dense via area of ​​the circuit board after actual processing. Detailed Implementation

[0018] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0019] Taking the ATE board corresponding to the BGA packaged chip as an example, this paper will provide a detailed introduction to the origin and technical principles of this patent solution.

[0020] In multilayer PCB design, to achieve electrical connectivity between the BGA pads on the board surface and the internal layers of the circuit board, vias need to be placed at the pad locations of the BGA packages. The BGA packages have pads arranged in an array, corresponding to an array of vias, as shown in the example below. Figure 1 As shown.

[0021] The typical process for manufacturing multilayer PCBs involves first forming a conductive circuit layer on the substrate (Core), then placing a PP layer (Prepreg, adhesive sheet) between adjacent substrates. By applying heat and pressure, the PP layer is transformed from a solid state to a semi-cured, fluid state. After cooling and curing, reliable bonding between adjacent substrates is achieved. This process completes the compression molding of the multilayer board.

[0022] Impedance is a key indicator for high-speed signal transmission; the higher the signal transmission rate, the more stringent the requirements for signal impedance control precision. The impedance of signal lines on a PCB circuit board can be represented by a simple function. ; Impedance can be expressed as a function calculated from several parameters; H represents the dielectric constant of the circuit board substrate; W represents the distance from the conductor (target reference layer) on the circuit board to the adjacent reference plane; T represents the linewidth of the conductor on the circuit board; and T represents the lineheight (thickness) of the conductor on the circuit board.

[0023] The nearest reference plane layer plays a decisive role in the impedance of the target reference layer. Typically, the nearest reference plane layer is separated from the target reference layer by a PP layer, or a PP layer and a substrate layer. Conductive layers further away are no longer considered effective reference planes. Therefore, the thickness of the cured PP layer directly determines the parameter H in the impedance calculation formula.

[0024] During the lamination process, the PP layer changes from its original solid state to a semi-cured, flowing state with temperature and pressure, and finally cools back to a solid state. Let the original thickness of the PP layer be H1 (this parameter is provided by the material manufacturer or can be measured), and the theoretical thickness after lamination and curing be H2. Typically, H1 > H2, meaning the PP layer thickness will decrease after lamination compared to its original state. The specific value of H2 is generally determined by each PCB manufacturer based on its own processing technology and experience with different board types. When calculating signal line impedance, the theoretical thickness H2 after lamination must first be estimated based on the original thickness H1 and process conditions. Through long-term design, processing, and experimental verification, the applicant has established corresponding thickness correction models for different board types: for example, for type A PP, the original thickness is H1. After extensive data statistics and verification, the equivalent thickness to be substituted into the impedance calculation is an empirical value (i.e., the theoretical thickness H2). This H2 is then substituted into the impedance formula to complete the theoretical impedance calculation.

[0025] Based on the above process analysis and design experience, the applicant found that there is a deviation between the theoretical impedance calculation value and the actual processing value. The core reason is that the theoretical thickness H2 after PP layer lamination is inconsistent with the actual thickness H2′. This thickness deviation directly leads to the deviation between the theoretical and measured impedance values, which in turn affects the quality of high-speed signal transmission and ultimately causes a decline in the overall performance of the chip.

[0026] The applicant of this patent further discovered that the key reason for the discrepancy between the theoretical and actual thickness of the PP layer lies in the flow and filling behavior of PP in its semi-cured state. Furthermore, the actual distribution of the conductive patterns in the inner layer within the densely packed via area is directly related to the fabrication rules of the inner layer via pads.

[0027] In theory, vias on the surface and inner layers of a circuit board form a ring-shaped copper foil structure, which can be called a via pad. The via pads on the surface layer are mandatory; however, the presence or absence of inner layer via pads depends on the electrical connection requirements: if an inner layer via pad has an electrical connection to a conductor or other conductive structure, it is retained; otherwise, it is typically not created. This is because BGA areas have a large number of small vias, and isolated inner layer via pads without electrical connections have poor adhesion, making them prone to defects such as detachment or misalignment during processing. Therefore, they are not typically retained in standard manufacturing processes. Figure 2 Image (a) shows a schematic diagram of the via pads and conductors in the densely viad area of ​​the circuit board during the design phase. Figure 2 (b) shows a schematic diagram of the via pads and wires in the dense via area of ​​the circuit board after actual processing.

[0028] During the lamination process, the semi-cured, fluid PP flows along the substrate surface and conductive patterns (wires, pads), filling gaps. For example... Figure 3 As shown, vias without electrical connections in the inner layer do not have pads; only via pads with wire connections are retained. This results in a sparse and low-proportion conductive pattern in the densely viad area. When the semi-cured PP flows and fills this area, its cross-sectional shape is as follows. Figure 4 As shown: Due to insufficient distribution of local conductive patterns, a large amount of semi-cured PP will flow into the blank substrate area without conductive patterns, resulting in the actual filling thickness of PP above the conductors and via pads being less than the preset thickness. This directly causes the actual value of the PP layer thickness to be smaller, ultimately resulting in the measured value of the signal line impedance being lower than the theoretical design value.

[0029] The area in the ATE board used to connect BGA packaged chips is a typical area with dense vias. The proportion of conductive patterns in the middle layer of this area is low and the distribution is sparse. During the lamination process, PP is prone to overflow into the blank areas of the substrate, resulting in thinner PP thickness and lower impedance above the conductive patterns, which seriously degrades the high-speed signal transmission performance.

[0030] In conventional PCB design, copper coverage is typically increased and excessive PP flow is suppressed by adding conductors or large areas of copper foil in sparse areas of conductive patterns. However, this patent is applied to high-speed PCB design scenarios. Arbitrarily adding other conductive structures near existing signal lines will introduce additional crosstalk. At the same time, the BGA area of ​​the ATE board has a large number of pins, dense arrangement, and a highly compact via array, which does not allow for the addition of large areas of copper foil due to physical space constraints, making conventional solutions unsuitable.

[0031] Based on the above system analysis, the applicant proposes the technical solution protected by this patent application.

[0032] like Figure 5 and Figure 6 As shown, a method for improving the high-speed signal impedance in a densely via region of a circuit board, the densely via region including multiple signal vias and multiple ground vias; the method includes: In the inner layer of a densely viad area on a circuit board, at least a portion of the ground vias are located around series signal vias and / or signal lines; wherein the signal lines are led out from the signal vias.

[0033] Specifically, in this embodiment, grounding vias are connected in series around existing signals. The additional conductors and pads created by these series-connected grounding vias together form a dam structure. This dam structure limits the overflow of PP (polypropylene) into the blank areas of the substrate during lamination, thereby controlling the PP thickness above the critical signal and ensuring that the impedance value of the critical signal line matches the calculated value. Furthermore, the dam structure formed by the additional conductors and pads near the critical signal due to the series-connected grounding vias does not cause crosstalk to the signal. The grounding vias themselves have a signal shielding effect; this arrangement actually improves the performance of the critical signal, thereby enhancing the quality of high-speed signal transmission and improving the overall chip performance.

[0034] Furthermore, as mentioned earlier, if there is no electrical connection at the inner layer vias, via pads are usually not made. This leads to a decrease in copper coverage, which typically results in uneven copper coverage. Taking the area on an ATE test board used to connect BGA packaged chips as an example, this area exhibits uneven pad distribution; some locations have pads, while others do not. During multilayer board lamination, the thickness of areas without pads will be lower than that of areas with pads. At a microscopic level, this results in inconsistent thickness of the laminated circuit board, thus affecting overall flatness. All pins of the BGA packaged chip need to contact the pads in the top layer BGA area of ​​the ATE board, therefore, the flatness requirements for the BGA area on the ATE board are very high.

[0035] In contrast, the technical solution provided in this embodiment can effectively increase the number of pads and wiring in the BGA area on the inner layer of the ATE board, improve the copper coverage, and thus improve the flatness of the BGA area after lamination of the multilayer board (the flatness of the BGA area of ​​the laminated PCB board can be controlled within 50um / inch), meeting the strict requirements for the flatness of the BGA area on the ATE board.

[0036] One method for connecting grounding vias in series is to fabricate pads for the grounding vias to be connected in series and then connect them with wires.

[0037] Specifically, at least a portion of the grounding vias surrounding the serial signal vias and / or signal lines are: Connect at least a portion of the grounding vias surrounding the signal vias in series to form at least one series line.

[0038] In this case, some grounding vias around the signal vias can be connected in series to form a single series line, or they can be connected in series to form two, three or even more series lines, depending on the specific wiring of the inner layer of the circuit board. Figure 6 The structure shown involves connecting a portion of the grounding vias surrounding the signal vias in series to form multiple series lines.

[0039] In this embodiment, preferably, at least a portion of the ground vias are located around series signal vias and / or signal lines in the inner layer of a densely viad area on the circuit board; specifically including: In the inner layer of a circuit board with a copper coverage ratio less than a first threshold in a densely via area, at least a portion of the ground vias around serial signal vias and / or signal lines.

[0040] More preferably, in the inner layer of a densely via-covered area of ​​the circuit board, at least a portion of the ground vias surrounding the series signal vias; specifically including: In the inner layer where the copper coverage of the dense via region of the circuit board is less than the first threshold, at least a portion of the ground vias around the serial signal vias are made such that the copper coverage of the dense via region of the circuit board is greater than the first threshold but not greater than the second threshold.

[0041] Generally, the first and second thresholds are determined based on experience and can be 30% and 60% respectively.

[0042] It's important to note that this method can be used to improve the impedance of high-speed signals on high-density circuit boards (where there are many signal pins or vias per unit area) with high impedance requirements. Examples include HDI (High-Density Interconnect) boards and ATE (Automatic Test) boards. The more vias connected in series, and the closer the connected ground vias are to the signal lines, the better the improvement. Of course, this is all predicated on not increasing manufacturing complexity or affecting other nearby signal lines.

[0043] For example, BGA packaged chips, and their derivatives PBGA, CBGA, and TBGA packaged chips, have a relatively larger number of pins and a denser pin distribution compared to ordinary packaged chips. Therefore, the copper coverage of the densely via areas on the corresponding ATE board (i.e., the locations connecting BGA, PBGA, CBGA, or TBGA packaged chips) will definitely be less than the first threshold. The above method can improve the excess adhesive in the densely via areas, thereby improving the high-speed signal impedance and bringing it as close as possible to the calculated value.

[0044] The solutions involved in the above embodiments will be described in detail below with reference to specific examples and comparative examples.

[0045] Example: Figure 6As shown, in the dense via area (the location for connecting packaged chips) of the ATE board, a number of ground vias are connected in series around the signal vias and the signal lines led out from the signal vias to form several series lines.

[0046] After testing, the impedance curves of multiple signal lines are as follows: Figure 7 As shown, at the beginning of the impedance curve (marked by a circle; the curve before the circle is the effect of the test fixture, which can be ignored), the impedance is already close to the expected impedance value (the expected impedance is 85 ohms).

[0047] Comparative example: such as Figure 8 As shown, with Figure 6 The difference in the illustrated embodiment is that no grounding vias are connected in series in the inner layer of the densely via area (where the packaged chip is connected) of the ATE board.

[0048] After testing, the impedance curves of multiple signal lines are as follows: Figure 9 As shown, at the beginning of the impedance curve (marked by a circle; the curve before the circle is due to the influence of the test fixture, which can be ignored), the impedance is low (the expected impedance is 85 ohms).

[0049] The effectiveness of the above-described improvement method is demonstrated through comparison of the embodiments and comparative examples, which enables the impedance of the signal line to meet expectations.

[0050] Based on the above-described preferred embodiments of the present invention, and through the foregoing description, those skilled in the art can make various changes and modifications without departing from the inventive concept. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A method for improving the impedance of high-speed signals in densely via regions of a circuit board, characterized in that, The densely viad areas of the circuit board include multiple signal vias and multiple ground vias; the method includes: In the inner layer of the dense via region on the circuit board, at least a portion of the ground vias surrounding the series signal vias and / or signal lines are provided, such that the copper coverage of the dense via region on the circuit board is greater than a first threshold but not greater than a second threshold; wherein the signal lines are led out from the signal vias; the inner layer of the dense via region on the circuit board is specifically: The copper coverage of the densely viad areas of the circuit board is less than the first threshold of the inner layer; The method for connecting grounding vias in series is as follows: the pads of the grounding vias to be connected in series are fabricated and then connected by wires.

2. The method for improving high-speed signal impedance in densely via areas of a circuit board according to claim 1, characterized in that, At least a portion of the ground vias surrounding the serial signal vias and / or signal lines, specifically: Connect at least a portion of the ground vias around the signal vias and / or signal lines in series to form at least one series line.

3. The method for improving high-speed signal impedance in densely via areas of a circuit board according to claim 1, characterized in that, The densely via areas on the circuit board are used to connect the chip to be tested.

4. The method for improving high-speed signal impedance in densely via areas of a circuit board according to claim 3, characterized in that, The types of chips to be tested include BGA packaged chips.

5. The method for improving high-speed signal impedance in densely via areas of a circuit board according to claim 3, characterized in that, The types of chips to be tested include PBGA, CBGA, and TBGA packaged chips.

6. An ATE board, characterized in that, The method for improving the high-speed signal impedance in densely via regions of a circuit board, as described in any one of claims 1-5, is used to improve the high-speed signal impedance in densely via regions.

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