Dual-mode single-pin power supply communication multiplexing interface circuit and testing method

Abstract

The application discloses a dual-mode single-pin power supply communication multiplexing interface circuit and a testing method. The circuit comprises a main control module, a programmable pin driving circuit and a communication / power supply multiplexing pin driving circuit. The main control module is used for outputting a first control signal, a second control signal, an encoding signal, an enabling signal and a package selection signal. The programmable pin driving circuit is used for generating a first adjustable voltage signal according to the first control signal and outputting the first adjustable voltage signal to a chip to be tested, and generating a second adjustable voltage signal according to the second control signal. The communication / power supply multiplexing pin driving circuit is used for enabling the transmission of the encoding signal according to the enabling signal, generating a modulation signal according to the encoding signal and the second adjustable voltage signal, selecting a path signal from the modulation signal and a fixed level according to the package selection signal, and outputting a multiplexing signal to a power supply communication multiplexing pin of the chip to be tested after the path signal is coupled with a reference voltage. The circuit and the testing method improve the universality, reliability and testing efficiency of a testing system.

Description

Technical Field

[0001] This invention relates to the field of sensor chip testing and calibration technology, and in particular to a dual-mode single-pin power supply communication multiplexing interface circuit and testing method. Background Technology

[0002] Hall effect sensors are widely used in automotive electronics, industrial control, and consumer electronics, and their development and mass production stages typically employ different packaging methods. During the development stage, to facilitate debugging and parameter optimization, chips often use discrete packages with independent communication pins and independent power supply pins. However, in the mass production stage, to reduce packaging costs and improve production efficiency, chips often multiplex communication and power supply functions onto the same pin, forming a single-pin power supply and communication multiplexed package.

[0003] However, the two packaging modes mentioned above differ significantly in their electrical interface characteristics: in discrete packaging, the communication pins and power supply pins are independent, allowing test equipment to directly connect and exchange data; in single-pin multiplexed packaging, the test equipment must simultaneously provide power and bidirectional data communication on the same pin, and Manchester encoding is often used to ensure data transmission reliability. Due to the fundamental differences in interface structure, existing test and programming equipment typically only supports one of the packaging modes and is incompatible with chips in both packaging forms.

[0004] This incompatibility has brought a series of problems to the integration of Hall sensor research and development with production. First, different test interfaces or conversion modules need to be configured for the research and development stage and the production stage, increasing equipment procurement costs and debugging complexity. Second, the communication protocols and level requirements differ under different packaging modes, making it impossible to directly reuse the same test program, affecting the consistency and portability of the test system. Third, existing single-pin multiplexed communication circuits generally suffer from insufficient driving capability, imperfect level matching, and signal distortion in high-speed communication, making it difficult to meet the data transmission stability requirements of precise sensor calibration and batch testing.

[0005] To address the aforementioned issues, some existing technologies attempt to achieve mode switching through external adapter boards or manual jumpers. However, such solutions are cumbersome, error-prone, and cannot achieve automated testing. Another solution uses a general-purpose interface chip for level conversion, but it fails to fundamentally solve the problem of unified control of signal paths under the two packaging modes and has insufficient driving capability in multi-channel parallel testing scenarios.

[0006] Therefore, there is an urgent need for an interface circuit and its testing method that can be compatible with dual-package mode, achieve stable power supply and reliable communication, so as to improve the equipment versatility, testing efficiency and communication reliability of Hall sensors in the research and development and production process. Summary of the Invention

[0007] To address the technical problems existing in the background art, this invention proposes a dual-mode single-pin power supply communication multiplexing interface circuit and a testing method.

[0008] This invention proposes a dual-mode single-pin power supply communication multiplexing interface circuit, comprising: The main control module is used to output the first control signal, the second control signal, the encoding signal, the enable signal, and the package selection signal; A programmable pin driver circuit is used to generate a first adjustable voltage signal according to a first control signal and output it to the chip under test through its first output terminal, and to generate a second adjustable voltage signal according to a second control signal and output it through its second output terminal. The communication / power supply multiplexed pin driver circuit has a first input terminal connected to the main control module to receive the encoded signal and the enable signal, a second input terminal connected to the second output terminal of the programmable pin driver circuit to receive the second adjustable voltage signal, a third input terminal connected to the main control module to receive the package selection signal, and an output terminal outputting a multiplexed signal to the power supply and communication multiplexed pin of the chip under test. The communication / power supply multiplexing pin driver circuit enables the transmission of the encoded signal based on the enable signal, generates a modulation signal based on the encoded signal and the second adjustable voltage signal, and selects one of the modulation signal and the fixed level as the path signal based on the package selection signal. After coupling the path signal with the reference voltage, the multiplexed signal is output. The multiplexed signal carries both power supply and Manchester encoded data in the first package mode, and only outputs DC power in the second package mode.

[0009] Preferably, the programmable pin driving circuit includes: The digital-to-analog converter has its first input terminal and second input terminal connected to the first I²C clock line and the first I²C data line of the main control module, respectively. It is used to receive the first control signal and the second control signal as digital signals, convert the first control signal into a first raw voltage signal in analog form and output it from its first output terminal, and convert the second control signal into a second raw voltage signal in analog form and output it from its second output terminal. The first operational amplifier has its input terminal connected to the first output terminal of the digital-to-analog converter to receive the first raw voltage signal. After enhancing the first raw voltage signal, it outputs a first adjustable voltage signal from its output terminal to the chip under test. The second operational amplifier has its input terminal connected to the second output terminal of the digital-to-analog converter to receive the second original voltage signal. After enhancing the second original voltage signal, it outputs a second adjustable voltage signal from its output terminal to the communication / power supply multiplexed pin driver circuit.

[0010] Preferably, the voltage range of the first adjustable voltage signal is 4V to 5.5V, and the voltage range of the second adjustable voltage signal is 0.3V to 1.8V.

[0011] Preferably, the communication / power supply multiplexing pin driving circuit includes: The buffer has its first input terminal connected to the main control module to receive the encoded signal, its second input terminal connected to the main control module to receive the enable signal, and its output terminal outputs the buffered encoded signal when the enable signal is valid. The switching unit has its control terminal connected to the output terminal of the buffer, its power supply terminal connected to the second output terminal of the programmable pin driver circuit to receive the second adjustable voltage signal, and its output terminal outputs a modulation signal whose amplitude is determined by the second adjustable voltage signal according to the on / off state of the buffered encoded signal. An analog switch has a first input terminal connected to the output terminal of a switching unit to receive a modulation signal, a second input terminal connected to a fixed level terminal to receive the fixed level, a control terminal connected to the main control module to receive the encapsulation selection signal, and an output terminal selecting to connect to the first input terminal or the second input terminal according to the encapsulation selection signal, and outputting a path selection signal. The third operational amplifier has a first stage configured as a voltage follower, with its input connected to the output of the analog switch to receive the path selection signal and its output output being a buffered signal; its second stage is configured as a gain amplifier, with its input connected to the output of the first stage, amplifying the buffered signal and superimposing it with the reference voltage to output the multiplexed signal.

[0012] Preferably, the switching unit includes: The first transistor has its base connected to the output of the buffer, its emitter grounded, and its collector connected to the base of the second transistor. The second transistor has its emitter connected to the second output terminal of the programmable pin driver circuit to receive the second adjustable voltage signal, and its collector serves as the output terminal of the switching unit to output the modulation signal. When the buffered encoded signal is high, the first transistor inside the switching unit turns on, driving the second transistor to turn on, so that the output of the switching unit outputs a high level with the amplitude of the second adjustable voltage signal. When the buffered encoded signal is low, the first transistor is turned off, and the second transistor is turned off accordingly, causing the output of the switching unit to output a low level. Thus, the switching unit modulates the second adjustable voltage signal into a pulse-shaped modulation signal whose amplitude is controlled by the voltage signal according to the on / off state of the buffered encoded signal, and outputs it to the first input of the analog switch.

[0013] Preferably, the amplitude of the modulation signal is equal to the voltage value of the second adjustable voltage signal, and the voltage value of the second adjustable voltage signal is configured by the main control module according to the communication level requirements of the chip under test.

[0014] Preferably, the second stage amplification factor of the third operational amplifier is 2.

[0015] Preferably, in the first encapsulation mode, when the encapsulation selection signal is at a low level, the analog switch selects to connect to the first input terminal, so that the multiplexed signal can simultaneously carry power and Manchester encoded data; in the second encapsulation mode, when the encapsulation selection signal is at a high level, the analog switch selects to connect to the second input terminal, so that the multiplexed signal outputs only DC power.

[0016] The present invention proposes a test method for a dual-mode single-pin power supply communication multiplexing interface circuit, comprising the following steps: Acquire the package selection signal and determine the package mode of the chip under test based on the package selection signal; Obtain the preset access code data and generate the encoded signal according to the Manchester encoding rules; Send enable and encoding signals to the communication / power supply multiplexed pin driver circuit to control the communication / power supply multiplexed pin driver circuit to output multiplexed signals to the power supply and communication multiplexed pins of the chip under test, thereby establishing a communication connection; The system acquires the commands and data to be sent, generates Manchester encoded signals, and sends the Manchester encoded signals to the chip under test via multiplexing signals. Receive the returned data from the chip under test, perform CRC verification on the returned data, and obtain the verification result; If the verification result is correct, end the communication and disconnect; if the verification result is incorrect, resend the command and data.

[0017] Preferably, the preset access code data includes 2 synchronization bits, 1 read / write bit, 6 address bits, 30 data bits, and 3 CRC check bits; the read / write bit is fixed at 0 to indicate a write operation, the address bit is fixed at 0x24, and the data bit is fixed at 0x2781_1F77.

[0018] This invention proposes a dual-mode single-pin power supply and communication multiplexing interface circuit and testing method. Through the collaborative design of a programmable pin driver circuit and a communication / power supply multiplexing pin driver circuit, it achieves adaptive compatibility of the same test system for Hall sensor chips with different package forms, solving the problems of equipment incompatibility and test program reuse caused by package differences during the R&D and production stages. In the first package mode, stable power supply and Manchester-encoded data communication can be achieved simultaneously through a single pin. In the second package mode, power supply and communication can be separated and controlled, improving the versatility and flexibility of the test system. Through software control of the package selection signal by the main control module, seamless switching between the two modes is achieved without replacing hardware or adjusting the test interface, simplifying the test process. At the same time, the programmable pin driver circuit can generate a precisely adjustable second voltage signal according to the communication level requirements of the chip under test, and use it to control the amplitude of the modulation signal to ensure level matching and signal integrity during data transmission. The communication / power supply multiplexing pin driver circuit, through the cascaded design of buffers, switching units, analog switches and operational amplifiers, realizes buffering, modulation, path selection, amplification and coupling with the reference voltage of the encoded signal, ensuring the driving capability and stability of the multiplexed signal. By incorporating Manchester encoding and CRC verification mechanisms, highly reliable bidirectional data communication is achieved while ensuring power supply continuity. This improves the equipment versatility, testing efficiency, and communication reliability of Hall sensors in the R&D and production stages, while reducing system costs and maintenance complexity. Attached Figure Description

[0019] Figure 1 A partial circuit diagram of the programmable pin driver circuit for a dual-mode single-pin power supply communication multiplexing interface circuit proposed in this invention. Figure 1 ; Figure 2 A partial circuit diagram of the programmable pin driver circuit for a dual-mode single-pin power supply communication multiplexing interface circuit proposed in this invention. Figure 2 ; Figure 3 The circuit structure diagram of the communication / power supply multiplexing pin driving circuit of the dual-mode single-pin power supply communication multiplexing interface circuit proposed in this invention is shown. Figure 4 This is a flowchart illustrating the testing method for a dual-mode single-pin power supply communication multiplexing interface circuit proposed in this invention. Figure 5 This is a flowchart illustrating one embodiment of the testing method for a dual-mode single-pin power supply communication multiplexing interface circuit proposed in this invention. Detailed Implementation

[0020] Reference Figures 1-5 The present invention proposes a dual-mode single-pin power supply communication multiplexing interface circuit, comprising: The main control module is used to output the first control signal, the second control signal, the encoding signal, the enable signal, and the package selection signal.

[0021] A programmable pin driver circuit is used to generate a first adjustable voltage signal according to a first control signal and output it to the chip under test through its first output terminal, and to generate a second adjustable voltage signal according to a second control signal and output it through its second output terminal.

[0022] The communication / power supply multiplexing pin driver circuit enables the transmission of the encoded signal based on the enable signal, generates a modulation signal based on the encoded signal and the second adjustable voltage signal, and selects one of the modulation signal and the fixed level as the path signal based on the package selection signal. After coupling the path signal with the reference voltage, the multiplexed signal is output. The multiplexed signal carries both power supply and Manchester encoded data in the first package mode, and only outputs DC power in the second package mode.

[0023] In this embodiment, the first encapsulation mode is when the encapsulation selection signal is at a low level, the analog switch selects to connect to the first input terminal, so that the multiplexed signal can simultaneously carry power and Manchester encoded data; the second encapsulation mode is when the encapsulation selection signal is at a high level, the analog switch selects to connect to the second input terminal, so that the multiplexed signal only outputs DC power.

[0024] Specifically, the first packaging mode corresponds to a single-pin multiplexed package for the chip under test (DUT), meaning that the chip's power supply pin also performs Manchester-encoded data communication functions. The second packaging mode corresponds to a split-pin package for the DUT, meaning that the chip has independent power supply and communication pins. The main control module, based on the package type of the DUT, sets the level of the package selection signal via software to achieve adaptive switching between the two modes.

[0025] In this embodiment, the programmable pin driving circuit includes: The digital-to-analog converter has its first input terminal and second input terminal connected to the first I²C clock line and the first I²C data line of the main control module, respectively. It is used to receive the first control signal and the second control signal as digital signals, convert the first control signal into a first raw voltage signal in analog form and output it from its first output terminal, and convert the second control signal into a second raw voltage signal in analog form and output it from its second output terminal. The first operational amplifier has its input terminal connected to the first output terminal of the digital-to-analog converter to receive the first raw voltage signal. After enhancing the first raw voltage signal, it outputs a first adjustable voltage signal from its output terminal to the chip under test. The second operational amplifier has its input terminal connected to the second output terminal of the digital-to-analog converter to receive the second original voltage signal. After enhancing the second original voltage signal, it outputs a second adjustable voltage signal from its output terminal to the communication / power supply multiplexed pin driver circuit.

[0026] The communication / power supply multiplexed pin driver circuit has a first input terminal connected to the main control module to receive the encoded signal and the enable signal, a second input terminal connected to the second output terminal of the programmable pin driver circuit to receive the second adjustable voltage signal, a third input terminal connected to the main control module to receive the package selection signal, and an output terminal outputting a multiplexed signal to the power supply and communication multiplexed pin of the chip under test.

[0027] In this embodiment, the voltage range of the first adjustable voltage signal is 4V to 5.5V, and the voltage range of the second adjustable voltage signal is 0.3V to 1.8V.

[0028] Specifically, such as Figure 1 and Figure 2 As shown, the core component of the programmable pin driver circuit is a dual-channel digital-to-analog converter U1 (specifically, model GP8403-TC50-EW). The first input terminal (SCL pin) and the second input terminal (SDA pin) of U1 are connected to the first I²C clock line and the first I²C data line of the main control module, respectively, to receive the first and second control signals, which are digital signals, from the main control module. U1 converts the first control signal into an analog form of a first raw voltage signal and outputs it from its first output terminal (VOUT1 pin), and converts the second control signal into an analog form of a second raw voltage signal and outputs it from its second output terminal (VOUT2 pin).

[0029] To enhance signal driving capability, the first output terminal of U1 is connected to the input terminal of the first operational amplifier U2 (specifically, LMH6558MA / NOPB). After amplifying the first original voltage signal, U2 outputs a first adjustable voltage signal from its output terminal. This first adjustable voltage signal is output to the chip under test (DUT) through the first output terminal of the programmable pin driver circuit, providing operating power to the DUT. In this embodiment, the voltage range of the first adjustable voltage signal is 4V to 5.5V, which meets the power supply requirements of the DUT.

[0030] The second output terminal of U1 is connected to the input terminal of the second operational amplifier U3 (specifically, LMH6672MA / NOPB). After amplifying the second original voltage signal, U3 outputs a second adjustable voltage signal. This second adjustable voltage signal is output to the communication / power supply multiplexed pin driver circuit through the second output terminal of the programmable pin driver circuit. In this embodiment, the voltage range of the second adjustable voltage signal is 0.3V to 1.8V, used to control the amplitude of the subsequent modulation signal to achieve precise matching with the communication level of the chip under test.

[0031] It is worth noting that the first operational amplifier U2 has multiple output terminals, which can output multiple identical first adjustable voltage signals to multiple chips under test; similarly, the second operational amplifier U3 also has multiple output terminals, which can output multiple identical second adjustable voltage signals to multiple communication / power supply multiplexed pin driver circuits. This design enables the circuit to perform multi-channel parallel testing, significantly improving testing efficiency.

[0032] In this embodiment, the communication / power supply multiplexed pin driving circuit includes: The buffer has its first input terminal connected to the main control module to receive the encoded signal, its second input terminal connected to the main control module to receive the enable signal, and its output terminal outputs the buffered encoded signal when the enable signal is valid. The switching unit has its control terminal connected to the output terminal of the buffer, its power supply terminal connected to the second output terminal of the programmable pin driver circuit to receive the second adjustable voltage signal, and its output terminal outputs a modulation signal whose amplitude is determined by the second adjustable voltage signal according to the on / off state of the buffered encoded signal. An analog switch has its first input terminal connected to the output terminal of a switching unit to receive a modulation signal, its second input terminal connected to a fixed level terminal to receive a fixed level, its control terminal connected to a main control module to receive a package selection signal, and its output terminal selects to connect to the first input terminal or the second input terminal according to the package selection signal, and outputs a path selection signal. The third operational amplifier has a first stage configured as a voltage follower, with its input connected to the output of an analog switch to receive a path selection signal and its output a buffered signal. Its second stage is configured as a gain amplifier, with its input connected to the output of the first stage. It amplifies the buffered signal and superimposes it with a reference voltage to output a multiplexed signal.

[0033] Specifically, the switching unit includes: The first transistor has its base connected to the output of the buffer, its emitter grounded, and its collector connected to the base of the second transistor. The second transistor has its emitter connected to the second output terminal of the programmable pin driver circuit to receive the second adjustable voltage signal, and its collector serves as the output terminal of the switching unit to output the modulation signal. When the buffered encoded signal is high, the first transistor inside the switching unit turns on, driving the second transistor to turn on, so that the output of the switching unit outputs a high level with the amplitude of the second adjustable voltage signal. When the buffered encoded signal is low, the first transistor is turned off, and the second transistor is turned off accordingly, causing the output of the switching unit to output a low level. Thus, the switching unit modulates the second adjustable voltage signal into a pulse-shaped modulation signal whose amplitude is controlled by the voltage signal according to the on / off state of the buffered encoded signal, and outputs it to the first input of the analog switch.

[0034] In this embodiment, the amplitude of the modulation signal is equal to the voltage value of the second adjustable voltage signal, which is configured by the main control module according to the communication level requirements of the chip under test.

[0035] In this embodiment, the second stage gain of the third operational amplifier is 2.

[0036] Specifically, such as Figure 3 As shown, the communication / power supply multiplexed pin drive circuit includes a buffer U4, a switching unit, an analog switch U5, and a third operational amplifier U6.

[0037] The first input of buffer U4 (specifically model SN74LVC1G126DBVR) is connected to the main control module to receive the encoded signal, and its second input is connected to the main control module to receive the enable signal CONNECT_CH1. When the enable signal is high, the output of U4 outputs the buffered encoded signal; when the enable signal is low, the output of U4 is in a high-impedance state.

[0038] The switching unit consists of a first transistor Q1 and a second transistor Q3. The first transistor Q1 (specifically model L2SC1623RLT1G) is an NPN transistor. Its base is connected to the output of buffer U4 to receive the buffered encoded signal, its emitter is grounded, and its collector is connected to the base of the second transistor Q3. The second transistor Q3 (specifically model NSS40201LT1G) is a high-voltage PNP transistor. Its emitter is connected to the second output of the programmable pin driver circuit to receive the second adjustable voltage signal, and its collector serves as the output of the switching unit.

[0039] The switching unit operates as follows: When the buffered encoded signal is high, the first transistor Q1 is turned on, its collector voltage is pulled low, thus turning on the second transistor Q3. The output of the switching unit is high, equal to the amplitude of the second adjustable voltage signal. When the buffered encoded signal is low, the first transistor Q1 is turned off, and the second transistor Q3 is also turned off, resulting in a low output from the switching unit. Thus, the switching unit modulates the second adjustable voltage signal into a pulse-like signal with an amplitude controlled by the buffered encoded signal, based on the on / off state of the signal. In other words, the amplitude of the modulated signal is equal to the voltage value of the second adjustable voltage signal, which is configured by the main control module according to the communication level requirements of the chip under test, thereby achieving programmable control of the communication level.

[0040] Analog switch U5 (specifically model TS5A3159DBVR) is a single-pole double-throw switch. Its first input terminal is connected to the output terminal of the switching unit to receive the modulation signal, and its second input terminal is connected to the fixed-level terminal to receive the fixed level (in this embodiment, the fixed level is 0V, i.e., ground). Its control terminal is connected to the main control module to receive the package selection signal PACK_SELE. The output terminal of analog switch U5 connects to either the first input terminal or the second input terminal according to the level of the package selection signal: when the package selection signal is low, U5 connects to the first input terminal and outputs the modulation signal as the path selection signal; when the package selection signal is high, U5 connects to the second input terminal and outputs the fixed level as the path selection signal.

[0041] The third operational amplifier U6 (specifically model LMH6658MA / NOPB) is a dual-channel high-speed operational amplifier, with its first stage configured as a voltage follower. The input of the first stage of U6 is connected to the output of analog switch U5 to receive the path selection signal, and its first stage output is a buffered signal, providing high input impedance and stable drive for subsequent stages.

[0042] The second stage of U6 is configured as a non-inverting gain amplifier, with its input connected to the output of the first stage. In this embodiment, the gain factor of the gain amplifier is determined by the ratio of resistors R27 and R26, specifically set to R27 / R26=2, i.e., the gain factor is 2. The second stage of U6 amplifies the buffered signal by 2 times, then superimposes it with a 4.5V reference voltage, and finally outputs a multiplexed signal 5V_CH1_POWER to the power supply and communication multiplexed pin of the chip under test.

[0043] The multiplexed signal exhibits different characteristics under different packaging modes: In the first packaging mode (the package selection signal is low), the analog switch U5 selects the modulation signal path. At this time, the multiplexed signal is a composite signal with Manchester encoded data superimposed on a 4.5V DC bias, carrying both power and communication data. In the second packaging mode (the package selection signal is high), the analog switch U5 selects the fixed level path. At this time, the multiplexed signal is only a 4.5V DC power supply used for chip power supply.

[0044] Reference Figures 1-5 The present invention proposes a test method for a dual-mode single-pin power supply communication multiplexing interface circuit, comprising the following steps: S1. Obtain the package selection signal and determine the package mode of the chip under test based on the package selection signal.

[0045] In this embodiment, as Figure 5 As shown, after the system powers on, the main control module first acquires the package selection signal. This package selection signal can be configured by the user via host computer software or set via a hardware DIP switch. The main control module determines the package mode of the chip under test based on the level of the package selection signal: if the package selection signal is low, it is determined to be the first package mode (single-pin multiplexed package); if the package selection signal is high, it is determined to be the second package mode (split-pin package).

[0046] S2. Obtain the preset access code data and generate the encoded signal according to the Manchester encoding rules.

[0047] In this embodiment, the preset access code data includes 2 synchronization bits, 1 read / write bit, 6 address bits, 30 data bits, and 3 CRC check bits; the read / write bit is fixed at 0 to indicate a write operation, the address bit is fixed at 0x24, and the data bit is fixed at 0x2781_1F77.

[0048] Specifically, the preset access code data acquired by the main control module is designed specifically for a particular model of Hall sensor, and its specific format includes: Two synchronization bits (fixed to "00") are used to synchronize the start of data transmission. One read / write bit (fixed to "0") indicates that a write operation is currently in progress; The 6-bit address (fixed to a binary value of 0x24) specifies the fixed address accessed by the client. 30 data bits (fixed at 0x2781_1F77) are the preset access data; Three CRC check bits are used to verify the integrity of the data.

[0049] It should be noted that the main control module converts the access code data into an encoded signal according to the Manchester encoding rules. The Manchester encoding rules are: each data bit has a level transition in the middle, with a high-to-low transition representing "0" and a low-to-high transition representing "1". Subsequently, the main control module sends an enable signal (set to high level) and the generated encoded signal to the communication / power supply multiplexed pin driver circuit. The communication / power supply multiplexed pin driver circuit generates a corresponding multiplexed signal based on the enable signal and the encoded signal, combined with the current package mode, and sends it to the chip under test (DUT) through the power supply / communication multiplexed pin. After receiving the access code, the DUT performs CRC check and address matching; if the check passes, a communication connection is established. In this embodiment, the main control module needs to complete the transmission of the access code within a preset t_ACC timeout period after power-on. t_ACC is the access code timeout period, and its specific value is determined according to the specifications of the DUT.

[0050] S3. Send an enable signal and an encoding signal to the communication / power supply multiplexed pin driver circuit to control the communication / power supply multiplexed pin driver circuit to output multiplexed signals to the power supply and communication multiplexed pins of the chip under test, thereby establishing a communication connection.

[0051] S4. Obtain the commands and data to be sent, generate Manchester encoded signals, and send the Manchester encoded signals to the chip under test through multiplexing signals.

[0052] In this embodiment, after the communication connection is established, the main control module acquires the commands and data to be sent. Depending on the testing requirements, the commands may include writing configuration parameters, reading sensor data, etc. The main control module organizes the commands and data into data frames according to a preset communication protocol and generates corresponding encoded signals according to Manchester encoding rules.

[0053] The encoded signal is sent to the chip under test through the established communication path: in the first package mode, the encoded signal is sent through a multiplexed signal (power supply and communication multiplexed pin); in the second package mode, the encoded signal is sent through an independent communication pin connected to the chip under test.

[0054] S5. Receive the returned data from the chip under test, and perform CRC verification on the returned data to obtain the verification result.

[0055] It should be noted that the returned data also uses Manchester encoding. The main control module performs edge detection and data frame recovery on it. After recovering the original data, the data is checked by CRC to obtain the verification result.

[0056] S6. If the verification result is correct, end the communication and disconnect; if the verification result is incorrect, resend the command and data.

[0057] In this embodiment, if the verification result is correct, it indicates that the communication was successful. The main control module ends the current communication process by setting the enable signal to a low level, closing the communication channel, and the system enters standby mode to wait for the next test.

[0058] If the verification result is incorrect, it indicates an error occurred during data transmission. The main control module will resend the commands and data according to the preset retry logic. If multiple retries fail consecutively, the main control module will report an error and terminate the current test.

[0059] In this embodiment, since both the first operational amplifier U2 and the second operational amplifier U3 have multi-output capabilities, this method can be applied to multiple chips under test simultaneously. The main control module establishes communication with each chip sequentially, sends commands, and receives data through time-division multiplexing or independent control, thereby achieving parallel testing and significantly improving testing efficiency.

[0060] Specifically, based on Figures 1 to 3 The single-channel structure shown in this invention achieves multi-channel parallel capability through bus expansion and independent channel control.

[0061] In the programmable pin driver circuit, the digital-to-analog converter U1 is expanded using an I²C bus cascade method: the main control module connects multiple U1 chips via the first I²C bus, each U1 having an independent device address (configured via hardware pins or software), thereby generating multiple sets of independent raw voltage signals. Each set of raw voltage signals is amplified by the corresponding first operational amplifier U2 and second operational amplifier U3, forming multiple sets of first adjustable voltage signals and multiple sets of second adjustable voltage signals, which are output to the corresponding chip under test and the corresponding communication / power supply multiplexed pin driver circuit, respectively. The first operational amplifier U2 and the second operational amplifier U3 are both designed as multi-output types, with each output corresponding to an independent test channel. The channels are electrically isolated from each other and do not interfere with each other.

[0062] Correspondingly, the communication / power supply multiplexed pin driver circuits are also set up independently for each channel. Each channel includes, for example, the following: Figure 3 The buffer U4, switching unit, analog switch U5, and third operational amplifier U6 are shown. The enable signal (CONNECT_CHn), encoding signal (DATA_CHn), and package selection signal (PACK_SELn) for each channel are provided by the main control module through independent GPIO ports or extended I / O chips, thereby enabling independent control of each channel. Each channel can operate independently in either the first or second package mode, allowing chips in single-pin multiplexed packages and chips in multi-pin packages to coexist in the same test system.

[0063] To enable parallel communication across multiple chips, the main control module incorporates a multi-channel communication scheduler, employing a combination of time-division multiplexing and interrupt priority to manage Manchester-encoded communication. Specifically: For write operations, the main control module polls each channel according to a preset time slice and sends access codes and command data in sequence to avoid multiple chips occupying the bus at the same time. For read operations, the main control module allocates an independent response time window for each channel. If the chip supports asynchronous response, the main control module is triggered to read via an interrupt, thereby improving real-time performance.

[0064] At the data receiving end, the main control module integrates a multi-channel DMA controller and a hardware CRC calculation unit. When multiple chips return data simultaneously, the DMA controller moves the data from each channel to an independent buffer, and the hardware CRC unit verifies multiple data frames in parallel. The verification result is notified to the main control module via an interrupt or a flag, which significantly reduces the CPU load and improves test throughput.

[0065] In addition, each drive circuit's output is equipped with a voltage / current monitoring and protection circuit, including a sampling resistor and a comparator. When a power supply abnormality (such as overcurrent or short circuit) or communication timeout is detected in a channel, the main control module immediately blocks the enable signal of that channel, cuts off the channel's output, and records the fault status. Meanwhile, other channels continue to operate normally, achieving fault isolation and ensuring the overall reliability of the test system.

[0066] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A dual-mode single-pin powered communication multiplexing interface circuit, characterized in that, include: The main control module is used to output the first control signal, the second control signal, the encoding signal, the enable signal, and the package selection signal; A programmable pin driver circuit is used to generate a first adjustable voltage signal according to a first control signal and output it to the chip under test through its first output terminal, and to generate a second adjustable voltage signal according to a second control signal and output it through its second output terminal. The communication / power supply multiplexed pin driver circuit has a first input terminal connected to the main control module to receive the encoded signal and the enable signal, a second input terminal connected to the second output terminal of the programmable pin driver circuit to receive the second adjustable voltage signal, a third input terminal connected to the main control module to receive the package selection signal, and an output terminal outputting a multiplexed signal to the power supply and communication multiplexed pin of the chip under test. The communication / power supply multiplexing pin driving circuit enables the transmission of the encoded signal according to the enable signal, generates a modulation signal according to the encoded signal and the second adjustable voltage signal, and selects one of the modulation signal and the fixed level as the path signal according to the package selection signal. After coupling the path signal with the reference voltage, the multiplexing signal is output. In the first package mode, the multiplexed signal carries both power supply and Manchester encoded data, while in the second package mode, it outputs only DC power supply.

2. The dual-mode single-pin power supply communication multiplexing interface circuit according to claim 1, characterized in that, The programmable pin driving circuit includes: The digital-to-analog converter has its first input terminal and second input terminal connected to the first I²C clock line and the first I²C data line of the main control module, respectively. It is used to receive the first control signal and the second control signal as digital signals, convert the first control signal into a first raw voltage signal in analog form and output it from its first output terminal, and convert the second control signal into a second raw voltage signal in analog form and output it from its second output terminal. The first operational amplifier has its input terminal connected to the first output terminal of the digital-to-analog converter to receive the first raw voltage signal. After enhancing the first raw voltage signal, it outputs a first adjustable voltage signal from its output terminal to the chip under test. The second operational amplifier has its input terminal connected to the second output terminal of the digital-to-analog converter to receive the second original voltage signal. After enhancing the second original voltage signal, it outputs a second adjustable voltage signal from its output terminal to the communication / power supply multiplexed pin driver circuit.

3. The dual-mode single-pin power supply communication multiplexing interface circuit according to claim 2, characterized in that, The voltage range of the first adjustable voltage signal is 4V to 5.5V, and the voltage range of the second adjustable voltage signal is 0.3V to 1.8V.

4. The dual-mode single-pin power supply communication multiplexing interface circuit according to claim 1, characterized in that, The communication / power supply multiplexed pin driving circuit includes: The buffer has its first input terminal connected to the main control module to receive the encoded signal, its second input terminal connected to the main control module to receive the enable signal, and its output terminal outputs the buffered encoded signal when the enable signal is valid. The switching unit has its control terminal connected to the output terminal of the buffer, its power supply terminal connected to the second output terminal of the programmable pin driver circuit to receive the second adjustable voltage signal, and its output terminal outputs a modulation signal whose amplitude is determined by the second adjustable voltage signal according to the on / off state of the buffered encoded signal. An analog switch has a first input terminal connected to the output terminal of a switching unit to receive a modulation signal, a second input terminal connected to a fixed level terminal to receive the fixed level, a control terminal connected to the main control module to receive the encapsulation selection signal, and an output terminal selecting to connect to the first input terminal or the second input terminal according to the encapsulation selection signal, and outputting a path selection signal. The third operational amplifier has a first stage configured as a voltage follower, with its input connected to the output of the analog switch to receive the path selection signal and its output output being a buffered signal; its second stage is configured as a gain amplifier, with its input connected to the output of the first stage, amplifying the buffered signal and superimposing it with the reference voltage to output the multiplexed signal.

5. The dual-mode single-pin power supply communication multiplexing interface circuit according to claim 4, characterized in that, The switching unit includes: The first transistor has its base connected to the output of the buffer, its emitter grounded, and its collector connected to the base of the second transistor. The second transistor has its emitter connected to the second output terminal of the programmable pin driver circuit to receive the second adjustable voltage signal, and its collector serves as the output terminal of the switching unit to output the modulation signal. When the buffered encoded signal is high, the first transistor inside the switching unit turns on, driving the second transistor to turn on, so that the output of the switching unit outputs a high level with the amplitude of the second adjustable voltage signal. When the buffered encoded signal is low, the first transistor is turned off, and the second transistor is turned off accordingly, causing the output of the switching unit to output a low level. Thus, the switching unit modulates the second adjustable voltage signal into a pulse-shaped modulation signal whose amplitude is controlled by the voltage signal according to the on / off state of the buffered encoded signal, and outputs it to the first input of the analog switch.

6. The dual-mode single-pin power supply communication multiplexing interface circuit according to claim 4 or 5, characterized in that, The amplitude of the modulation signal is equal to the voltage value of the second adjustable voltage signal, which is configured by the main control module according to the communication level requirements of the chip under test.

7. The dual-mode single-pin power supply communication multiplexing interface circuit according to claim 4, characterized in that, The second stage amplification factor of the third operational amplifier is 2.

8. The dual-mode single-pin power supply communication multiplexing interface circuit according to claim 4, characterized in that, In the first encapsulation mode, when the encapsulation selection signal is low, the analog switch connects to the first input terminal, allowing the multiplexed signal to simultaneously carry power and Manchester-encoded data. In the second encapsulation mode, when the encapsulation selection signal is high, the analog switch connects to the second input terminal, allowing the multiplexed signal to output only DC power.

9. A test method for the dual-mode single-pin power supply communication multiplexing interface circuit according to any one of claims 1-8, characterized in that, Includes the following steps: Acquire the package selection signal and determine the package mode of the chip under test based on the package selection signal; Obtain the preset access code data and generate the encoded signal according to the Manchester encoding rules; Send enable and encoding signals to the communication / power supply multiplexed pin driver circuit to control the communication / power supply multiplexed pin driver circuit to output multiplexed signals to the power supply and communication multiplexed pins of the chip under test, thereby establishing a communication connection; The system acquires the commands and data to be sent, generates Manchester encoded signals, and sends the Manchester encoded signals to the chip under test via multiplexing signals. Receive returned data from the chip under test, perform CRC check on the returned data, and obtain the check result; If the verification result is correct, end the communication and disconnect. If the verification result is incorrect, resend the command and data.

10. The test method for the dual-mode single-pin power supply communication multiplexing interface circuit according to claim 9, characterized in that, The preset access code data includes 2 synchronization bits, 1 read / write bit, 6 address bits, 30 data bits, and 3 CRC check bits; the read / write bit is fixed at 0 to indicate a write operation, the address bit is fixed at 0x24, and the data bit is fixed at 0x2781_1F77.

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