Data reading method, memory and computer program product

Abstract

The application discloses a data reading method, a memory and a computer program product, and relates to the technical field of storage. The data reading method comprises the following steps: a memory receives a data reading instruction, splits the data reading instruction into at least one reading request based on the continuity of a target physical address corresponding to the data reading instruction and a parallel storage unit to which the target physical address belongs, wherein the physical address corresponding to one reading request is continuous and belongs to one parallel storage unit; the reading request is added to a request queue under the corresponding parallel storage unit; and data is read in parallel through the parallel storage units and the request queues of the parallel storage units. In the application, any length of data reading instruction can participate in the concurrent reading process after being converted into a reading request, and the data reading performance in a random mixed reading scene can be greatly improved. Meanwhile, the application does not need to switch reading strategies according to the length of the reading instruction, so that the overhead can be further reduced and the performance in the mixed reading scene can be improved.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a data reading method, a memory, and a computer program product. Background Technology

[0002] In the field of storage technology, random read speeds of 4KB are a typical performance benchmark. Therefore, current flash storage devices are optimized for 4KB random read speeds. For example, flash storage devices typically aggregate multiple 4KB random reads at the FTL (Flash Translation Layer) layer for continuous processing, using the concurrency characteristics of the storage device to issue multiple 4KB read requests simultaneously to accelerate 4KB read performance. Although this approach can achieve good scores in performance benchmarking scenarios and improve read performance to some extent in practical applications, it is difficult to achieve good performance in actual mixed random read scenarios because it is only optimized for a single read scenario.

[0003] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0004] The main purpose of this application is to provide a data reading method, a memory, and a computer program product, which aims to solve the technical problem that traditional data reading schemes are difficult to achieve good performance in practical mixed random read scenarios.

[0005] To achieve the above objectives, this application proposes a data reading method applied to a memory, the memory including parallel storage units, the data reading method comprising: Upon receiving a data read instruction, based on the continuity of the target physical address corresponding to the data read instruction and the parallel storage unit to which it belongs, the data read instruction is split into at least one read request, wherein the physical addresses corresponding to one read request are continuous and belong to one parallel storage unit. Add the read request to the request queue under the corresponding parallel storage unit; Data is read in parallel through each parallel storage unit and the request queue of each parallel storage unit.

[0006] Optionally, the step of splitting the data read instruction into at least one read request based on the contiguousness of the target physical address corresponding to the data read instruction and the parallel storage unit to which it belongs includes: When the target physical addresses belong to the same parallel memory unit, the first continuity of the target physical addresses is determined; When the first continuity is discontinuous, based on the address discrete characteristics of the target physical address, the data read instruction is split into individual read requests; and / or, If the first continuity is continuous, the data read instruction is treated as a read request.

[0007] Optionally, the step of splitting the data read instruction into at least one read request based on the contiguousness of the target physical address corresponding to the data read instruction and the parallel storage unit to which it belongs further includes: When the target physical address belongs to different parallel storage units, the data read instruction is split into sub-data read instructions according to the affiliation relationship between the target physical address and each parallel storage unit; For any one of the sub-data read instructions, determine the second continuity of the sub-target physical address corresponding to the sub-data read instruction; When the second continuity is discontinuous, based on the address discrete characteristics of the sub-target physical address, the sub-data read instruction is split into each of the read requests; and / or, When the second continuity is continuous, the sub-data read instruction is treated as a read request.

[0008] Optionally, before the step of splitting the data read instruction into at least one read request based on the contiguousness of the target physical address corresponding to the data read instruction and the parallel storage unit to which it belongs, the method further includes: Based on the device function and / or device status of the memory, parallel storage cells of the memory are selected, wherein the types of parallel storage cells include the plane of the memory, the chip of the memory, and the channel of the memory, and the plane has a higher selection priority than the chip and the channel.

[0009] Optionally, the step of reading data in parallel through each parallel storage unit and the request queue of each parallel storage unit includes: The data unit set is obtained by performing parallel read operations through each parallel storage unit and the request queue of each parallel storage unit; Based on the data unit set, determine the target data read instruction to complete the data reading, and return the target data requested by the target data read instruction.

[0010] Optionally, a data read instruction is configured with a data buffer; The step of determining the target data read instruction based on the data unit set after data reading is completed includes: The data units in the data unit set are stored in the corresponding data cache area; Determine the target cache area to store all the data, wherein the data length in the target cache area is consistent with the expected data length of the data read instruction corresponding to the target cache area; The data read instruction corresponding to the target buffer is used as the target data read instruction.

[0011] Optionally, after the step of receiving the data read instruction, the method further includes: Configure a data buffer for the data read instruction based on the maximum read length of the data read instruction or the expected data length of the data read instruction.

[0012] Optionally, the step of storing the data units in the data unit set in the corresponding data cache area includes: For any data unit to be stored in the data unit set, determine the data read instruction to which the read request pointing to the data unit to be stored belongs; The data unit to be stored is stored in the data cache area corresponding to the data read instruction. Optionally, the step of returning the target data requested by the target data read instruction includes: The data in the target cache is used as the target data requested by the target data read instruction; The target data is returned to the sender of the target data read instruction.

[0013] Optionally, after the step of returning the target data requested by the target data read instruction, the method includes: If the request queues of each parallel storage unit are not empty, return to the step of performing parallel read operations through each parallel storage unit and its request queue to obtain a data unit set, until the request queues of each parallel storage unit are empty.

[0014] Optionally, the step of performing parallel read operations through each parallel storage unit and the request queue of each parallel storage unit to obtain a data unit set includes: For any one of the parallel storage units, the data unit is obtained by executing the read request of the current read round in the request queue corresponding to the parallel storage unit, and the read request of the current read round is removed from the corresponding request queue. The data unit set is formed based on the data units obtained from each parallel storage unit.

[0015] Optionally, after the step of receiving the data read instruction, the method includes: Determine the size of the data to be read as pointed to by the data read instruction; If the data size is greater than a preset size, the step of splitting the data read instruction into at least one read request based on the contiguousness of the target physical address corresponding to the data read instruction and the parallel storage unit to which it belongs is executed; and / or, If the data size is less than or equal to the preset size, the data read instruction is treated as a read request.

[0016] In addition, to achieve the above objectives, this application also proposes a memory, which includes a main control chip and a storage chip, wherein the storage chip stores a computer program, and the main control chip executes the computer program to implement the data reading method described above.

[0017] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the data reading method described above.

[0018] In addition, to achieve the above objectives, this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the data reading method described above.

[0019] One or more technical solutions proposed in this application have at least the following technical effects: In this embodiment, the memory includes parallel storage units. The memory receives a data read instruction and, based on the continuity of the target physical address corresponding to the data read instruction and the parallel storage unit to which it belongs, splits the data read instruction into at least one read request. Each read request corresponds to a continuous physical address and belongs to a single parallel storage unit. The read request is added to the request queue of the corresponding parallel storage unit. Data is read in parallel through each parallel storage unit and its request queue. That is, the memory in this application can generate read requests with continuous physical addresses belonging to the same parallel storage unit based on the continuity of the target physical address corresponding to the received data read instruction and the parallel storage unit to which it belongs, thereby ensuring that a read request can be completed independently by a parallel storage unit in a single read operation. The read request is then added to the corresponding request queue, allowing the read requests in the queue to be processed and read in parallel by each parallel storage unit in an orderly manner. Compared to traditional solutions that optimize only for read scenarios with a single data length, in this application, data read instructions of any length, after being split into read requests, can participate in the concurrent read process. Therefore, data read performance in random mixed read scenarios can be significantly improved. Meanwhile, since this application does not require switching between parallel and non-parallel reading strategies based on the length of the data in the read instruction, it can further reduce overhead and improve performance in mixed read scenarios. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the first process of an embodiment of the data reading method of this application; Figure 2 This is a schematic diagram of the second process in an embodiment of the data reading method of this application; Figure 3 This is a schematic diagram of a scenario in the data reading method of this application; Figure 4 This is a schematic diagram of the third process in an embodiment of the data reading method of this application; Figure 5 This is a schematic diagram of the fourth process in an embodiment of the data reading method of this application; Figure 6This is a schematic diagram illustrating the configuration of the data cache area in the data reading method of this application; Figure 7 This is a schematic diagram of the fifth process in an embodiment of the data reading method of this application; Figure 8 This is a schematic diagram of the memory structure involved in the data reading method in the embodiments of this application.

[0023] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0024] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0025] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0026] In the storage technology field, random reads of 4KB size are a typical performance benchmark. Therefore, current flash storage devices are optimized for 4KB random reads. For example, flash storage devices typically aggregate multiple 4KB random reads at the FTL (Flash Translation Layer) for continuous processing, leveraging the concurrency characteristics of the storage device to simultaneously issue multiple 4KB read requests to accelerate 4KB read performance. While this approach can achieve good scores in performance benchmarks and improve read performance to some extent in practical applications, it is optimized only for a single read scenario. Therefore, it is difficult to achieve good performance in real-world mixed random read scenarios. Furthermore, it should be noted that because traditional solutions lack dedicated mechanisms for handling read requests larger than 4KB, the flash FTL switches between 4KB concurrent and non-4KB concurrent scheduling modes when I / O is mixed, further impacting storage performance.

[0027] The main solution of this application embodiment is: the memory includes parallel storage units, the memory receives a data read instruction, and based on the continuity of the target physical address corresponding to the data read instruction and the parallel storage unit to which it belongs, the data read instruction is split into at least one read request, wherein the physical address corresponding to a read request is continuous and belongs to a parallel storage unit; the read request is added to the request queue under the corresponding parallel storage unit; and data is read in parallel through each parallel storage unit and the request queue of each parallel storage unit.

[0028] In this application, the memory can generate read requests with contiguous physical addresses belonging to the same parallel memory unit based on the continuity of the target physical address corresponding to the received data read instruction and the parallel memory unit to which it belongs. This ensures that a read request can be completed independently by the parallel memory unit in a single read operation. The read requests are then added to the corresponding request queue, allowing the read requests in the queue to be processed and read in parallel by each parallel memory unit in an orderly manner. Compared to traditional solutions that optimize only for read scenarios with a single data length, in this application, data read instructions of any length can participate in the concurrent read process after being split into read requests. Therefore, it can significantly improve data read performance in random mixed read scenarios. Furthermore, since this application does not require switching between parallel and non-parallel read strategies based on the data length of the read instruction, it can further reduce overhead and improve performance in mixed read scenarios.

[0029] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication and program execution functions, such as a memory, computer, mobile phone, etc., or an electronic device capable of realizing the above functions.

[0030] Reference Figure 1 , Figure 1 This illustration shows a first flowchart of a data reading method provided in an embodiment of this application. In this embodiment, the method is applied to a memory, which includes parallel storage units. The data reading method includes steps S10 to S30: Step S10: Receive a data read instruction. Based on the continuity of the target physical address corresponding to the data read instruction and the parallel storage unit to which it belongs, split the data read instruction into at least one read request. Among them, the physical addresses corresponding to a read request are continuous and belong to a parallel storage unit. It should be noted that in this embodiment, the above-described data reading method can be applied to a memory, and correspondingly, the memory or the main controller (or main controller chip) within the memory can serve as the execution entity of the above-described data reading method. The memory includes parallel storage units. The type of parallel storage unit can be determined by the concurrency mechanism of the memory. Generally speaking, a parallel storage unit refers to a storage hardware unit within the memory that can independently perform read operations and work in parallel with other units. Optionally, a parallel storage unit can be a plane within the memory. Multiple planes can be contained within the same flash memory die, each with its own independent page register, enabling simultaneous read operations through multi-plane read commands. Optionally, a parallel storage unit can also be a flash memory die, channel, or chip, etc. Typically, the memory can receive multiple data read commands sent by the host at once. In this embodiment, the processing logic for each data read command is consistent; therefore, one example will be used for explanation in the following sections.

[0031] For example, the memory generates a read request based on the received data read instruction. Optionally, the logical address in the data read instruction is first parsed, and the physical address corresponding to the logical address, i.e., the target physical address, is determined by querying a mapping table. The continuity of the target physical address and its corresponding parallel storage cell are then determined. The continuity of the target physical address refers to whether the address numbers of the data stored on the flash memory physical medium are numerically adjacent. For example, in NAND flash memory, if multiple 4KB data cells are located within the same physical page or on consecutive page addresses within the same plane, then the addresses of these physical cells constitute a contiguous address space. Based on the continuity of the target physical address and the corresponding parallel storage cell, the data read instruction is then split into at least one read request. The split read requests must meet specific conditions, namely, the physical addresses corresponding to the read requests must be consecutive and belong to the same parallel storage cell. Optionally, if the data read instruction itself meets this specific condition (consecutive physical addresses and belonging to the same parallel storage cell), then the data read instruction can be considered as a single read request. Conversely, if the specific condition is not met, the data read instruction needs to be split into multiple read requests, ensuring that each split read request meets the aforementioned specific condition.

[0032] For example, if the host issues a 16KB data read command with contiguous logical addresses, a lookup in the mapping table reveals that the four 4KB physical units corresponding to this 16KB data are all located within the same physical page (Plane0) on the same plane (physical page size is 16KB, with offsets of 0, 4KB, 8K, and 12K respectively), and their physical addresses are contiguous. The main control chip then directly generates a read request for this 16KB command, with a request size of 16KB, contiguous physical addresses, and belonging to Plane0.

[0033] It is understood that, in this embodiment, by generating read requests with contiguous physical addresses belonging to the same parallel storage unit, it is ensured that a read request can be completed independently by the parallel storage unit in a single read operation, laying the foundation for subsequent queuing and parallel reading by parallel storage unit. Moreover, data read instructions of any length can be processed to generate read requests and participate in subsequent parallel read operations.

[0034] Step S20: Add the read request to the request queue under the corresponding parallel storage unit; It should be noted that each parallel memory cell in the memory can maintain a first-in-first-out (FIFO) or priority-based queue of pending read requests. That is, each parallel memory cell can have an independent request queue to temporarily store read requests belonging to that parallel memory cell.

[0035] For example, after a read request is generated, the memory can add it to the tail of the request queue of the corresponding parallel memory cell based on the parallel memory cell to which the read request belongs. For instance, if the physical address pointed to by a read request belongs to a certain parallel memory cell, then the read request and that parallel memory cell can be considered to have a corresponding relationship. Optionally, if the firmware of the aforementioned memory supports request priority, it can also insert the request into an appropriate position in the queue according to its urgency. For example, a 16KB read request belonging to Plane0 is generated and added to Plane0's request queue. At the same time, another 4KB read request belonging to Plane1 can be added to Plane1's request queue.

[0036] It is understood that, in this embodiment, by establishing an independent request queue for each parallel storage unit, physical resource isolation of requests is achieved, avoiding mutual blocking of tasks between different units. The queue mechanism allows read requests to be continuously sent to the flash memory in a pipelined manner, improving request submission efficiency and providing data preparation for subsequent parallel scheduling.

[0037] Step S30: Read data in parallel through each parallel storage unit and the request queue of each parallel storage unit.

[0038] For example, the memory can process read requests in each request queue in parallel through its parallel storage cells, thereby achieving parallel data reading. Optionally, the memory controller can select one read request from each queue and concurrently issue read commands to the storage medium (or flash memory) in the memory. The parallel storage cells in the flash memory then process the read requests in parallel. It should be noted that if the memory supports multi-plane concurrent read, the memory controller can merge read commands from different planes belonging to the same die into a single multi-plane command packet and send it all at once; if only die-level concurrency is supported, independent commands are issued to multiple dies simultaneously through multiple channels or chip select signals. All concurrent read operations are executed concurrently in time to fully utilize the parallel resources within the memory.

[0039] Understandably, by merging multiple independent host read requests at the physical layer, the problem of idle parallel resources in traditional sequential processing is eliminated. This is especially true for random read loads of mixed sizes and dispersed physical addresses, which can significantly improve data read performance and reduce average read latency.

[0040] In this embodiment, the memory includes parallel storage units. The memory receives a data read instruction and, based on the continuity of the target physical address corresponding to the data read instruction and the parallel storage unit to which it belongs, splits the data read instruction into at least one read request. Each read request corresponds to a continuous physical address and belongs to a single parallel storage unit. The read request is added to the request queue of the corresponding parallel storage unit. Data is read in parallel through each parallel storage unit and its request queue. That is, the memory in this application can generate read requests with continuous physical addresses belonging to the same parallel storage unit based on the continuity of the target physical address corresponding to the received data read instruction and the parallel storage unit to which it belongs, thereby ensuring that a read request can be completed independently by a parallel storage unit in a single read operation. The read request is then added to the corresponding request queue, allowing the read requests in the queue to be processed and read in parallel by each parallel storage unit in an orderly manner. Compared to traditional solutions that optimize only for read scenarios with a single data length, in this application, data read instructions of any length, after being split into read requests, can participate in the concurrent read process. Therefore, data read performance in random mixed read scenarios can be significantly improved. Meanwhile, since this application does not require switching between parallel and non-parallel reading strategies based on the length of the data in the read instruction, it can further reduce overhead and improve performance in mixed read scenarios.

[0041] In one feasible implementation, before the step of splitting a data read instruction into at least one read request based on the contiguousness of the target physical address corresponding to the data read instruction and the parallel memory cell to which it belongs, the method further includes step S100: Step S100: Based on the device function and / or device status of the memory, select parallel storage cells of the memory. The types of parallel storage cells include memory planes, memory chips, and memory channels. The selection priority of planes is higher than that of chips and channels.

[0042] It should be noted that the aforementioned device functions can refer to the parallel processing capabilities supported by the memory hardware, such as whether the memory supports multi-plane parallel reads, multi-chip parallel processing, and multi-channel parallel processing. This information can be obtained by reading the controller registers in the memory or through firmware configuration. Device status refers to the dynamic parameters of the memory during operation, including but not limited to the load (queue depth), temperature, and resource limits of each parallel memory cell. This status can be obtained in real time through firmware monitoring. Furthermore, device functions and / or device status can be used for the selection of parallel memory cells.

[0043] For example, during the initialization phase or periodic operation, the memory assesses its current hardware capabilities and operating status, selects the currently available parallel storage unit type according to a preset priority (e.g., plane > chip and channel), and uses it as the basic unit for subsequent concurrent scheduling. The selection result can be used in step S10 and subsequent processes. For example, the selection process can be as follows: planes are preferred as parallel storage units. If the memory supports multi-plane parallel reads and the current planes are load-balanced, have normal temperatures, and no resource limitations, then the parallel storage unit can be set as a plane. In this case, subsequent steps will split and merge requests at the plane level; chips and channels are preferred. If plane-level concurrency is unavailable (e.g., flash memory does not support multi-plane commands, or a plane is faulty / overloaded), then the priority is to use chips or channels as parallel storage units.

[0044] This step employs a dynamic parallel cell selection mechanism, enabling the memory to adaptively adjust the granularity of parallel reads based on hardware capabilities and real-time status. On one hand, prioritizing the use of planar parallel storage cells maximizes the utilization of internal flash memory parallelism, achieving optimal read performance. On the other hand, when planar concurrency is limited, it can flexibly degrade to chip-level or channel-level concurrency, ensuring continuous and stable system operation. This mechanism balances performance optimization and reliability assurance, enhancing the adaptability of storage devices under complex operating conditions.

[0045] Reference Figure 2 , Figure 2 The diagram illustrates the second flowchart of the data reading method provided in this application embodiment. Content identical or similar to the above description in the following text will not be repeated hereafter. The step of splitting the data read instruction into at least one read request based on the continuity of the target physical address corresponding to the data read instruction and the corresponding parallel storage unit includes steps S111 to S113: Step S111: If the target physical addresses belong to the same parallel memory unit, determine the first continuity of the target physical addresses; Step S112, if the first continuity is discontinuous, based on the address discrete characteristics of the target physical address, the data read instruction is split into individual read requests; and / or, Step S113: If the first continuity is continuous, the data read instruction is treated as a read request.

[0046] It should be noted that in this embodiment, the memory controller converts the received data read instruction into a read request, and each read request satisfies the requirements of physical address contiguousness and belonging to a parallel memory unit to ensure that subsequent concurrent processes can proceed smoothly. Since the processing of each data read instruction is roughly the same, the following steps will use a single data read instruction as an example for explanation.

[0047] For example, for a data read instruction, if all logical addresses mapped to the target physical addresses of this data read instruction belong to the same parallel memory unit (such as a single Plane), then the continuity of the target physical addresses is further determined, i.e., the aforementioned first continuity. If there is at least one discontinuity in the target physical addresses, then the first continuity is determined to be discontinuous. Accordingly, based on the address discreteness characteristics of the target physical addresses, continuous address segments are merged into one read request, and discontinuous segments are split. Ultimately, the instruction is split into several read requests, ensuring that the physical addresses of each request are continuous and belong to the same parallel memory unit. For example, for an 8KB read instruction, the two 4KB physical addresses are (Plane1, Block10, Page0, offset0) and (Plane1, Block10, Page2, offset0), and the two page addresses are discontinuous (separated by Page1). Therefore, it is split into two 4KB read requests. Furthermore, if all addresses in the target physical address are numerically consecutive (this can include consecutive offsets within the same page and consecutive page numbers across pages), then the first continuity can be determined as contiguous. Accordingly, the entire data read instruction can be directly treated as a single read request, with a size equal to the instruction data length. For example, a 4KB data read instruction, on a single physical page, with contiguous addresses, can be directly treated as a 4KB read request.

[0048] Understandably, the above partitioning strategy ensures that the physical addresses within each read request are contiguous and belong to a single parallel storage unit, which is a prerequisite for efficient parallel access by the memory. Reference Figure 3 This is a schematic diagram of the first scenario according to an embodiment of this application. Figure 3As shown, data read instruction 0 is 4KB, and its physical address belongs to parallel memory cell 0; data read instruction 1 is 8KB, and its two consecutive 4KB physical cells both belong to parallel memory cell 1; data read instruction 2 is 4KB, belonging to parallel memory cell 2; and data read instruction 3 is 16KB, and its four consecutive 4KB physical cells all belong to parallel memory cell 3. Since the data pointed to by these four data read instructions are located in different parallel memory cells with contiguous addresses, the memory controller can generate four read requests for each of the four data read instructions. Simultaneously, these four read requests can be sent to parallel memory cells 0-3, achieving four-way concurrent reading, thus significantly improving the efficiency of read command processing. The storage medium is NAND flash memory, and parallel memory cells 0-3 correspond to different planes or dies within the storage medium.

[0049] Reference Figure 4 , Figure 4 The diagram illustrates the third process flow of the data reading method provided in this application embodiment. Content identical or similar to the above description in the subsequent description will not be repeated hereafter. The step of splitting the data read instruction into at least one read request based on the continuity of the target physical address corresponding to the data read instruction and the associated parallel storage unit further includes steps S121 to S124: Step S121: When the target physical address belongs to different parallel memory units, the data read instruction is split into sub-data read instructions according to the affiliation relationship between the target physical address and each parallel memory unit. Step S122: For any one of the sub-data read instructions, determine the second continuity of the physical address of the sub-target corresponding to the sub-data read instruction; Step S123, in the case where the second continuity is discontinuous, based on the address discrete characteristics of the sub-target physical address, the sub-data read instruction is split into individual read requests; and / or, Step S124: If the second continuity is continuous, treat the sub-data read instruction as a read request.

[0050] It should be noted that in practical applications, data migration occurs due to various mechanisms within the memory (such as garbage collection and wear averaging). Therefore, scenarios involving random mixed reads become more complex.

[0051] For example, if the target physical address corresponding to a data read instruction can span multiple parallel memory units (e.g., some data is in Plane0 and some is in Plane1), the data read instruction can be split according to the affiliation relationship between the target physical address corresponding to the data read instruction and each parallel memory unit. For instance, the parallel memory unit can be used as a boundary to split the data read instruction into several sub-data read instructions, ensuring that the sub-target physical address corresponding to any sub-data read instruction belongs to the same parallel memory unit.

[0052] For example, since the processing procedure for each sub-data read instruction is consistent, this embodiment will use one sub-data read instruction as an example for explanation. For any sub-data read instruction among all sub-data read instructions, the continuity of the corresponding sub-target physical address is determined by querying, that is, the aforementioned second continuity. Optionally, if the sub-target physical address of the sub-data read instruction is not continuous (i.e., the second continuity is not continuous), it can be further split into multiple read requests with continuous physical addresses according to the method in step S112. Optionally, if it is determined that the sub-target physical address of the sub-data read instruction is continuous (i.e., the second continuity is continuous), it can be known that the entire sub-instruction is directly treated as a single read request, and its size is equal to the sub-instruction data length.

[0053] For example, if the host issues a 12KB data read command, the target physical address mapping is as follows: the first 8KB is located in Plane0 (two 4KB units, non-contiguous physical addresses), and the last 4KB is located in Plane1 (one 4KB unit). This is first split into two sub-data read commands: sub-data read command A (8KB, belonging to Plane0) and sub-data read command B (4KB, belonging to Plane1). Sub-command A corresponds to non-contiguous target physical addresses; therefore, sub-data read command A can be further split into two 4KB read requests. Sub-data read command B corresponds to contiguous target physical addresses and can be directly used as a 4KB read request.

[0054] Understandably, the above-described splitting strategy can solve the parallelization problem of read requests across parallel memory cells. First, the data is split along the boundaries of the parallel memory cells, allowing each sub-data read instruction to independently utilize intra-cell sequential read optimization. Then, within each cell, it is split according to address contiguity, ensuring that the final request granularity adapts to the physical characteristics of the flash memory. This mechanism enables host read instructions of any size and distribution to be transformed into a concurrent-friendly set of requests, fundamentally eliminating the performance bottleneck of "only 4KB can be concurrently executed" in traditional solutions.

[0055] Reference Figure 5 , Figure 5The diagram illustrates the fourth flow of the data reading method provided in this application embodiment. Content identical or similar to the above description in the subsequent description will not be repeated hereafter. The steps of reading data in parallel through each parallel storage unit and the request queue of each parallel storage unit include steps S31 to S32: Step S31: Perform parallel read operations through each parallel storage unit and the request queue of each parallel storage unit to obtain a data unit set; For example, the memory controller sends read requests from each request queue to each parallel memory cell in parallel, and each parallel memory cell executes the read requests in parallel. The data cells read by all the parallel memory cells in this instance can form a data cell set.

[0056] In one feasible implementation, the step of obtaining a data unit set by performing parallel read operations through each parallel storage unit and the request queue of each parallel storage unit includes steps S311 to S312: Step S311: For any one of the parallel storage units, execute the read request of the current reading round in the request queue corresponding to the parallel storage unit to obtain the data unit, and remove the read request of the current reading round from the corresponding request queue. Step S312: A data unit set is formed based on the data units obtained from each parallel storage unit.

[0057] It should be noted that the process of reading data in each parallel storage unit is basically the same in each round of parallel read operation. Therefore, in this embodiment, one of the parallel storage units will be used as an example for explanation.

[0058] For example, for any one of the parallel storage units, the memory controller can retrieve the read request for the current read round from the request queue corresponding to that parallel storage unit and send it to that parallel storage unit for execution. Alternatively, the parallel storage unit can retrieve the read request for the current read round from its corresponding request queue and execute it. After executing the read request for the current read round, the parallel storage unit obtains a data unit. Simultaneously, the read request for the current read round is removed from the request queue corresponding to that parallel storage unit, thus updating the request queue. It can be understood that by executing the above steps in parallel, each parallel storage unit can complete one round of parallel reading, and the data units obtained in one round of parallel reading can form the aforementioned data unit set.

[0059] Step S32: Determine the target data read instruction for data reading completion based on the data unit set, and return the target data requested by the target data read instruction.

[0060] For example, the memory controller traverses the data cell set, locating the original data read instruction for each data cell. If all data requested by a data read instruction has been returned (i.e., all read requests split from that instruction have been completed), the instruction is marked as "data read complete," which is the aforementioned target data read instruction. All data read according to the target data read instruction is the target data, and the complete target data is submitted to the host and finally returned to the sender. For example, after a concurrent read operation, the data cell set includes a parallel storage cell Plane0 that returns 16KB of data. This data belongs to the only request split from data read instruction A. Therefore, instruction A belongs to the target data read instruction and is completed immediately, and the 16KB of data is returned to the host. Alternatively, data read instruction B is an 8KB read, split into two 4KB requests, which are completed by Plane1 and Plane2 in different rounds of concurrent reads. In the first round of concurrent reads, Plane1 returns a 4KB data unit, at which point the data read instruction B has not yet completed; in the second round of concurrent reads, Plane2 returns another 4KB data unit, at which point all the data from the data read instruction B has arrived, and the two 4KB units are merged into an 8KB unit and returned to the host.

[0061] It is understood that in this embodiment, the target data read instruction that has been read is selected through the above mechanism, and the target data of the target data read instruction is returned as a whole to ensure data consistency and integrity, so as to support the possible splitting steps involved in the conversion from instruction to request.

[0062] In one feasible implementation, a data read instruction is configured with a data buffer; The steps for determining the target data read instruction based on the data unit set include steps S321 to S323: Step S321: Store the data units in the data unit set in the corresponding data buffer area; It should be noted that, in this embodiment, the memory can be configured with a data buffer for each data read instruction, as shown in the example below. Figure 6 This diagram illustrates the configuration of the data buffer in this application. Data read instructions 0 to n are configured with data buffers 0 to n respectively. The data buffer can temporarily store the data units read.

[0063] In one feasible implementation, after the step of receiving the data read instruction, the method further includes step S101: Step S101: Configure a data buffer for the data read instruction based on the maximum read length of the data read instruction or the expected data length of the data read instruction. Optionally, the data buffer size can be fixed. That is, the data buffer can be configured based on the maximum read length of the data read instruction. For example, if the maximum read length of a data read instruction is 16KB, then the fixed size of the data buffer can be 16KB. The data buffer typically resides in RAM (Random Access Memory) or a dedicated data buffer within memory. It is understood that setting the data buffer size to a fixed length can further reduce memory management overhead.

[0064] Optionally, the data buffer size can be dynamically changed, i.e., configured according to the expected data length of the data read instruction. For example, the memory can receive a data read command sent by the host through a front-end interface, parse the data read command descriptor, and obtain the data length (i.e., the expected data length of the data read instruction). The memory controller can allocate a buffer in internal RAM or a dedicated cache pool according to the data length to temporarily store the data read based on the data read instruction. Optionally, the buffer size can be equal to the data length obtained from the instruction. The allocation strategy can employ a pre-allocated cache pool or dynamic allocation to avoid memory fragmentation. Simultaneously, a mapping relationship is established between the data read instruction ID and the buffer address. It should be noted that under the above data buffer configuration mechanism, when a data buffer is full, it can be considered the target buffer, and the target data read instruction can be determined. For example, if the host issues a 4KB read instruction, the memory controller can retrieve a 4KB data buffer from the cache pool and bind the buffer to the instruction ID. If the 4KB data buffer is full, the 4KB read instruction can be considered complete.

[0065] Understandably, by dynamically configuring the size of the buffer, ensuring that the buffer size strictly matches the instruction length, cache resources can be fully utilized. This also facilitates subsequent data integrity verification, allowing the determination of which data read instructions have been completed, thereby filtering out the target read instructions.

[0066] In one feasible implementation, the step of storing data units in the data unit set in the corresponding data buffer includes steps S3211 to S3212: Step S3211: For any data unit to be stored in the data unit set, determine the data read instruction to which the read request pointing to the data unit to be stored belongs. Step S3212: Store the data unit to be stored in the data buffer area corresponding to the data read instruction.

[0067] For example, for any data unit in the data unit set that needs to be stored in the data buffer (i.e., the data unit to be stored), the memory can determine the data read instruction to which the read request pointing to the data unit to be stored belongs, and then store the data unit to be stored in the data buffer configured for that data read instruction. Similarly, each data unit to be stored can be stored in the corresponding data buffer in the above manner. For example, the memory controller parses the data read instruction ID to which each data unit to be stored belongs from the data unit set. For example, the controller determines which read request the data unit to be stored was obtained by executing, and then determines which data read instruction the read request belongs to. Further, the data buffer pre-allocated for that data read instruction is found through the data read instruction ID, and then the data unit to be stored is stored in that data buffer.

[0068] Step S322: Determine the target cache area in each data cache area, wherein the data length of the data in the target cache area is consistent with the expected data length of the corresponding data read instruction in the target cache area; Step S323: Use the data read instruction corresponding to the target buffer as the target data read instruction after the data read is completed.

[0069] For example, after a set of data units read in a round of parallel processing is stored in the corresponding data buffer, the memory controller can check the data buffer corresponding to each data read instruction. If the total length of data currently written to a certain data buffer is equal to the expected length of the data for the corresponding data read instruction (i.e., the amount of data the data read instruction needs to read), then the buffer is marked as the target buffer. Accordingly, the data read instruction corresponding to the target buffer is the target data read instruction, and then it enters the subsequent data return process. For example, data read instruction X requests 4KB, and its data buffer size is 4KB. After a single concurrent read, Plane0 returns 4KB of data, which is written to the data buffer. At this time, the data length of the data buffer is 4KB, which is equal to the expected length, so data read instruction X is completed. As another example, data read instruction Y requests 8KB, which is split into two 4KB requests. Its data buffer size is 8KB. After the first concurrent read, Plane1 returns 4KB, which is written to offset 0 of the data buffer. At this time, the data length of the data buffer is 4KB, which is less than 8KB, so data read instruction Y is not completed. After the second concurrent read, Plane2 returns 4KB, writes to the data buffer offset by 4KB, and the data length in the data buffer becomes 8KB, which is equal to the expected length. The data read instruction Y is then completed.

[0070] It is understood that this embodiment implements data integrity detection at the instruction level for reading data, and accurately determines whether the instruction has been completed by measuring the length of the buffer data.

[0071] In one feasible implementation, the step of returning the target data requested by the target data read instruction includes steps S324 to S325: Step S324: Use the data in the target buffer as the target data requested by the target data read instruction; Step S325: Return the target data to the sender of the target data read instruction.

[0072] For example, the data in the target cache is considered the target data requested by the target data read instruction. The master controller of the storage area can encapsulate the pointer to the data cache and its data length into a completion response. This response is then reported to the host (i.e., the sender of the target data read instruction) through the corresponding interface protocol to complete the instruction. Furthermore, it should be noted that after returning the target data to the sender of the target data read instruction, the aforementioned target cache can be released, ensuring the cyclical use of cache space.

[0073] In one feasible implementation, after the step of returning the target data requested by the target data read instruction, the method includes step S40: Step S40: If the request queue of each parallel storage unit is not empty, return to the step of performing parallel read operations through each parallel storage unit and its request queue to obtain a data unit set, until the request queue of each parallel storage unit is empty.

[0074] For example, after a concurrent read operation and data return processing, the memory controller can check all unfinished data read instructions. If the request queue of each parallel memory unit is not empty, it means that at least one data read instruction still has unreturned data, that is, the data read instruction has requested data but has not yet returned, and this can be directly manifested as the instruction's buffer not being full, or the data length in the buffer corresponding to the instruction being less than the expected length. In this case, the next round of concurrent read operation is started, that is, step S31 is repeated. This loop continues until all pending instructions are completed or the queue is empty. For example, the memory processes data read instruction C (4KB) and data read instruction D (8KB, split into two 4KB) simultaneously. First round of concurrent read: Plane0 returns the data of data read instruction C, and Plane1 returns the first 4KB of data read instruction D. At this time, data read instruction C is completed, and data read instruction D is not completed. The firmware detects that data read instruction D still has one 4KB unread, and schedules the second round of concurrent read, Plane1 returns the second 4KB of data read instruction D, and data read instruction D is completed.

[0075] Understandably, this embodiment implements continuous pipelined operations. Through cyclic scheduling, it can continuously utilize the concurrent capabilities of memory to maximize throughput. Especially for scenarios involving long instruction splitting, it can ensure that each instruction is executed completely.

[0076] Reference Figure 7 , Figure 7 This diagram illustrates the fifth step of the data reading method provided in this application. Any content that is the same as or similar to the above description will be referred to above and will not be repeated hereafter. After the step of receiving the data read instruction, the method includes steps S01 to S03: Step S01: Determine the size of the data to be read pointed to by the data read instruction; Step S02, if the data size is greater than a preset size, perform the step of splitting the data read instruction into at least one read request based on the contiguousness of the target physical address corresponding to the data read instruction and the parallel storage unit to which it belongs; and / or, Step S03: If the data size is less than or equal to the preset size, the data read instruction is treated as a read request.

[0077] For example, after receiving a data read instruction, the memory can first determine the size of the data to be read, which is pointed to by the data read instruction. The data size can be in bytes, and the size of the data to be read can be directly parsed from the data read instruction descriptor.

[0078] For example, after determining the size of the data to be read, it can be compared with a preset size. If the size of the data to be read is larger than the preset size, it indicates that the data read instruction may involve multiple parallel storage units, and their corresponding target physical addresses may not be contiguous. Therefore, a step can be taken to split the data read instruction into at least one read request based on the contiguousness of the target physical address corresponding to the data read instruction and the parallel storage unit to which it belongs, so as to ensure that the read request meets the specific condition of "corresponding physical addresses are contiguous and belong to a parallel storage unit" and participates in parallel reading. Optionally, the above-mentioned preset size can be 4KB, which is consistent with the basic granularity of the internal physical mapping of the flash memory storage device (i.e., a physical unit). This value can be adjusted according to the flash physical page size or system design.

[0079] For example, if the size of the data to be read is less than or equal to a preset size, it means that the data read instruction itself already meets the specific condition mentioned above: "the corresponding physical addresses are contiguous and belong to a parallel memory unit." Therefore, the data read instruction can be directly treated as a read request. For example, if the data size does not exceed 4KB, there is no need to perform complex address contiguousness and parallel memory unit attribution judgments; the data read instruction can be directly regarded as a read request. This read request can then be added to the request queue of the corresponding parallel unit.

[0080] Understandably, the initial judgment step quickly distributes host read commands by setting a preset size threshold (4KB), avoiding indiscriminate address continuity lookup and splitting operations for all commands, thus saving processing resources. For the large number of small read requests of 4KB or less, they are processed directly as single requests, reducing firmware overhead; for requests larger than 4KB, fine-grained splitting is triggered, creating conditions for subsequent concurrent scheduling. This mechanism ensures high-performance concurrency while also considering the processing efficiency of data read commands.

[0081] The following is for reference. Figure 8 This is a schematic diagram of a memory 400 provided in an embodiment of this application. The memory 400 includes a main control chip 410 and a storage chip 420. The main control chip 410 and the storage chip 420 are electrically connected directly or indirectly to realize data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines.

[0082] The storage chip 420 stores a computer program that can be executed by the main control chip 410. The main control chip is used to read / write the data or computer program stored in the storage chip 420 and perform corresponding functions. For example, when the computer program stored in the storage chip 420 is executed by the main control chip 410, the data reading method disclosed in the above embodiments can be implemented.

[0083] It should be understood that, Figure 8 The structure shown is only a schematic diagram of the memory 400. The memory 400 may also include components such as memory 400. Figure 8 The more or fewer components shown, or having the same Figure 8 The different configurations shown. Figure 8 The components shown can be implemented using hardware, software, or a combination thereof.

[0084] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, which are used to execute the data reading method described in the above embodiments.

[0085] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0086] The aforementioned computer-readable storage medium may be contained within a memory or may exist independently without being assembled into a memory.

[0087] The aforementioned computer-readable storage medium carries one or more programs, which, when executed by the memory, cause the memory to: Upon receiving a data read instruction, based on the continuity of the target physical address corresponding to the data read instruction and the parallel storage unit to which it belongs, the data read instruction is split into at least one read request, wherein the physical addresses corresponding to a read request are continuous and belong to a parallel storage unit. Add the read request to the request queue under the corresponding parallel storage unit; Data is read in parallel through each parallel storage unit and the request queue of each parallel storage unit.

[0088] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0089] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0090] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0091] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described data reading method. This solves the technical problem that traditional data reading schemes struggle to achieve good performance in real-world mixed random read scenarios. Compared to the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the data reading method provided in the above embodiments, and will not be elaborated upon here.

[0092] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the data reading method described above.

[0093] The computer program product provided in this application can solve the technical problem that traditional data reading schemes are difficult to achieve good performance in practical mixed random read scenarios. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as those of the data reading method provided in the above embodiments, and will not be repeated here.

[0094] The above are only some embodiments of this application and do not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A data reading method, characterized in that, Applied to a memory, the memory includes parallel storage units, which are planes, flash memory wafers, channels, or chips in the memory. The data reading method includes: Receive a data read instruction in a mixed read scenario, and based on the continuity of the target physical address corresponding to the data read instruction and the parallel storage unit to which it belongs, split the data read instruction into at least one read request, wherein the physical address corresponding to one read request is continuous and belongs to one parallel storage unit. Add the read request to the request queue under the corresponding parallel storage unit; Data is read in parallel through each parallel storage unit and the request queue of each parallel storage unit; The step of splitting the data read instruction into at least one read request based on the continuity of the target physical address corresponding to the data read instruction and the parallel storage unit to which it belongs includes: When the target physical addresses belong to the same parallel memory unit, the first continuity of the target physical addresses is determined; When the first continuity is discontinuous, the data read instruction is split into each read request based on the address discrete characteristics of the target physical address.

2. The data reading method as described in claim 1, characterized in that, The step of splitting the data read instruction into at least one read request based on the continuity of the target physical address corresponding to the data read instruction and the parallel storage unit to which it belongs further includes: If the first continuity is continuous, the data read instruction is treated as a read request.

3. The data reading method as described in claim 1, characterized in that, The step of splitting the data read instruction into at least one read request based on the continuity of the target physical address corresponding to the data read instruction and the parallel storage unit to which it belongs further includes: When the target physical address belongs to different parallel storage units, the data read instruction is split into sub-data read instructions according to the affiliation relationship between the target physical address and each parallel storage unit; For any one of the sub-data read instructions, determine the second continuity of the sub-target physical address corresponding to the sub-data read instruction; When the second continuity is discontinuous, based on the address discrete characteristics of the sub-target physical address, the sub-data read instruction is split into each of the read requests; and / or, When the second continuity is continuous, the sub-data read instruction is treated as a read request.

4. The data reading method as described in claim 1, characterized in that, Before the step of splitting the data read instruction into at least one read request based on the contiguousness of the target physical address corresponding to the data read instruction and the parallel storage unit to which it belongs, the method further includes: Based on the device function and / or device status of the memory, parallel storage cells of the memory are selected, wherein the types of parallel storage cells include the plane of the memory, the chip of the memory, and the channel of the memory, and the plane has a higher selection priority than the chip and the channel.

5. The data reading method as described in claim 1, characterized in that, The step of reading data in parallel through each parallel storage unit and the request queue of each parallel storage unit includes: The data unit set is obtained by performing parallel read operations through each parallel storage unit and the request queue of each parallel storage unit; Based on the data unit set, determine the target data read instruction to complete the data reading, and return the target data requested by the target data read instruction.

6. The data reading method as described in claim 5, characterized in that, Each of the aforementioned data read instructions is configured with a data buffer; The step of determining the target data read instruction based on the data unit set after data reading is completed includes: The data units in the data unit set are stored in the corresponding data cache area; Determine the target cache area to store all the data, wherein the data length in the target cache area is consistent with the expected data length of the data read instruction corresponding to the target cache area; The data read instruction corresponding to the target buffer is used as the target data read instruction.

7. The data reading method as described in claim 6, characterized in that, After the step of receiving data read instructions in a mixed read scenario, the method further includes: Configure a data buffer for the data read instruction based on the maximum read length of the data read instruction or the expected data length of the data read instruction.

8. The data reading method as described in claim 6, characterized in that, The step of storing the data units in the data unit set in the corresponding data cache area includes: For any data unit to be stored in the data unit set, determine the data read instruction to which the read request pointing to the data unit to be stored belongs; The data unit to be stored is stored in the data cache area corresponding to the data read instruction.

9. The data reading method as described in claim 6, characterized in that, The step of returning the target data requested by the target data read instruction includes: The data in the target cache is used as the target data requested by the target data read instruction; The target data is returned to the sender of the target data read instruction.

10. The data reading method as described in claim 5, characterized in that, After the step of returning the target data requested by the target data read instruction, the method includes: If the request queues of each parallel storage unit are not empty, return to the step of performing parallel read operations through each parallel storage unit and its request queue to obtain a data unit set, until the request queues of each parallel storage unit are empty.

11. The data reading method as described in claim 5, characterized in that, The step of obtaining a data unit set by performing parallel read operations through each parallel storage unit and the request queue of each parallel storage unit includes: For any one of the parallel storage units, the data unit is obtained by executing the read request of the current read round in the request queue corresponding to the parallel storage unit, and the read request of the current read round is removed from the corresponding request queue. The data unit set is formed based on the data units obtained from each parallel storage unit.

12. The data reading method as described in claim 1, characterized in that, After the step of receiving data read instructions in a mixed read scenario, the method includes: Determine the size of the data to be read as pointed to by the data read instruction; If the data size is greater than a preset size, the step of splitting the data read instruction into at least one read request based on the contiguousness of the target physical address corresponding to the data read instruction and the parallel storage unit to which it belongs is executed; and / or, If the data size is less than or equal to the preset size, the data read instruction is treated as a read request.

13. A memory, characterized in that, The memory includes a main control chip and a storage chip. The storage chip stores a computer program. When the main control chip executes the computer program, it implements the data reading method as described in any one of claims 1-12.

14. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the steps of the data reading method as described in any one of claims 1-12.

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