Solid state disk id and hardware state synchronization method, controller, system and medium

Abstract

This invention relates to the field of solid-state drive (SSD) technology, specifically to a method, controller, system, and medium for synchronizing SSD ID and hardware status. The method includes the following steps: S1, before the system enters a hibernation state, the driver layer acquires and persistently stores the initial identification information of the NVMe device; S2, after the system wakes up from hibernation, it performs multiple rounds of identifier query operations on the NVMe device; S3, based on the results of the multiple rounds of queries and the initial identifier information, it calculates the identifier change rate. If the identifier change rate is lower than a first preset threshold, it is determined to be temporary interference, and the device link is maintained; if the identifier change rate is higher than the first preset threshold, it proceeds to step S4; S4, it acquires the real-time status parameters of the NVMe device's physical layer and verifies them. If the verification passes, the link is restored; if the verification fails, a reset operation is performed on the NVMe device. Compared with existing technologies, this method significantly reduces the misjudgment rate caused by instantaneous changes in the device ID through status analysis, cross-validation, and joint decision-making.

Description

Technical Field

[0001] This invention relates to the field of solid-state drive (SSD) technology, specifically to a method, controller, system, and medium for synchronizing SSD ID with hardware status. Background Technology

[0002] As the NVMe protocol becomes the mainstream standard for high-performance solid-state storage, the reliability issues of its device management are becoming increasingly prominent. A typical problem is that NVMe solid-state drives using controllers from Venustech, such as the MAP1202 and MAP1002, may experience unexpected changes in their device unique identifiers, such as the EUI64, after the system wakes up from hibernation S3 / S4 state.

[0003] The defects of the existing technology are mainly concentrated in the following interrelated aspects: 1. Root cause of hardware initialization anomalies: The hardware state machine of the Lianyun main controller in low power mode has design limitations, which makes it easy for various initialization anomalies to occur during wake-up, including: (a) incomplete reset of the status register, and some registers fail to be restored to the state before sleep; (b) clock domain synchronization misalignment between different functional modules, causing information reading timing disorder; (c) voltage spikes or fluctuations generated by the power management unit during state switching, affecting the stability of the storage unit; (d) critical cache contents are lost due to power failure during deep sleep and cannot be completely reconstructed after wake-up.

[0004] 2. Rigid Operating System Kernel Verification Logic: Currently, the Linux kernel's NVMe driver queries device identifiers via multiple interfaces such as NVMe_GetEUI64() and NVMe_GetSN when managing devices. When the identifier values ​​returned by these interfaces are inconsistent or do not match the pre-sleep records in the kernel cache, the kernel's default strategy is to determine that the physical device has been replaced or has suffered an unrecoverable hardware failure, thus taking the aggressive action of directly deleting the corresponding NVMe namespace. This "black and white" logic cannot distinguish between temporary ID disturbances caused by the aforementioned hardware transient anomalies and real, permanent device failures.

[0005] 3. Severe Impact on User Experience and System Stability: The direct consequence of the aforementioned "misjudgment-deletion" chain is that user devices experience unexpected disk failures after waking from hibernation, resulting in the interruption of all data access. Recovery from this failure typically requires manually restarting the entire operating system, which is unacceptable for servers and industrial control equipment requiring 24 / 7 continuous operation, severely damaging system availability, data service continuity, and user experience.

[0006] Therefore, there is an urgent need for a method and system that can intelligently distinguish between temporary device ID disturbances and real hardware failures, so as to avoid misjudgment-induced disk failures at the source. Summary of the Invention

[0007] To overcome the shortcomings of the prior art, this invention provides a method, controller, system, and medium for synchronizing solid-state drive ID and hardware status, solving the problem that the operating system misidentifies and triggers the device offline due to the instantaneous change of the device identifier ID during the system power state switching process of NVMe solid-state drives.

[0008] To achieve the above objectives, a method for synchronizing solid-state drive ID with hardware status is designed, including the following steps: S1, Pre-sleep recording: Before the system enters sleep mode, the driver layer obtains and persistently stores the initial identification information of the NVMe device; S2, Post-wake-up verification: After the system wakes up from the hibernation state, it performs multiple rounds of identifier query operations on the NVMe device; S3, Verification Result Analysis: Based on the results of multiple rounds of queries and the initial identifier information, calculate the identifier change rate. If the identifier change rate is lower than the first preset threshold, it is determined to be temporary interference, and the device link is maintained; if the identifier change rate is higher than the first preset threshold, proceed to step S4. S4, Fault Decision and Execution: Obtain the real-time status parameters of the NVMe device's physical layer and verify them. If the verification passes, restore the link; if the verification fails, perform a reset operation on the NVMe device.

[0009] In step S1, the initial identification information includes, but is not limited to, EUI64, serial number SN, and model MN. The target locations for storing the initial identifier information include: the persistent cache of the operating system kernel, and an ID anchoring unit located in the NVMe controller and powered by a backup power supply. The ID anchoring unit exposes its stored identifier information to the host through the I²C or system management bus interface.

[0010] In step S2, multiple rounds of ID queries are performed at short time intervals, with 3 to 8 rounds and time intervals of 5ms to 20ms. In step S3, the rate of change of the identifier between the query result and the baseline value in each round is calculated, and then the average rate of change is obtained.

[0011] In step S3, the method for calculating the rate of change of the identifier is as follows: S31, Preprocessing data: Converting the initial identifiers and the results of each round of queries into quantifiable sequences; S32, Calculate the difference: After preprocessing, the difference is obtained by measuring the string difference through edit distance or by calculating the numerical deviation through byte-by-byte difference. S33, Calculate the rate of change of identifiers: Single-round rate of change = Difference / Total number of bits in the benchmark value; The first preset threshold is adaptively adjusted based on at least one of the following: NVMe device operating temperature, cumulative power-on time, or the baseline noise level of the physical layer.

[0012] In step S3, when it is determined to be temporary interference, the method further includes: starting a security protection window, suspending the initiation of new input / output commands to the NVMe device during the security protection window period, and monitoring the training status of the PCIe link.

[0013] In step S4, the specific method for obtaining the real-time status parameters of the NVMe device physical layer includes: reading the PHY chip register through memory-mapped I / O to obtain the bit error rate, power supply voltage fluctuation value, and signal integrity index.

[0014] In step S4, the verification is performed by combining the software ID change pattern with the hardware physical layer state: If the identifier change rate is less than or equal to the first preset threshold and the physical layer is in good condition, it is determined to be a benign transient interference, the link is automatically restored, and the device continues to work normally. If the identifier change rate is greater than the first preset threshold and the physical layer state is abnormal, it is determined to be a potential real hardware failure, triggering the controlled device reset process.

[0015] To achieve the above objectives, a solid-state drive controller is designed to execute the above methods, comprising: The main control module is used to perform flash memory conversion layer operations; The ID anchoring unit is connected to the main control module and is equipped with a backup power interface to maintain device identifier information during host hibernation. The PHY module integrates a status monitoring circuit and is used to output the status parameters of the physical layer link.

[0016] To achieve the above objectives, a computer storage system is designed, comprising: The aforementioned solid-state drive controller; The host computer runs an operating system, and the NVMe driver contained in the operating system is configured to perform the above method.

[0017] To achieve the above objectives, a computer-readable storage medium is designed, on which a computer program is stored, which, when executed by a processor, can implement the above methods.

[0018] Compared with existing technologies, this invention significantly reduces the false positive rate caused by instantaneous changes in device ID through state analysis, cross-validation, and joint decision-making, and has the following beneficial effects: 1. Significantly reduced false alarm rate: Through multiple rounds of software sampling and dual verification of hardware status, the false alarm rate of equipment offline caused by transient interference can be reduced by more than 90%.

[0019] 2. Significantly improved system availability: Unnecessary system restarts are avoided, improving the continuity of storage services by over 95%, which is especially beneficial for mission-critical servers.

[0020] 3. Cost savings in operation and maintenance: Reduces on-site maintenance support due to "false failures", shortens the mean time to repair (MTTR) to the second level, and is estimated to save 70% in operation and maintenance costs.

[0021] 4. Broad compatibility: The solution is not only designed for Lianyun controllers, but can also be adapted to other NVMe controllers with similar sleep-wake consistency issues, thus enhancing the overall system compatibility. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the process of the present invention.

[0023] Figure 2 This is a schematic diagram of the architecture of the present invention. Detailed Implementation

[0024] The present invention will now be further described with reference to the accompanying drawings.

[0025] like Figure 1 As shown, the first embodiment of this application provides a method for synchronizing a solid-state drive ID with its hardware status, including the following steps: S1, Pre-sleep recording: Before the system enters sleep mode, the driver layer obtains and persistently stores the initial identification information of the NVMe device as a benchmark for subsequent comparisons; S2, Post-wake-up verification: After the system wakes up from the hibernation state, it performs multiple rounds of identifier query operations on the NVMe device; S3, Verification Result Analysis: Based on the results of multiple rounds of queries and the initial identifier information, calculate the identifier change rate. If the identifier change rate is lower than the first preset threshold, it is determined to be temporary interference, and the device link is maintained; if the identifier change rate is higher than the first preset threshold, proceed to step S4. S4, Fault Decision and Execution: Obtain the real-time status parameters of the NVMe device's physical layer and verify them. If the verification passes, restore the link; if the verification fails, perform a reset operation on the NVMe device.

[0026] In step S1, the initial identification information includes, but is not limited to, EUI64, serial number SN, and model MN; the target locations for storing the initial identifier information include: the persistent cache of the operating system kernel, and the ID anchoring unit located in the NVMe controller and powered by a backup power supply. The ID anchoring unit exposes its stored identifier information to the host through the I²C or system management bus interface.

[0027] In step S2, multiple rounds of ID queries are performed at short time intervals, with 3 to 8 rounds and time intervals of 5ms to 20ms. In step S3, the rate of change of the identifier between the query results of each round and the baseline value is calculated, and then the average rate of change is obtained.

[0028] In step S3, the specific method for calculating the rate of change of the identifier is as follows: S31, Preprocessing data: Convert the initial identifier and the query results of each round into a quantifiable sequence, such as the SN string "NVMe12345678", convert it into a byte array according to ASCII code, or perform hash processing on the numeric identifier; S32, Calculate the difference: After preprocessing, the difference between strings is measured by edit distance or by calculating the numerical deviation by byte-by-byte difference to obtain the difference. For example, the difference between the SN string "NVMe12345678" and the SN string "NVMe12345679" is 1. S33, Calculate the identifier change rate: Single round change rate = difference / total number of bits in the baseline value. For example, the change rate of 1 difference in an 8-bit string is 1 / 8 = 0.125. The first preset threshold is adaptively adjusted based on at least one of the following: NVMe device operating temperature, cumulative power-on time, or the baseline noise level of the physical layer. Specifically, the first preset threshold is 3%-15%. A threshold below 3% is susceptible to noise interference, leading to false alarms, while a threshold above 15% may miss genuine hardware faults. Furthermore, it increases linearly with environmental degradation, such as increased operating temperature, aging, or increased ambient noise. When the device operating temperature increases, the cumulative power-on time increases, or the physical layer baseline noise increases, the system automatically increases the first preset threshold using a lookup table or a linear weighted formula to tolerate normal data fluctuations caused by aging or ambient noise and prevent false alarms. In this embodiment, the baseline threshold is 5%, and the threshold increases by 0.5% for every 10°C increase in temperature.

[0029] In step S3, when it is determined to be temporary interference, the method further includes: starting a security protection window, suspending the initiation of new input / output commands to the NVMe device during the security protection window period, and monitoring the training status of the PCIe link.

[0030] In step S4, the specific method for obtaining the real-time status parameters of the NVMe device's physical layer includes: reading the PHY chip registers through memory-mapped I / O to obtain the bit error rate, power supply voltage fluctuation value, and signal integrity index. These parameters reflect the true health status of the hardware.

[0031] In step S4, the software ID change pattern is verified in conjunction with the hardware physical layer state: If the identifier change rate is less than or equal to the first preset threshold and the physical layer condition is good, such as bit error rate BER < 10⁻¹² and voltage fluctuation < 5%, it is determined to be a benign transient interference, the link is automatically restored, and the device continues to work normally. If the identifier change rate is greater than the first preset threshold and the physical layer status is abnormal, such as bit error rate BER ≥ 10⁻¹² or voltage fluctuation ≥ 5%, it is determined to be a potential real hardware failure, triggering the controlled device reset process.

[0032] In practical use, the entire decision-making process is completed within a very short safety protection window, such as 10ms, and unnecessary bus transactions are suspended to avoid the spread of misoperation.

[0033] like Figure 2 As shown, a second aspect embodiment of this application provides an NVMe solid-state drive controller for performing the method of the first aspect embodiment, including: The main control module is used to perform flash memory conversion layer operations; The ID anchoring unit is connected to the main control module and is equipped with a backup power interface to maintain device identifier information during host hibernation. The PHY module integrates a status monitoring circuit and is used to output the status parameters of the physical layer link.

[0034] A third aspect of this application provides a computer storage system, comprising: The NVMe solid-state drive controller described in the second aspect embodiment; The host computer runs an operating system, and the NVMe driver included in the operating system is configured to perform the method of the first aspect embodiment.

[0035] A fourth aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, can implement the method of the first aspect embodiment.

[0036] This application introduces a multi-dimensional verification mechanism that integrates hardware and software. After system wake-up and before the kernel makes the final decision to delete the device, an intelligent diagnostic and recovery window is inserted, significantly reducing the false positive rate caused by instantaneous changes in the device ID. It is particularly suitable for NVMe SSDs using Maxio's specific controller chip and can be widely applied in scenarios with stringent storage stability requirements, such as servers, data centers, industrial embedded equipment, and high-end consumer laptops.

Claims

1. A method for synchronizing a solid state drive ID with a hardware state, the method comprising: Includes the following steps: ​ S1, Pre-sleep recording: Before the system enters sleep mode, the driver layer obtains and persistently stores the initial identifier information of the NVMe device as a baseline value; S2, Post-wake-up verification: After the system wakes up from the hibernation state, it performs multiple rounds of identifier query operations on the NVMe device; S3, Verification Result Analysis: Based on the results of multiple rounds of queries and the initial identifier information, calculate the identifier change rate. If the identifier change rate is lower than the first preset threshold, it is determined to be temporary interference, and the device link is maintained. If the rate of change of the identifier is higher than the first preset threshold, proceed to step S4; S4, Fault Decision and Execution: Obtain the real-time status parameters of the NVMe device's physical layer and verify them. If the verification passes, restore the link; if the verification fails, perform a reset operation on the NVMe device.

2. The method of claim 1, wherein: In step S1, the initial identifier information includes, but is not limited to, EUI64, serial number SN, and model MN; The target locations for storing initial identifier information include: persistent cache of the operating system kernel, and ID anchoring unit located within the NVMe controller and powered by backup power. The ID anchoring unit exposes its stored identifier information to the host via I²C or system management bus interface.

3. The method for synchronizing solid-state drive ID and hardware status according to claim 1, characterized in that: In step S2, multiple rounds of ID queries are performed at short time intervals, with 3 to 8 rounds and time intervals of 5ms to 20ms. In step S3, the rate of change of the identifier between the query result and the baseline value in each round is calculated, and then the average rate of change is obtained.

4. The method for synchronizing solid-state drive ID and hardware status according to claim 1, characterized in that: In step S3, the method for calculating the rate of change of the identifier is as follows: S31, Preprocessing data: Convert the initial identifiers and the results of each round of queries into quantifiable sequences; S32, Calculate the difference: After preprocessing, the difference is obtained by measuring the string difference through edit distance or by calculating the numerical deviation through byte-by-byte difference. S33, Calculate the rate of change of identifiers: Single-round rate of change = Difference / Total number of bits in the benchmark value; The first preset threshold is adaptively adjusted based on at least one of the NVMe device operating temperature, cumulative power-on time, or the baseline noise level of the physical layer.

5. The method for synchronizing solid-state drive ID and hardware status according to claim 1, characterized in that: In step S3, when it is determined to be temporary interference, the method further includes: starting a security protection window, suspending the initiation of new input / output commands to the NVMe device during the security protection window period, and monitoring the training status of the PCIe link.

6. The method for synchronizing solid-state drive ID and hardware status according to claim 1, characterized in that: In step S4, the specific method for obtaining the real-time status parameters of the NVMe device physical layer includes: reading the PHY chip register through memory-mapped I / O to obtain the bit error rate, power supply voltage fluctuation value, and signal integrity index.

7. The method for synchronizing solid-state drive ID and hardware status according to claim 1, characterized in that: In step S4, the verification is performed by combining the software ID change pattern with the hardware physical layer state: If the identifier change rate is less than or equal to the first preset threshold and the physical layer is in good condition, it is determined to be a benign transient interference, the link is automatically restored, and the device continues to work normally. If the identifier change rate is greater than the first preset threshold and the physical layer state is abnormal, it is determined to be a potential real hardware failure, triggering the controlled device reset process.

8. A solid-state drive controller for performing the method as described in any one of claims 1 to 7, characterized in that, include: The main control module is used to perform flash memory conversion layer operations; The ID anchoring unit is connected to the main control module and is equipped with a backup power interface to maintain device identifier information during host hibernation. The PHY module integrates a status monitoring circuit and is used to output the status parameters of the physical layer link. A decision state machine is used for state transition control.

9. A computer storage system, characterized in that, include: The solid-state drive controller as described in claim 8; The host computer runs an operating system, the NVMe driver of which is configured to perform the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 7.

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