晶圆级异构键合集成方法、存储介质及键合设备
By constructing digital models and using global reference markers, precise alignment and efficient bonding of wafer-level heterogeneous bonding integration were achieved, solving the problem of insufficient alignment accuracy in existing technologies and improving production efficiency and yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 天津中科晶禾电子科技有限责任公司
- Filing Date
- 2026-03-27
- Publication Date
- 2026-07-17
AI Technical Summary
Existing technologies lack efficient and precise wafer-level heterogeneous bonding integration methods, resulting in insufficient alignment accuracy between heterogeneous chips and carrier wafers, which affects the reliability and yield of electrical connections.
A digital model is constructed using layout design information based on the carrier wafer. Position deviations are acquired in real time through global reference marking and a visual recognition system to generate an actual coordinate mapping table. Position compensation is performed in conjunction with a motion controller to ensure accurate alignment and bonding between heterogeneous chips and the carrier wafer.
It significantly improves the efficiency and accuracy of wafer-level heterogeneous bonding integration, avoids the problem of error accumulation, improves production yield and reduces material loss.
Smart Images
Figure CN121960359B_ABST