A device threshold voltage distribution statistical method and device of an integrated circuit, an electronic equipment and a storage medium

Abstract

This invention relates to the field of integrated circuit design technology, and particularly to a method, apparatus, electronic device, and storage medium for statistical analysis of threshold voltage distribution in integrated circuit devices. The method includes: acquiring device structure information and instantiation information of each standard unit corresponding to a target circuit module; for each standard unit, calculating the number of fins contributed by it based on the information, and performing classification and statistics based on threshold voltage attributes to generate threshold voltage distribution data for the target circuit module. This application, by parsing and fusing fin-level device information from a process library with instantiation data of circuit modules, innovates the statistical benchmark for threshold voltage distribution from the traditional number of standard units to the number of fins. This accurately reflects the true physical proportion of devices with different threshold voltages in the circuit. The generated precise distribution data provides a reliable quantitative basis for the replacement and optimization of multiple threshold voltage devices, directly enhancing the effect and reliability of power consumption and performance synergistic optimization.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a method, apparatus, electronic device, and storage medium for statistical analysis of device threshold voltage distribution in integrated circuits. Background Technology

[0002] As semiconductor processes advance to the nanoscale, FinFETs have become the mainstream device architecture for realizing high-performance, low-power integrated circuits. In chip designs employing FinFET technology, multi-threshold voltage (Multi-Vth) technology is a key method for optimizing circuit performance and static power consumption. This technology integrates transistors with different threshold voltages on the same chip, using low-threshold voltage (LVT) devices in critical timing paths to improve speed and high-threshold voltage (HVT) devices in non-critical paths to reduce leakage current, thereby achieving the optimal balance between power consumption and performance at the system level.

[0003] To achieve the aforementioned balance during the chip physical design phase, the design flow typically involves multiple rounds of multi-threshold voltage device replacement and optimization based on timing margins. This process relies on accurate statistical analysis of the threshold voltage distribution of circuit modules to dynamically adjust optimization strategies. Currently, the industry commonly uses a statistical method based on the number of standard cell instantiations to evaluate the threshold voltage distribution of circuit modules. However, this method has inherent limitations.

[0004] For example, suppose a circuit module contains 100 standard cell instances, of which 60 are identified as low-threshold voltage cells and 40 as high-threshold voltage cells. Traditional methods would conclude that low-threshold voltage devices account for 60%. However, this conclusion deviates significantly from physical reality. This is because the number of transistors and their fin configurations vary greatly among different standard cells: a simple inverter contains only 2 transistors, while a complex arithmetic logic unit may contain hundreds of transistors; furthermore, in FinFET architectures, a high-drive transistor may contain 8 fins, while a conventional transistor contains only 2 fins. Traditional methods only count the number of cells, completely ignoring the differences in the number of transistors within a cell and the number of fins per transistor. This results in statistical results that fail to accurately reflect the true distribution of different threshold voltage devices within the circuit module, especially in complex cells containing a large number of transistors (such as SRAM) or cells with high drive intensity, where the error is particularly significant.

[0005] Therefore, there is a lack of statistical methods in the existing technology that can accurately reflect the true distribution characteristics of the threshold voltage of circuit modules under FinFET technology. Summary of the Invention

[0006] In view of this, the purpose of the present invention is to provide a method, apparatus, electronic device, and storage medium for statistical analysis of the threshold voltage distribution of integrated circuits.

[0007] In a first aspect, embodiments of the present invention provide a method for statistically analyzing the device threshold voltage distribution of an integrated circuit, the method comprising: Obtain the device structure information and instantiation information of each standard unit corresponding to the target circuit module; For each standard cell, the number of fins contributed by the standard cell to the target circuit module is calculated based on the number of fins in the instantiation information and device structure information. Based on the threshold voltage attribute in the device structure information, the number of contributing fins is classified and statistically analyzed according to the threshold voltage category to generate threshold voltage distribution data of the target circuit module.

[0008] In conjunction with the first aspect, the steps for obtaining the device structure information of each standard unit corresponding to the target circuit module include: Obtain the SPICE netlist files for each standard cell provided by the process library; For each standard cell's SPICE netlist file, the SPICE netlist file is parsed to extract the number of Fin FET devices contained in the standard cell, the number of fins corresponding to each Fin FET device, and their corresponding threshold voltage attributes.

[0009] In conjunction with the first aspect, the steps for obtaining the instantiation information of each standard unit in the target circuit module include: Obtain the design database file or netlist file of the target circuit module; Parse the database file or netlist file to identify the number of times each standard unit is instantiated in the target circuit module.

[0010] In conjunction with the first aspect, standard units include logic standard units and static random access memory units.

[0011] In conjunction with the first aspect, the steps for calculating the number of fins contributed by the standard unit in the target circuit module include: For each Fin FET device in the standard cell, the product of the number of fins of the Fin FET device and the number of instantiations is calculated to obtain the number of fins contributed by the Fin FET device to the standard cell. The total number of fins contributed by all Fin FET devices in the standard cell is calculated to obtain the total number of fins contributed by the standard cell in the target circuit module.

[0012] In conjunction with the first aspect, the steps of classifying and statistically analyzing the number of contributing fins according to threshold voltage categories to generate threshold voltage distribution data for the target circuit module include: Based on the threshold voltage attribute, each FinFET device is divided into different threshold voltage categories; For each threshold voltage category, the total number of contributing fins corresponding to all Fin FET devices belonging to the threshold voltage category is accumulated to obtain the total number of fins corresponding to the threshold voltage category. Threshold voltage distribution data is generated based on the total number of fins corresponding to each threshold voltage category.

[0013] In conjunction with the first aspect, the threshold voltage distribution data includes the percentage of fins corresponding to the threshold voltage category, distribution maps, or statistical reports.

[0014] Secondly, this application provides a device for statistically analyzing the threshold voltage distribution of an integrated circuit, the device comprising: The acquisition module is used to acquire the device structure information and instantiation information of each standard unit corresponding to the target circuit module; The calculation module is used to calculate the number of fins contributed by each standard cell in the target circuit module based on the number of fins in the instantiation information and device structure information. The classification module is used to classify and statistically analyze the number of contributing fins according to the threshold voltage attribute in the device structure information, and generate threshold voltage distribution data of the target circuit module.

[0015] Thirdly, this application provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor runs the computer program to cause the electronic device to perform the above-described method.

[0016] Fourthly, this application provides a readable storage medium storing computer program instructions, which are read and executed by a processor to perform the above-described method.

[0017] The embodiments of the present invention bring the following beneficial effects: The device, apparatus, electronic device, and storage medium for statistical analysis of device threshold voltage distribution of integrated circuits provided in this application include: obtaining device structure information and instantiation information of each standard unit corresponding to the target circuit module; for each standard unit, calculating the number of fins contributed by the standard unit in the target circuit module based on the number of fins in the instantiation information and device structure information; and classifying and statistically analyzing the number of contributed fins according to the threshold voltage category based on the threshold voltage attribute in the device structure information to generate threshold voltage distribution data of the target circuit module.

[0018] This application obtains the fin-level device structure and instantiation information of the standard units corresponding to the target circuit module, calculates the number of fins contributed by each standard unit, and performs classification and statistics based on threshold voltage attributes to generate accurate threshold voltage distribution data. This application innovates the statistical benchmark from the number of standard units to the number of fins, which can accurately reflect the true physical proportion of devices with different threshold voltages in the circuit, providing a reliable quantitative basis for multi-threshold voltage optimization and significantly improving the effect and reliability of chip power consumption and performance co-optimization.

[0019] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained in accordance with the structures particularly pointed out in the description, claims and drawings.

[0020] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0021] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 A flowchart illustrating the method for statistical analysis of device threshold voltage distribution in integrated circuits provided in an embodiment of the present invention; Figure 2 A schematic diagram of a device threshold voltage distribution statistical device for integrated circuits provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the electronic device structure provided in an embodiment of the present invention.

[0023] Figure label: 10 - Acquisition module, 20 - Calculation module, 30 - Classification module; 130 - Processor, 131 - Memory, 132 - Bus, 133 - Communication interface. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] To facilitate understanding of this embodiment, the technical terms used in this application will be briefly introduced below.

[0026] Fin FET (Fin Field-Effect Transistor) is the mainstream transistor structure in current advanced semiconductor process nodes (such as 7nm and 5nm). Its core feature that distinguishes it from traditional planar transistors is that the current conduction channel is one or more silicon "fins" that protrude vertically from the substrate, and the gate is wrapped around the fins on three sides, thereby achieving more effective electrostatic control of the channel.

[0027] Fin count refers to the number of vertical silicon "fins" contained in a Fin FET device. In physical design, a transistor can be composed of one, two, or more fins connected in parallel. The number of fins directly determines the effective channel width of the device, which in turn affects its conduction current, speed, and static leakage current.

[0028] After introducing the technical terms used in this application, the application scenarios and design concepts of the embodiments of this application will be briefly described below.

[0029] Existing threshold voltage distribution statistical methods are based only on the number of standard cells and do not consider the differences in the number of transistors within a cell or the number of FinFET fins, resulting in severely distorted statistical results and failing to provide accurate data support for circuit optimization.

[0030] Based on this, embodiments of this application provide a method, apparatus, electronic device, and storage medium for statistically analyzing the threshold voltage distribution of integrated circuits. Using fins as the basic statistical unit, it achieves accurate quantification of threshold voltage distribution and avoids statistical distortion caused by differences in unit structure. Example

[0031] This application provides a statistical method for the distribution of device threshold voltages in integrated circuits, combined with... Figure 1 As shown, the method includes: S110, obtain the device structure information and instantiation information of each standard unit corresponding to the target circuit module.

[0032] S120: For each standard cell, calculate the number of fins contributed by the standard cell to the target circuit module based on the number of fins in the instantiation information and device structure information.

[0033] S130: Based on the threshold voltage attribute in the device structure information, the number of contributing fins is classified and statistically analyzed according to the threshold voltage category to generate threshold voltage distribution data of the target circuit module.

[0034] This application obtains the fin-level device structure and instantiation information of the standard units corresponding to the target circuit module, calculates the number of fins contributed by each standard unit, and performs classification and statistics based on threshold voltage attributes to generate accurate threshold voltage distribution data. This application innovates the statistical benchmark from the number of standard units to the number of fins, which can accurately reflect the true physical proportion of devices with different threshold voltages in the circuit, providing a reliable quantitative basis for multi-threshold voltage optimization and significantly improving the effect and reliability of chip power consumption and performance co-optimization.

[0035] In conjunction with the first aspect, step S110 involves obtaining the device structure information of each standard unit corresponding to the target circuit module, including: S111, obtain the SPICE netlist files of each standard cell provided by the process library.

[0036] The technology library is a database containing complete physical and electrical descriptions of all available standard cells (such as logic gates, flip-flops, SRAM modules, etc.). Among them, the SPICE (Simulation Program with Integrated Circuit Emphasis) netlist file is a text file describing the internal circuit connections, device types, and precise process parameters of the standard cell.

[0037] Performing step S111 means systematically reading the SPICE netlist files of all relevant standard cells from the process library, preparing the raw data source for subsequent deep analysis.

[0038] S112, for each standard cell's SPICE netlist file, parse the SPICE netlist file and extract the number of Fin FET devices contained in the standard cell, the number of fins corresponding to each Fin FET device, and their corresponding threshold voltage attributes.

[0039] This step aims to decode the key physical features required for this method from the original netlist description. The parsing process involves identifying device declaration statements, connectivity relationships, and device model parameters within the netlist. Through this parsing, we can: Extract the number of Fin FET devices: Identify and count how many independent Fin FET transistors (i.e. Fin FET devices) are contained within the standard cell.

[0040] Fin number extraction: For each identified Fin FET device, read its key fin number attribute from its device model parameters or size definition.

[0041] Extract threshold voltage attributes: Determine the threshold voltage type (e.g., LVT, RVT, HVT) of each FinFET device by associating it with the process model (e.g., model name) or directly from the device's parameter card.

[0042] By executing steps S111 and S112 in sequence, the conversion from the process library file to structured device feature data is completed, ensuring high accuracy of the statistical module input.

[0043] In conjunction with the first aspect, step S110, which involves obtaining the instantiation information of each standard unit in the target circuit module, includes: S113, obtain the design database file or netlist file of the target circuit module.

[0044] Understandably, after the chip physical design phase is completed, two core files are typically generated: one is a design database file (such as a DEF file), which records in detail the module's placement and routing, the physical coordinates of all standard cell instances, and their attributes; the other is a netlist file (gate-level or transistor-level), which describes the module's logical structure and the connections between cells in text form. Executing step S113 means reading this type of final or intermediate design data for the target circuit module, providing an authoritative data source for statistical analysis of the target circuit module's internal structure.

[0045] S114, parse the database file or netlist file to identify the number of times each standard unit is instantiated in the target circuit module.

[0046] Step S114 involves a deep analysis of the design database file or netlist file. Its core objective is to quantify the frequency of use of each standard cell within the module. The analysis systematically scans the cell instantiation statements or records according to the file format. By identifying the standard cell names or identifiers referenced by each instance and categorizing and counting all identical references, the instantiation frequency of each standard cell in the target circuit module is accurately determined. For example, the analysis results might show that cell "INVX1" was called 120 times, while cell "NAND2X2" was called 45 times.

[0047] In conjunction with the first aspect, standard units include logic standard units and static random access memory units.

[0048] In this embodiment, the standard unit includes logic standard units (such as inverters, NAND gates, flip-flops, etc., circuit modules that implement basic logic and timing functions) and static random access memory units (i.e., basic storage units such as 6T / 8T that constitute a cache).

[0049] Logic standard units refer to units that implement basic logic operations, timing control, or interface functions, such as inverters (INV), NAND gates (NOR), flip-flops (DFF), buffers (BUF), selectors (MUX), etc. They are relatively regular, have a small number of transistors (ranging from 2 to dozens), and are usually arranged in a symmetrical or regular array.

[0050] Static random access memory (SRAM) units refer to the basic memory units used to form caches or on-chip memory. Examples include 6TB SRAM (the most common type, containing 6 transistors) and 8TB SRAM.

[0051] Traditionally, in statistics based on the number of standard cells, an SRAM macromodule containing millions of memory bits may only be considered one or a few "instances." This completely masks the existence of its massive number of transistors (e.g., a 1MB SRAM contains approximately 60 million transistors), leading to a complete distortion of its threshold voltage distribution statistics, with errors reaching several orders of magnitude. This application, however, treats SRAM cells as a special category of standard cells, parsing the SPICE netlist to extract the fin count and threshold voltage attributes of each transistor. This allows the transistor resources, which account for the majority of chip area and power consumption in the SRAM macromodule, to be fairly and accurately included in the fin-based global statistics.

[0052] SRAM cells and logic cells differ significantly in circuit structure, layout, and electrical behavior. This limitation indicates that the method of this invention does not depend on the simplicity or uniformity of the cell structure. As long as a standard SPICE netlist description can be provided, regardless of whether the cell contains a simple two-transistor (inverter) structure or a complex 6-transistor interlocked structure (SRAM), this method can extract the required fin-level information through a unified parsing process. This demonstrates the method's strong technical inclusivity and robustness.

[0053] In conjunction with the first aspect, step S120 includes: S121, for each Fin FET device in the standard cell, the product of the number of fins of the Fin FET device and the number of instantiations is used to obtain the number of fins contributed by the Fin FET device to the standard cell.

[0054] S122: Accumulate the total number of fins contributed by all Fin FET devices in the standard cell to obtain the total number of fins contributed by the standard cell in the target circuit module.

[0055] Step S120 integrates device-level physical properties with design-level topology information to precisely quantify the weight of each standard cell in the overall composition of the target circuit module. Specifically: First, this is performed at the level of a single standard cell. It iterates through each Fin FET device resolved from the SPICE netlist for that standard cell. For each Fin FET device, a core operation is performed: the number of fins of that Fin FET device (from device structure information) is multiplied by the number of times that standard cell is instantiated in the entire target module (from instantiation information). The physical meaning of this product is clear: it represents the number of fins that the Fin FET device contributes to the entire target circuit module due to the reuse of its own standard cell. For example, a device with 2 fins, if its own cell is invoked 100 times, has a contribution of 200 fins. This step transforms the abstract instantiation count into a concrete, accumulative physical quantity (fin count).

[0056] Subsequently, after calculating the independent contributions of all Fin FET devices within the cell, step S122 performs a crucial aggregation. This involves summing and accumulating the fin counts contributed by each Fin FET device within the standard cell, as calculated in step S121. Specifically, this is expressed as:

[0057] in, The total number of fins for all Fin FET devices in the target circuit module is the calculation target for this step.

[0058] This represents the total number of different standard unit types involved in the target circuit module.

[0059] For the first The sum of the number of fins of all Fin FET devices within a single instance of a standard cell (this value is obtained by parsing and extracting from the SPICE netlist in the process library through steps S111-S112).

[0060] For the first The number of times the standard cell is instantiated in the target circuit module (this value is obtained by parsing and extracting from the design database or netlist in steps S113-S114).

[0061] The above formula macroscopically defines the calculation objective of step S120: to obtain the total number of fins in the circuit module through weighted summation. Its calculation logic corresponds to steps S121 and S122 as follows: For the A standard unit, the total number of fins contained in a single instance. The instantiation count is obtained by parsing the SPICE netlist in the process library (results from steps S111-S112). The results of steps S113-S114 are obtained by analyzing the circuit module design data.

[0062] Individual terms in the formula , calculates the first The contribution of the standard unit to the total fins of the entire module .

[0063] Finally, in step S122, all standard cell types are traversed, and the contribution of each type of standard cell is calculated. Accumulate, and you will get .

[0064] Understandably, this results in a certain number of fins. It is a core dataset that bridges the gap between previous and subsequent approaches: it concludes the evaluation of contribution weights for various standard units and accurately encapsulates the contribution weights of various units based on their physical composition. and design reusability The overall impact; at the same time, it also provides accurate and categorizable input data for the next step (S130) to perform global classification statistics across units according to the threshold voltage attribute.

[0065] Step S120 achieves a transformation of statistical dimensions by first decomposing (calculating by device) and then aggregating (accumulating by unit). It abandons the coarse approach of using a standard unit instance as the calculation unit in traditional methods. Instead, it assigns a precise, non-integer contribution weight (total number of fins) to each fin based on its actual physical composition (sum of fins) and actual design importance (instantiation count). This ensures that each physical fin in the target circuit module can be accurately included in the overall statistics through its corresponding device and unit, thus laying the computational foundation for generating a threshold voltage distribution that truly reflects the physical characteristics of the circuit.

[0066] In conjunction with the first aspect, step S130 includes: S131, based on the threshold voltage attribute, classify each FinFET device into different threshold voltage categories.

[0067] S132, for each threshold voltage category, accumulate the number of contributing fins corresponding to all Fin FET devices belonging to the threshold voltage category to obtain the total number of fins corresponding to the threshold voltage category.

[0068] S133, generate threshold voltage distribution data based on the total number of fins for each threshold voltage category.

[0069] The goal of step S130 is to globally categorize and statistically analyze the dispersed unit contribution values ​​calculated in previous steps according to their core electrical properties, thereby generating an intuitive and accurate circuit module-level threshold voltage distribution view. Specifically: First, based on the key parameter of the threshold voltage attribute extracted from the SPICE netlist in the process library, a clear category label is assigned to all involved FinFET devices (regardless of which standard cell they belong to). Understandably, these category labels are usually consistent with the process library definitions, such as Low Threshold Voltage (LVT), Standard Threshold Voltage (SVT or RVT), High Threshold Voltage (HVT), etc. This step logically establishes a clear classification framework, ensuring that each subsequent physical fin can be accurately assigned to its correct electrical category.

[0070] Next, within the framework of the threshold voltage categories established in the previous step, it performs a global data aggregation. For each threshold voltage category (such as all LVT devices), the system iterates through all standard cells, but only selects those Fin FET devices belonging to that category. Then, it sums up the "contributing fin count" (which has been precisely calculated in step S120, meaning the number of fins contributed to the entire module by the device due to the instantiation of its cell) corresponding to these selected devices. This summation result is the "total number of fins corresponding to that threshold voltage category". For example, by accumulating the fins contributed by all devices marked as HVT, the total number of high threshold voltage fins in the module is obtained.

[0071] Finally, the total number of fins for each threshold voltage category calculated by S132 is converted into "threshold voltage distribution data" that can be directly used by designers or automation tools.

[0072] Step S130, through a process of first classifying, then accumulating across cells, and finally formatting, transforms low-level physical contribution data into high-level design insights. Its technical effects are direct and significant: the distribution data it produces accurately reflects the physical resource weight (i.e., the proportion of total fins) occupied by devices with different threshold voltages within a circuit module. Compared to traditional statistics based on the number of cells, the data generated by this method is more directly and accurately correlated with physical characteristics of the circuit, such as leakage power consumption and driving capability. This precise distribution map enables design optimization tools to make more informed decisions, such as accurately locating and replacing low-threshold voltage cells that contribute a large number of fins to optimize power consumption, thereby ultimately achieving a precise balance between chip performance and power consumption.

[0073] This threshold voltage distribution data provides precise quantitative input for subsequent circuit optimization. In a specific application scenario, this data can be directly imported into chip electronic design automation (EDA) tools (such as power optimization modules). By parsing the distribution data, the optimization tool can accurately locate circuit paths or standard cell sets that "contribute excessive low threshold voltage (LVT) fins." Based on this, the tool can prioritize replacing LVT devices in these paths with high threshold voltage (HVT) devices, while meeting timing constraints. Since the distribution data is based on the number of fins rather than the number of cells, this optimization strategy ensures that the parts with the greatest impact on static power consumption are prioritized and accurately addressed, thereby efficiently achieving the best balance between circuit performance and power consumption, and avoiding under-optimization or over-design caused by data distortion in traditional methods.

[0074] In conjunction with the first aspect, the threshold voltage distribution data includes the percentage of fins corresponding to the threshold voltage category, distribution maps, or statistical reports.

[0075] The threshold voltage distribution data is the final output of the method of this invention. It accurately depicts the configuration of different threshold voltage resources in the target circuit module in a structured and visualized form. This data is not a single value, but a dataset containing multi-dimensional information, mainly manifested in the following three complementary forms, which together provide a comprehensive insight for circuit design and optimization: A. Fin Quantity Percentage for Threshold Voltage Categories: This data presents the weight distribution of various threshold voltage devices in the target circuit module in a relative proportion. It is important to emphasize that this quantity is not the number of standard cells in the traditional sense, but rather the equivalent quantity measured in fins. For example, the data can be expressed as "Low Threshold Voltage (LVT) devices account for 45%, High Threshold Voltage (HVT) devices account for 30%", but this percentage is calculated based on the total number of fins under each threshold voltage category. This percentage directly relates to the circuit's static power consumption and speed potential: a high LVT percentage usually means high potential module performance, but also greater static leakage current; a high HVT percentage is beneficial for reducing power consumption, but may limit speed. It provides designers with a first-hand quantitative indicator for evaluating the power-performance balance of the current design.

[0076] B. Threshold Voltage Distribution Map: This is a graphical and spatial representation of the aforementioned percentage data, designed to provide a more intuitive visual analysis tool. The map can take various forms, such as pie charts or bar charts, to visually display the number or percentage of fins in each threshold voltage category; distribution histograms can further show the device distribution within the same threshold voltage category across different fin number ranges. Heatmaps associated with circuit layout (if combined with layout information) can use color coding on the chip layout to show the tendency of threshold voltage attributes in different areas, helping to identify "high leakage areas" or "critical timing path concentration areas."

[0077] C. Statistical Reports: This is the most detailed and structured form of data, typically presented in tables or structured text files, which can be directly read by design automation tools or used for in-depth analysis. A complete statistical report may include, but is not limited to, the following fields: threshold voltage category (e.g., LVT, RVT, HVT), total number of fins in that category, percentage of fins in that category, list of major standard cells contributing to that category of fins and their contribution, and static power consumption contribution ratio estimated based on the total number of fins (which can be combined with process parameter models). Understandably, statistical reports not only provide a macroscopic distribution but also reveal microscopic components, enabling designers to trace the specific sources of power consumption or performance bottlenecks (e.g., discovering that a particular cell type contributes an unusually large number of LVT fins), thereby achieving a closed loop from global optimization to precise local adjustments.

[0078] The threshold voltage distribution data, presented in three formats—fin quantity percentage, graphs, and reports—transforms from overview to detail, and from intuitive to calculable, constructing a multi-layered, comprehensive circuit characteristic analysis system. It not only clarifies the distribution but also reveals its causes and impacts, thus providing a solid and accurate data foundation for subsequent multi-threshold voltage optimization, power consumption verification, and reliability assessment. This achieves a leap from rough estimation to precise design and optimization.

[0079] Secondly, this application provides a device for statistically analyzing the threshold voltage distribution of integrated circuits, combined with... Figure 2 As shown, the device includes: an acquisition module 10, a calculation module 20, and a classification module 30.

[0080] The acquisition module 10 is used to acquire the device structure information and instantiation information of each standard unit corresponding to the target circuit module.

[0081] The calculation module 20 is used to calculate the number of fins contributed by each standard cell in the target circuit module based on the number of fins in the instantiation information and device structure information.

[0082] The classification module 30 is used to classify and statistically analyze the number of contributing fins according to the threshold voltage category based on the threshold voltage attribute in the device structure information, and generate threshold voltage distribution data of the target circuit module.

[0083] Thirdly, embodiments of this application provide an electronic device, combined with Figure 3 As shown, the electronic device includes a memory 131 and a processor 130. The memory 131 stores a computer program, and the processor 130 runs the computer program to make the electronic device perform the above-described method.

[0084] Furthermore, combined Figure 3 The electronic device shown also includes a bus 132 and a communication interface 133, with the processor 130, the communication interface 133 and the memory 131 connected via the bus 132.

[0085] The memory 131 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device. Communication between this system network element and at least one other network element is achieved through at least one communication interface 133 (which can be wired or wireless), such as the Internet, wide area network, local area network, metropolitan area network, etc. The bus 132 may be an ISA bus, PCI bus, or EISA bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 3 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0086] Processor 130 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of processor 130 or by instructions in software form. Processor 130 may be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this invention. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this invention can be directly manifested as execution by a hardware decoding processor, or execution by a combination of hardware and software modules in the decoding processor. The software module can reside in a mature storage medium in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory 131, and processor 130 reads the information in memory 131 and, in conjunction with its hardware, completes the steps of the method described in the foregoing embodiments.

[0087] Fourthly, embodiments of this application provide a readable storage medium storing computer program instructions, which are read and executed by a processor to perform the above-described method.

[0088] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the system and apparatus described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0089] Furthermore, in the description of the embodiments of the present invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.

[0090] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0091] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0092] Finally, it should be noted that the above embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A statistical method for the distribution of device threshold voltage in an integrated circuit, characterized in that, The method includes: Obtain the device structure information and instantiation information of each standard unit corresponding to the target circuit module; For each of the standard units, the number of fins contributed by the standard unit in the target circuit module is calculated based on the number of fins in the instantiation information and the device structure information. Based on the threshold voltage attribute in the device structure information, the number of contributing fins is classified and statistically analyzed according to the threshold voltage category to generate threshold voltage distribution data of the target circuit module. The step of calculating the number of fins contributed by the standard unit in the target circuit module includes: For each Fin FET device in the standard cell, the product of the number of fins of the Fin FET device and the number of instantiations is calculated to obtain the number of fins contributed by the Fin FET device to the standard cell. The total number of fins contributed by all the Fin FET devices in the standard unit is calculated to obtain the total number of fins contributed by the standard unit in the target circuit module.

2. The method according to claim 1, characterized in that, The steps for obtaining the device structure information of each standard unit corresponding to the target circuit module include: Obtain the SPICE netlist files for each of the standard cells provided by the process library; For each standard cell's SPICE netlist file, the SPICE netlist file is parsed to extract the number of Fin FET devices contained in the standard cell, the number of fins corresponding to each Fin FET device, and their corresponding threshold voltage attributes.

3. The method according to claim 1, characterized in that, The steps for obtaining the instantiation information of each standard unit in the target circuit module include: Obtain the design database file or netlist file of the target circuit module; The database file or netlist file is parsed to identify the number of times each standard unit is instantiated in the target circuit module.

4. The method according to claim 2, characterized in that, The standard unit includes a logic standard unit and a static random access memory unit.

5. The method according to claim 1, characterized in that, The step of classifying and statistically analyzing the number of contributing fins according to threshold voltage categories to generate threshold voltage distribution data for the target circuit module includes: Based on the threshold voltage attribute, each FinFET device is classified into a different threshold voltage category; For each threshold voltage category, the total number of contributing fins corresponding to all Fin FET devices belonging to the threshold voltage category is accumulated to obtain the total number of fins corresponding to the threshold voltage category; The threshold voltage distribution data is generated based on the total number of fins corresponding to each threshold voltage category.

6. The method according to claim 1 or 5, characterized in that, The threshold voltage distribution data includes the percentage of fins corresponding to the threshold voltage category, distribution maps, or statistical reports.

7. A device for statistically analyzing the threshold voltage distribution of integrated circuits, characterized in that, The apparatus is configured to perform the method as described in any one of claims 1-6; the apparatus comprises: The acquisition module is used to acquire the device structure information and instantiation information of each standard unit corresponding to the target circuit module; A calculation module is used to calculate, for each of the standard units, the number of fins contributed by the standard unit in the target circuit module based on the instantiation information and the number of fins in the device structure information; The classification module is used to classify and statistically analyze the number of contributing fins according to the threshold voltage attribute in the device structure information, and generate threshold voltage distribution data of the target circuit module.

8. An electronic device, characterized in that, The electronic device includes a memory and a processor, the memory storing a computer program and the processor running the computer program to cause the electronic device to perform the method of any one of claims 1 to 6.

9. A storage medium, characterized in that, The storage medium stores computer program instructions, which, when read and executed by a processor, perform the method described in any one of claims 1 to 6.

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