A method and system for optimizing a cavity QFN package structure of a millimeter wave radio frequency chip

Abstract

The application discloses a kind of millimeter wave radio frequency chip cavity QFN packaging structure optimization method and system, including the following steps: step one: the core electrical parameter of millimeter wave radio frequency chip, heat dissipation parameter and the performance requirement of target application scene are collected, the basic structure parameter of cavity QFN packaging is determined, basic structure parameter includes the size of packaging body, pin number and arrangement pitch, cavity opening size range;Step two: based on millimeter wave frequency band signal transmission characteristics and electromagnetic coupling suppression demand;The beneficial effects of the application are: specially aiming at the high-frequency characteristics of millimeter wave radio frequency chip, optimize from cavity structure, heat dissipation layout, pin and bonding design multiple dimensions, solve the problem that prior art does not consider millimeter wave frequency band signal transmission characteristics;Through cavity electromagnetic shielding design, differential heat dissipation layout, impedance matching optimization, the radio frequency performance, heat dissipation performance and mechanical reliability of packaging structure are significantly improved, meet the application demand of 120GHz and above frequency band chip.

Description

Technical Field

[0001] This invention belongs to the field of chip packaging technology, specifically relating to a method and system for optimizing the cavity QFN packaging structure of millimeter-wave radio frequency chips. Background Technology

[0002] With the rapid development of technologies such as wireless communication and intelligent sensing, millimeter-wave radio frequency (RF) chips are finding increasingly wide applications, including low-orbit satellite communication, drone obstacle avoidance radar, and autonomous driving. Millimeter-wave RF chips offer advantages such as high operating frequency, large signal bandwidth, and high detection accuracy, but also place more stringent demands on packaging technology. Cavity QFN packaging, as a leadless packaging form, features small package size, good heat dissipation, and relatively low cost, and has been gradually applied to millimeter-wave RF chip packaging. However, the signal wavelength in the millimeter-wave band is extremely short and susceptible to electromagnetic interference, signal reflection, and transmission loss. Traditional cavity QFN packaging structures are unable to meet the high-frequency performance requirements of millimeter-wave RF chips.

[0003] In the field of chip packaging structure optimization, relevant research and patents already exist in the existing technology. For example, Chinese invention patent CN119720913A discloses a PCB packaging structure and its design method for improving the performance of large-size QFN chips. This patent selects an n-row n-column pad array, designs the pad array gap according to the PCB process requirements for line-pad spacing rules and power trace current carrying capacity, and designs the side length of a single pad based on the original thermal pad length of the chip package. Thus, the chip performance is improved through packaging structure layout optimization. This patent mainly targets the PCB packaging of large-size QFN chips, focusing on solving the problem of matching pad layout with power traces to improve the electrical and heat dissipation performance of the chip.

[0004] However, the aforementioned existing technologies have significant limitations when applied to millimeter-wave RF chip packaging: First, the core optimization of this patent focuses on the size and spacing design of the pad array, without considering the unique high-frequency signal transmission characteristics of the millimeter-wave band, such as electromagnetic coupling, signal reflection, and transmission loss, thus failing to meet the stringent signal integrity requirements of millimeter-wave RF chips. Second, this patent uses a traditional planar pad layout, without differentiated heat dissipation design based on the heat dissipation distribution characteristics of millimeter-wave RF chips, resulting in limited heat dissipation efficiency and difficulty in solving the problem of high heat accumulation in millimeter-wave RF chips operating at high frequencies. Third, this patent does not address the cavity structure optimization of cavity QFN packaging, while parameters such as cavity depth and inner wall contour have a crucial impact on the transmission path and electromagnetic shielding effect of millimeter-wave signals; traditional cavity structures are prone to signal leakage and electromagnetic interference. Finally, this patent does not incorporate RF impedance matching principles into pin arrangement and bonding wire design; impedance mismatch in the millimeter-wave band will severely affect signal transmission quality, leading to a decline in chip performance.

[0005] Furthermore, millimeter-wave radio frequency chips typically operate at frequencies of 60 GHz and above, even reaching near-terahertz bands such as 120 GHz and 140 GHz. As the frequency increases, signal transmission loss and electromagnetic coupling effects increase dramatically, while the chip's heat dissipation density also increases significantly. In existing packaging technologies, problems such as poor electromagnetic shielding of the packaging structure, unreasonable heat dissipation paths, and low impedance matching have become key bottlenecks restricting the performance of millimeter-wave radio frequency chips. Summary of the Invention

[0006] The purpose of this invention is to provide a method and system for optimizing the cavity QFN packaging structure of millimeter-wave radio frequency chips, thereby solving the problem that existing packaging technologies cannot meet the requirements of high frequency, low loss, and high heat dissipation for millimeter-wave radio frequency chips.

[0007] To achieve the above objectives, the present invention provides the following technical solution: a method for optimizing the cavity QFN packaging structure of a millimeter-wave radio frequency chip, comprising the following steps: Step 1: Collect the core electrical parameters, thermal power parameters and performance requirements of the target application scenario of the millimeter-wave RF chip, and determine the basic structural parameters of the cavity QFN package. The basic structural parameters include the package body size, number of pins and their spacing, and cavity opening size range. Step 2: Based on the signal transmission characteristics of the millimeter-wave band and the requirements for electromagnetic coupling suppression, optimize the depth of the cavity, the inner wall contour, and the relative position of the cavity and the active area of ​​the chip to form a cavity structure adapted to high-frequency signal transmission. Step 3: Based on the chip's thermal power distribution data, divide the chip into areas with concentrated heat and areas with low heat dissipation, and design differentiated heat dissipation pad layouts accordingly. The heat dissipation pads include main heat dissipation pads and auxiliary heat dissipation pads, and the main heat dissipation pads correspond precisely to the areas with concentrated heat on the chip. Step 4: Combining the principles of RF impedance matching and signal integrity requirements, optimize the pin arrangement, pin spacing, and the correspondence between pins and chip pads, and design the routing path and curvature of the bonding wires; Step 5: Construct a multiphysics simulation model to perform RF performance simulation, heat dissipation performance simulation, and mechanical reliability simulation on the optimized packaging structure, and obtain simulation data; Step Six: Compare the simulation data with the preset performance indicators. If the preset performance indicators are not met, return to any one or more of Steps Two to Four to adjust the parameters until the simulation data meets the preset performance indicators, and output the final cavity QFN packaging structure optimization scheme.

[0008] As a preferred technical solution of the present invention, in step one, the core electrical parameters include chip operating frequency, output power, input and output impedance, and signal bandwidth; the performance requirements of the target application scenario include anti-interference level, operating temperature range, and reliability level; in the process of determining the basic structural parameters, the packaging space limitations and assembly process requirements of the millimeter-wave RF chip need to be taken into account to ensure that the pin spacing meets the mounting accuracy requirements.

[0009] As a preferred technical solution of the present invention, in step two, the depth design of the cavity is determined based on the height of the active area of ​​the chip and the length of the signal transmission path, so that the difference between the cavity depth and the height of the active area of ​​the chip is within a preset range; the inner wall contour adopts a stepped structure or an arc transition structure, and an electromagnetic shielding coating is provided on the inner wall of the cavity, the material of which is silver, copper or nickel alloy.

[0010] As a preferred technical solution of the present invention, in step two, the relative position optimization between the cavity and the active area of ​​the chip includes: making the central axis of the cavity coincide with the central axis of the active area of ​​the chip, and making the size of the cavity in the projection direction of the active area of ​​the chip greater than a preset ratio of the size of the active area of ​​the chip in the corresponding direction, so as to ensure that the active area of ​​the chip is completely within the coverage of the cavity.

[0011] As a preferred technical solution of the present invention, in step three, the area of ​​the main heat dissipation pad is determined according to the area of ​​the heat concentration region of the chip and the heat power density, and the thickness of the main heat dissipation pad is greater than the thickness of the auxiliary heat dissipation pad; the auxiliary heat dissipation pads are evenly distributed around the main heat dissipation pads, and a heat conduction channel is set between the auxiliary heat dissipation pads and the main heat dissipation pads, and the heat conduction channel is made of a high thermal conductivity material.

[0012] As a preferred technical solution of the present invention, in step four, the pin arrangement order optimization adopts a method of arranging by signal type, and the RF signal pin, power supply pin, and ground pin are arranged in a concentrated manner, and an isolation gap is set between the RF signal pin and the power supply pin and the ground pin; the routing path of the bonding wire avoids the high-frequency signal interference area, and the curvature design of the bonding wire makes the characteristic impedance of the bonding wire match the input and output impedance of the chip.

[0013] As a preferred technical solution of the present invention, in step five, the radio frequency performance simulation includes insertion loss, return loss, and isolation simulation; the heat dissipation performance simulation includes steady-state temperature distribution and thermal response speed simulation; the mechanical reliability simulation includes structural stress and strain simulation under thermal cycling shock and vibration shock; the construction of the multiphysics simulation model requires importing the physical parameters of the packaging material, including dielectric constant, thermal conductivity, coefficient of thermal expansion, and elastic modulus.

[0014] As a preferred technical solution of the present invention, in step six, the preset performance indicators include: radio frequency performance indicators of insertion loss ≤0.5dB, return loss ≤-15dB, and isolation ≥25dB; heat dissipation performance indicators of chip operating temperature ≤85℃; and mechanical reliability indicators of no cracks in the packaging structure and no detachment of bonding wires after a preset number of thermal cycling shocks and vibration shocks.

[0015] This invention also discloses a cavity QFN packaging structure optimization system for millimeter-wave radio frequency chips, including... The parameter acquisition module is used to collect the core electrical parameters, thermal power consumption parameters and performance requirements of the target application scenario of the millimeter-wave RF chip, and to determine the basic structural parameters of the cavity QFN package. The cavity structure optimization module is used to optimize the depth, inner wall contour, and relative position of the cavity to the active area of ​​the chip based on the signal transmission characteristics and electromagnetic coupling suppression requirements of the millimeter-wave band. The heat dissipation layout optimization module is used to divide the chip into heat-concentrated areas and low-heat-dissipation areas based on the chip's heat power distribution data, and design differentiated heat dissipation pad layouts accordingly. The pin and bonding optimization module is used to optimize the pin arrangement, pin spacing, and bonding wire routing path and curvature by combining the principles of RF impedance matching and signal integrity requirements. The multiphysics simulation module is used to build multiphysics simulation models, simulate the RF performance, heat dissipation performance and mechanical reliability of the optimized packaging structure, and output simulation data. The iterative optimization module is used to compare the simulation data with the preset performance indicators. If the preset performance indicators are not met, it controls one or more of the cavity structure optimization module, heat dissipation layout optimization module, and pin and bonding optimization module to adjust the parameters until the simulation data meets the preset performance indicators. The solution output module is used to output the final cavity QFN package structure optimization solution.

[0016] Compared with the prior art, the beneficial effects of the present invention are: Specifically designed for the high-frequency characteristics of millimeter-wave RF chips, optimizations have been made in multiple dimensions, including cavity structure, heat dissipation layout, and pin and bonding design, solving the problem that existing technologies have not considered the signal transmission characteristics of the millimeter-wave band. Through cavity electromagnetic shielding design, differentiated heat dissipation layout, and impedance matching optimization, the RF performance, heat dissipation performance, and mechanical reliability of the packaging structure are significantly improved, meeting the application requirements of chips in the 120GHz and above frequency bands. By combining multiphysics simulation with iterative optimization, the optimal solution can be obtained without making physical samples multiple times, thus reducing R&D costs and time. The parameters can be flexibly adjusted and optimized according to the parameters of different millimeter-wave RF chips and application scenarios, making it suitable for chip packaging in multiple fields such as low-orbit satellite communication, drone obstacle avoidance, and intelligent driving. Attached Figure Description

[0017] Figure 1 This is a flowchart of the method for optimizing the cavity QFN packaging structure of millimeter-wave radio frequency chips according to the present invention; Figure 2 This is a schematic diagram of the optimized system configuration of the millimeter-wave radio frequency chip cavity QFN packaging structure according to the present invention; Figure 3 This is a top view of the cavity QFN package of the millimeter-wave radio frequency chip of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Please see Figures 1-3 This invention provides a method for optimizing the cavity QFN package structure of millimeter-wave radio frequency chips, comprising the following steps: Step 1: Collect the core electrical parameters, thermal power parameters, and performance requirements of the target application scenario for the millimeter-wave RF chip to determine the basic structural parameters of the cavity QFN package. These parameters include the package body size, number and spacing of pins, and cavity opening size range. Core electrical parameters include the chip's operating frequency, output power, input / output impedance, and signal bandwidth. Performance requirements for the target application scenario include interference immunity level, operating temperature range, and reliability level. During the determination of these basic structural parameters, the packaging space limitations and assembly process requirements of the millimeter-wave RF chip must be considered to ensure that the pin spacing meets the mounting accuracy requirements.

[0020] Step 2: Based on the signal transmission characteristics and electromagnetic coupling suppression requirements of the millimeter-wave band, optimize the depth, inner wall contour, and relative position of the cavity and the active area of ​​the chip to form a cavity structure suitable for high-frequency signal transmission. The depth design of the cavity is determined based on the height of the active area of ​​the chip and the signal transmission path length, ensuring that the difference between the cavity depth and the height of the active area of ​​the chip is within a preset reasonable range to reduce signal reflection. The inner wall contour adopts a stepped structure or an arc-shaped transition structure to avoid electromagnetic resonance caused by right-angle structures, and an electromagnetic shielding coating is set on the inner wall of the cavity. The material of the electromagnetic shielding coating is silver, copper, or nickel alloy. The optimization of the relative position of the cavity and the active area of ​​the chip includes: aligning the central axis of the cavity with the central axis of the active area of ​​the chip, and ensuring that the dimension of the cavity in the projection direction of the active area of ​​the chip is greater than a preset ratio of the corresponding dimension of the active area of ​​the chip, ensuring that the active area of ​​the chip is completely within the cavity coverage area and reducing edge signal leakage.

[0021] Step 3: Based on the chip's thermal power distribution data, divide the chip into areas with concentrated heat and areas with low heat dissipation. Design differentiated heat dissipation pad layouts accordingly. The heat dissipation pads include main heat dissipation pads and auxiliary heat dissipation pads, with the main heat dissipation pads precisely corresponding to the chip's concentrated heat areas. The area of ​​the main heat dissipation pad is determined based on the area of ​​the chip's concentrated heat areas and the heat dissipation density, and the thickness of the main heat dissipation pad is greater than the thickness of the auxiliary heat dissipation pads. The auxiliary heat dissipation pads are evenly distributed around the main heat dissipation pads, and a heat conduction channel is set between the auxiliary heat dissipation pads and the main heat dissipation pads. The heat conduction channel is made of a material with high thermal conductivity.

[0022] Step 4: Combining the principles of RF impedance matching and signal integrity requirements, optimize the pin arrangement, pin spacing, and the correspondence between pins and chip pads, and design the wiring path and curvature of the bonding wires. The pin arrangement optimization adopts a zoned arrangement according to signal type, with RF signal pins, power pins, and ground pins arranged in separate groups, and isolation spacing is set between RF signal pins and power and ground pins. The wiring path of the bonding wires avoids high-frequency signal interference areas, and the curvature design of the bonding wires ensures that the characteristic impedance of the bonding wires matches the input and output impedance of the chip. The length of the bonding wires is controlled within a preset range to reduce signal transmission loss.

[0023] Step 5: Construct a multiphysics simulation model to perform RF performance simulation, heat dissipation performance simulation, and mechanical reliability simulation on the optimized packaging structure, and obtain simulation data. RF performance simulation includes insertion loss, return loss, and isolation simulation; heat dissipation performance simulation includes steady-state temperature distribution and thermal response speed simulation; mechanical reliability simulation includes structural stress and strain simulation under thermal cycling shock and vibration shock. The construction of the multiphysics simulation model requires importing the physical parameters of the packaging material, including dielectric constant, thermal conductivity, coefficient of thermal expansion, and elastic modulus.

[0024] Step Six: Compare the simulation data with the preset performance indicators. If the preset performance indicators are not met, return to any one or more of steps two through four to adjust the parameters until the simulation data meets the preset performance indicators. Output the final cavity QFN packaging structure optimization scheme. The preset performance indicators include: RF performance indicators: insertion loss ≤ 0.5dB, return loss ≤ -15dB, isolation ≥ 25dB; heat dissipation performance indicators: chip operating temperature ≤ 85℃; mechanical reliability indicators: after a preset number of thermal cycling shocks and vibration shocks, the packaging structure has no cracks and the bonding wires have not fallen off.

[0025] This embodiment also includes step seven: based on the final packaging structure optimization scheme, fabricate a packaging sample, conduct physical testing on the packaging sample, and obtain physical test data. If the deviation between the physical test data and the simulation data exceeds a preset allowable range, return to step five to adjust the simulation model parameters and re-perform simulation and optimization until the physical test data meets the preset performance indicators. The specific methods for packaging sample fabrication and physical testing verification are as follows: Based on the final optimized packaging structure, high-precision molds are used to process the packaging base and cavity. High thermal conductivity and low dielectric loss packaging materials suitable for millimeter-wave RF chips are selected. The chip is precisely fixed to the preset position on the packaging base using automated chip mounting equipment. Gold bonding wires are used to complete the bonding connection between the chip pads and the packaging pins according to the optimized routing path and curvature. The packaging sample is made through processes such as vacuum molding, cutting and forming, and electromagnetic shielding coating sputtering to ensure that the sample structure is consistent with the optimized scheme. During the physical testing phase, a comprehensive testing environment was built, including an RF performance testing system, a high and low temperature heat dissipation test chamber, and a mechanical reliability testing platform. RF performance testing used a vector network analyzer to detect parameters such as insertion loss, return loss, and isolation. Heat dissipation performance testing used an infrared thermal imager to collect temperature data of the chip's core area under different workloads. Mechanical reliability testing simulated thermal cycling and vibration shock environments to observe the integrity of the packaging structure and the stability of the bonding wire connections. The physical test data is compared with the simulation data one by one, and the allowable deviation is preset. If the deviation of a certain parameter exceeds the range, return to step five, and combine the test data to correct the key parameters such as the material dielectric constant and thermal conductivity in the multiphysics simulation model. Then, the RF, heat dissipation and mechanical reliability simulations are performed again. Simultaneously, the cavity structure size, heat dissipation pad layout or bonding wire design and other related parameters are adjusted to generate a new optimization scheme and make a sample for testing again. The process is iterated until all physical test data meet the preset performance indicators.

[0026] A system for optimizing the cavity QFN packaging structure of millimeter-wave radio frequency chips, comprising: The parameter acquisition module is used to collect the core electrical parameters, thermal power consumption parameters and performance requirements of the target application scenario of the millimeter-wave RF chip, and to determine the basic structural parameters of the cavity QFN package. The cavity structure optimization module is used to optimize the depth, inner wall contour, and relative position of the cavity to the active area of ​​the chip based on the signal transmission characteristics and electromagnetic coupling suppression requirements of the millimeter-wave band. The heat dissipation layout optimization module is used to divide the chip into heat-concentrated areas and low-heat-dissipation areas based on the chip's heat power distribution data, and design differentiated heat dissipation pad layouts accordingly. The pin and bonding optimization module is used to optimize the pin arrangement, pin spacing, and bonding wire routing path and curvature by combining the principles of RF impedance matching and signal integrity requirements. The multiphysics simulation module is used to build multiphysics simulation models, simulate the RF performance, heat dissipation performance and mechanical reliability of the optimized packaging structure, and output simulation data. The iterative optimization module is used to compare the simulation data with the preset performance indicators. If the preset performance indicators are not met, it controls one or more of the cavity structure optimization module, heat dissipation layout optimization module, and pin and bonding optimization module to adjust the parameters until the simulation data meets the preset performance indicators. The solution output module is used to output the final cavity QFN package structure optimization solution.

[0027] To verify the effectiveness of the optimization method described in this invention, we designed and implemented the following comparative experiment. The experiment selected a millimeter-wave RF front-end chip with a working frequency of 120GHz as the test carrier, and used a traditional cavity QFN packaging structure (comparative example) and a cavity QFN packaging structure optimized by the method of this invention (experimental group) for packaging, simulation and actual measurement.

[0028] Experimental Design and Test Indicators Test subject: Comparative Example (Ref.): A cavity QFN package based on industry standard design rules, with a rectangular right angle cavity, evenly distributed heat dissipation pads, and pins arranged simply according to function; Experimental group (Opt.): The method of this invention was optimized, including a stepped cavity with a silver shielding coating, a differentiated main / auxiliary heat dissipation pad layout, and a pin design for bonding wires that is partitioned by signal type and optimized.

[0029] Performance metrics: RF performance: Insertion loss (S21), return loss (S11), and channel isolation (S31) were tested in the 110-130 GHz band.

[0030] Experimental Results and Data Analysis Channel isolation (S31) comparison (@120GHz) Comparative Example (Ref.) 19.5 Experimental group (Opt.) 32.0 Increase +12.5 Conclusion: By optimizing the pin partitioning and cavity shielding design, the channel isolation of the package at 120GHz was improved by approximately 12.5dB, effectively suppressing signal crosstalk.

[0031] Although embodiments of the invention have been shown and described (see the detailed description above), it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for optimizing the cavity QFN packaging structure of a millimeter-wave radio frequency chip, characterized in that: Includes the following steps: Step 1: Collect the core electrical parameters, thermal power parameters and performance requirements of the target application scenario of the millimeter-wave RF chip, and determine the basic structural parameters of the cavity QFN package. The basic structural parameters include the package body size, number of pins and their spacing, and cavity opening size range. Step 2: Based on the signal transmission characteristics of the millimeter-wave band and the requirements for electromagnetic coupling suppression, optimize the depth of the cavity, the inner wall contour, and the relative position of the cavity and the active area of ​​the chip to form a cavity structure adapted to high-frequency signal transmission. Step 3: Based on the chip's thermal power distribution data, divide the chip into areas with concentrated heat and areas with low heat dissipation, and design differentiated heat dissipation pad layouts accordingly. The heat dissipation pads include main heat dissipation pads and auxiliary heat dissipation pads, and the main heat dissipation pads correspond precisely to the areas with concentrated heat on the chip. Step 4: Combining the principles of RF impedance matching and signal integrity requirements, optimize the pin arrangement, pin spacing, and the correspondence between pins and chip pads, and design the routing path and curvature of the bonding wires; Step 5: Construct a multiphysics simulation model to perform RF performance simulation, heat dissipation performance simulation, and mechanical reliability simulation on the optimized packaging structure, and obtain simulation data; Step Six: Compare the simulation data with the preset performance indicators. If the preset performance indicators are not met, return to any one or more of Steps Two to Four to adjust the parameters until the simulation data meets the preset performance indicators, and output the final cavity QFN packaging structure optimization scheme.

2. The method for optimizing the cavity QFN packaging structure of a millimeter-wave radio frequency chip according to claim 1, characterized in that: In step one, the core electrical parameters include the chip's operating frequency, output power, input and output impedance, and signal bandwidth; the performance requirements of the target application scenario include anti-interference level, operating temperature range, and reliability level; in the process of determining the basic structural parameters, the packaging space limitations and assembly process requirements of the millimeter-wave RF chip need to be taken into account to ensure that the pin spacing meets the mounting accuracy requirements.

3. The method for optimizing the cavity QFN packaging structure of a millimeter-wave radio frequency chip according to claim 1, characterized in that: In step two, the depth of the cavity is designed based on the height of the active area of ​​the chip and the length of the signal transmission path, so that the difference between the cavity depth and the height of the active area of ​​the chip is within a preset range; the inner wall contour adopts a stepped structure or an arc transition structure, and an electromagnetic shielding coating is provided on the inner wall of the cavity. The material of the electromagnetic shielding coating is silver, copper or nickel alloy.

4. The method for optimizing the cavity QFN packaging structure of a millimeter-wave radio frequency chip according to claim 1, characterized in that: In step two, the relative position optimization between the cavity and the active area of ​​the chip includes: aligning the central axis of the cavity with the central axis of the active area of ​​the chip, and ensuring that the size of the cavity in the projection direction of the active area of ​​the chip is greater than a preset ratio of the size of the active area of ​​the chip in the corresponding direction, so as to ensure that the active area of ​​the chip is completely within the coverage area of ​​the cavity.

5. The method for optimizing the cavity QFN packaging structure of a millimeter-wave radio frequency chip according to claim 1, characterized in that: In step three, the area of ​​the main heat dissipation pad is determined based on the area of ​​the heat concentration region of the chip and the heat dissipation density. The thickness of the main heat dissipation pad is greater than the thickness of the auxiliary heat dissipation pad. The auxiliary heat dissipation pads are evenly distributed around the main heat dissipation pads, and a heat conduction channel is set between the auxiliary heat dissipation pads and the main heat dissipation pads. The heat conduction channel is made of a material with high thermal conductivity.

6. The method for optimizing the cavity QFN packaging structure of a millimeter-wave radio frequency chip according to claim 1, characterized in that: In step four, the pin arrangement order optimization adopts a partitioned arrangement method according to signal type, and the RF signal pins, power pins, and ground pins are arranged in a concentrated manner, and an isolation gap is set between the RF signal pins and the power pins and ground pins; the routing path of the bonding wire avoids the high-frequency signal interference area, and the curvature design of the bonding wire makes the characteristic impedance of the bonding wire match the input and output impedance of the chip.

7. The method for optimizing the cavity QFN packaging structure of a millimeter-wave radio frequency chip according to claim 1, characterized in that: In step five, the RF performance simulation includes insertion loss, return loss, and isolation simulation; the heat dissipation performance simulation includes steady-state temperature distribution and thermal response speed simulation; the mechanical reliability simulation includes structural stress and strain simulation under thermal cycling shock and vibration shock; the construction of the multiphysics simulation model requires importing the physical parameters of the packaging material, including dielectric constant, thermal conductivity, coefficient of thermal expansion, and elastic modulus.

8. The method for optimizing the cavity QFN packaging structure of a millimeter-wave radio frequency chip according to claim 1, characterized in that: In step six, the preset performance indicators include: radio frequency performance indicators of insertion loss ≤ 0.5dB, return loss ≤ -15dB, and isolation ≥ 25dB; heat dissipation performance indicators of chip operating temperature ≤ 85℃; and mechanical reliability indicators of no cracks in the packaging structure and no detachment of bonding wires after a preset number of thermal cycling and vibration shocks.

9. A cavity QFN packaging structure optimization system for millimeter-wave radio frequency chips, characterized in that: The method for optimizing the cavity QFN package structure of millimeter-wave radio frequency chips as described in any one of claims 1-8 includes: The parameter acquisition module is used to collect the core electrical parameters, thermal power consumption parameters and performance requirements of the target application scenario of the millimeter-wave RF chip, and to determine the basic structural parameters of the cavity QFN package. The cavity structure optimization module is used to optimize the depth, inner wall contour, and relative position of the cavity to the active area of ​​the chip based on the signal transmission characteristics and electromagnetic coupling suppression requirements of the millimeter-wave band. The heat dissipation layout optimization module is used to divide the chip into heat-concentrated areas and low-heat-dissipation areas based on the chip's heat power distribution data, and design differentiated heat dissipation pad layouts accordingly. The pin and bonding optimization module is used to optimize the pin arrangement, pin spacing, and bonding wire routing path and curvature by combining the principles of RF impedance matching and signal integrity requirements. The multiphysics simulation module is used to build multiphysics simulation models, simulate the RF performance, heat dissipation performance and mechanical reliability of the optimized packaging structure, and output simulation data. The iterative optimization module is used to compare the simulation data with the preset performance indicators. If the preset performance indicators are not met, it controls one or more of the cavity structure optimization module, heat dissipation layout optimization module, and pin and bonding optimization module to adjust the parameters until the simulation data meets the preset performance indicators. The solution output module is used to output the final cavity QFN package structure optimization solution.

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