Low latency ecc check system and method based on corelet interconnect controller

Abstract

The application provides a low-delay ECC check system and method based on a core particle interconnection interface controller. In the system, a sending end comprises an ECC check bit generation module, which is used for generating 10-bit ECC check codes for flit data of a data link layer based on a pre-generated specific generation matrix, and inserting the check codes into a flit format as a tail part. A receiving end comprises a main data path and an ECC check branch which are arranged in parallel. A selector selects data output from the first synchronous FIFO or data output from the ECC error detection and correction module according to a check state signal. The application reduces the number of check bit generation logic levels by optimizing the generation matrix, adopts a main path and an ECC branch parallel processing structure at the receiving end, and combines a unified bit width adaptation mechanism to realize single-cycle check generation and two-cycle error correction at a high frequency of 1.5 GHz, thereby significantly reducing the delay and hardware overhead.

Description

Technical Field

[0001] The present invention belongs to the technical field of chiplet interconnection interface control, and particularly relates to a low-latency ECC check system and method based on a chiplet interconnection interface controller. Background Art

[0002] It is specified in the chiplet interconnection interface specification that when the raw bit error rate of the physical layer satisfies 1e-27<BER<1e-15, the chiplet interconnection interface controller needs to support the function of ECC10 for multi-bit error detection and 1-bit error correction. Specifically, in the data link layer of the chiplet interconnection interface controller, flit (flow control unit: the basic data unit transmitted by the data link layer) is taken as the unit, and the flit format is shown in Figure 1 , the transmitting end inserts a 10-bit ECC check bit, and the receiving end implements ECC error detection and error correction.

[0003] Based on the above considerations, the existing ECC check systems have the following problems: (1) In high-speed scenarios (e.g., SMIC 12nm process, the chiplet interconnection interface controller operates at 1.5 GHz), it is difficult for the transmitting end to generate ECC check bits within 1 clock cycle, and it is difficult for the receiving end to complete ECC error detection and error correction within 1 clock cycle. In existing designs, the transmitting end requires more than 1 clock cycle to complete the generation of ECC check bits, and the receiving end requires more than 3 clock cycles to complete ECC error detection and error correction. In CPU systems with high requirements for Latency, high latency is unacceptable.

[0004] (2) Since the payload size in flit supports multiple types (16Byte, 32Byte, 48Byte, 60Byte), in conventional implementations, a set of ECC10 check bit generation logic and ECC10 error detection and correction logic are respectively allocated for different data link layers. Especially when implementing ECC10 error detection and correction at the receiving end, the decoder logic is huge, resulting in long development cycle, large verification workload, excessive cost and high power consumption. Summary of the Invention

[0005] The purpose of the present invention is to solve the problems of high latency and large area of the existing ECC check system for chiplet interconnection interface controller existing in the background art, and provide a low-latency ECC check system and method based on a chiplet interconnection interface controller.

[0006] The low-latency ECC verification system based on a chip interconnect interface controller of the present invention includes a transmitter and a receiver. The transmitter includes an ECC check bit generation module, used to generate a 10-bit ECC check code for the data link layer flit data based on a pre-generated specific generation matrix, and insert the check code as a tail part into the flit format; the receiver includes a main data path and an ECC verification branch configured in parallel, wherein: the main data path includes a first synchronization FIFO, used to directly buffer the received flit data; the ECC verification branch includes an ECC error detection and correction module, used to perform parallel error detection and correction on the received flit data, and output a verification status signal and error-corrected data; a selector, which selects to output the data of the first synchronization FIFO or the error-corrected data of the ECC error detection and correction module according to the verification status signal.

[0007] Furthermore, preferably, in the low-latency ECC verification system based on the chip interconnect interface controller described in this invention, the specific generation matrix is ​​a binary matrix with 10 rows × 495 columns, satisfying the following conditions: each column in the matrix is ​​distinct and there are no columns with all zeros; each column contains an odd number of 1s; the total number of 1s in each row is 241 or 242, and the number of 1s in each row is evenly distributed.

[0008] Furthermore, preferably, in the low-latency ECC verification system based on the chip interconnect interface controller described in this invention, the ECC check bit generation module is configured to: for valid data with an input bit width of 485 bits, perform an XOR operation on the corresponding data bits according to the column position of 1 in each row of the specific generation matrix to generate a 10-bit ECC check code; wherein, the maximum number of XOR logic levels does not exceed 8 levels, so that the timing converges within a single clock cycle at a clock frequency of 1.5 GHz.

[0009] Furthermore, preferably, in the low-latency ECC verification system based on the chip interconnect interface controller described in this invention, the ECC error detection and correction module includes: a check code generation unit, which uses the same specific generation matrix as the transmitting end to perform XOR calculation on 495 bits of received data including check bits to generate a 10-bit check result; a decoder unit, which generates 485 mask signals and check status signals in parallel according to the check result; and an error correction unit, which uses the mask signals to correct erroneous bits in the received data.

[0010] Furthermore, preferably, in the low-latency ECC verification system based on the chip interconnect interface controller described in this invention, the decoder unit includes: 485 parallel comparators that compare the verification result with a predefined error mode constant to generate a mask control signal; and a status decision circuit that generates a 2-bit verification status signal based on the comparison result to indicate no error, 1-bit error corrected, or multiple-bit uncorrectable error.

[0011] Furthermore, preferably, in the low-latency ECC verification system based on the chip interconnect interface controller described in this invention, the total processing delay of the ECC verification branch does not exceed 2 clock cycles and is less than the readout delay of the first synchronous FIFO in the main data path.

[0012] Furthermore, preferably, in the low-latency ECC verification system based on the chip interconnect interface controller described in this invention, the system supports multiple flit payload sizes and expands data of less than 495 bits to a uniform bit width by padding with zeros in the high bits, thus adapting to the same set of ECC verification logic.

[0013] Furthermore, preferably, the present invention also provides a low-latency ECC verification method based on a chip interconnect interface controller. Utilizing any of the low-latency ECC verification systems based on a chip interconnect interface controller described in this invention, the method includes: at the transmitting end, generating a 10-bit ECC checksum for the flit data within a single clock cycle using an optimized generator matrix; at the receiving end, sending the received data in parallel into the main data path and the ECC verification branch; in the ECC verification branch, completing error detection and correction within two clock cycles and outputting the verification status; and selecting the output of the main data path or the ECC branch as the final data based on the verification status.

[0014] This invention reduces the number of logic stages for generating parity bits by optimizing the generation matrix, adopts a parallel processing structure of the main path and ECC branch at the receiving end, and combines a unified bit width adaptation mechanism to achieve single-cycle parity generation and two-cycle error correction at a high frequency of 1.5GHz, significantly reducing latency and hardware overhead. Attached Figure Description

[0015] Figure 1 This is a schematic diagram illustrating the flit format according to an embodiment of the present invention.

[0016] Figure 2 This is a schematic diagram illustrating a conventional scheme according to an embodiment of the present invention.

[0017] Figure 3 This is a schematic diagram illustrating the structure of an ECC verification system according to an embodiment of the present invention.

[0018] Figure 4This is a schematic diagram illustrating the ECC10 parity bit generation principle based on a generator matrix according to an embodiment of the present invention.

[0019] Figure 5 This is a schematic diagram of an ECC10 parity bit generation circuit based on a generator matrix according to an embodiment of the present invention.

[0020] Figure 6 This is a schematic diagram illustrating the ECC10 error correction and detection logic according to an embodiment of the present invention.

[0021] Figure 7 This is a schematic diagram illustrating a maskgen(i) module circuit according to one embodiment of the present invention.

[0022] Figure 8 This is a schematic diagram showing a circuit diagram of the parity_cs module according to an embodiment of the present invention.

[0023] Figure 9 This is a schematic diagram illustrating the input data bit width adaptation processing of an ECC verification system according to an embodiment of the present invention. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Other embodiments or modifications obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the scope of protection of this application.

[0025] Currently, a conventional solution according to one embodiment of the present invention is shown below. Figure 2 .

[0026] The left side of the dashed line in the diagram represents the transmitting side, where the TX1 interface receives data. The data bit width has four possible cases (e.g., ...). Figure 1 The data link layer has its own set of ECC generation modules for each data bit width. The ECC generation modules use ordinary ECC verification algorithms. In high-speed scenarios (such as SMIC 12nm process, where the chip interconnect interface controller operates at 1.5GHz), the generation logic is difficult to converge within one clock cycle.

[0027] The area to the right of the dashed line in the diagram represents the receiving side. The RX1 interface receives data first, and then sends the received data to the ECC verification module. The received data bit width has four possibilities (e.g., ...). Figure 1The data link layer (in the system) requires four different ECC verification modules. The processed data from the ECC verification modules is fed into a FIFO and finally sent to the upper layer of the system via RX2. In high-speed scenarios (e.g., SMIC 12nm process, where the chip interconnect interface controller operates at 1.5GHz), conventional ECC verification modules require more than two clock cycles to complete data error detection and correction. Furthermore, the serial connection between the conventional ECC verification modules and the main data path significantly increases the latency of the main data path.

[0028] Based on the conventional approach, the following problems exist: (1) Due to the high latency of the main data path caused by ECC verification, the data transmission efficiency is greatly affected. Assuming that data is sent from the local chip to the remote chip and then returned from the remote chip to the local chip, the extra latency due to ECC verification in the data path is as high as 6 clock cycles. For CPU systems with high latency requirements, such high latency is unacceptable.

[0029] (2) Conventional solutions require 8 ECC modules (4 ECC generation modules and 4 ECC verification modules), which increases chip area, resulting in long development cycles, large verification workload, excessive cost, and excessive power consumption.

[0030] According to a preferred embodiment of the present invention, a low-latency ECC verification system is provided in a chip interconnect interface controller. This low-latency ECC verification system is as follows: Figure 3 As shown in the figure, this diagram highlights the structures related to ECC verification in the data link layer, which are divided into the transmitting end and the receiving end.

[0031] The sending end: The data link layer receives data from the protocol layer via PAIF (protocol adapter interface), in units of split payloads. Each payload is accompanied by a header (corresponding to...). Figure 3 The "header added" part is then fed into the "ECC10_parity_gen" module, which generates a 10-bit ECC checksum as the tail part of the flit, and finally outputs the result. Figure 1 The complete flit format shown is described in point 2 below. This module, after synchronizing with the flit_fifo, ultimately sends the data to the physical layer via CPIF (chiplet phy interface).

[0032] Receiver section: The data link layer receives data from the physical layer via CPIF, processes it in two paths, and sends the data to the main path. Figure 3 In the "PAIF fifo", this fifo is a synchronous fifo; the branch sends data into it. Figure 3 The "ECC10_parity_chk" module performs ECC error detection and correction on the received data and outputs the verification result and the corrected data. For a detailed description of this module, please refer to point 3 below. The data read from the PAIF FIFO in the main path and the corrected data output from the "ECC10_parity_chk" module in the branch path are processed by a selector. The selection criterion is the verification result status signal output by the "ECC10_parity_chk" module. If there is no ECC verification error, the data read from the PAIF FIFO is selected; if there is a 1-bit error that has been corrected, the corrected data output by the "ECC10_parity_chk" module is selected; if there is an uncorrectable error greater than 1 bit, it is sent to the "error handler" module, which ultimately interrupts and uploads the error.

[0033] Furthermore, according to a preferred embodiment of the present invention, an optimization algorithm is provided to pre-determine a specific generator matrix for the optimal minimum odd-weight column key, such as... Figure 4 As shown, this specific generating matrix has the following characteristics: (1) The generated matrix is ​​10 rows x 495 columns. The values ​​of the row and column elements can only be 0 or 1. There are no columns with all zeros. (2) All columns in the generated matrix are distinct; (3) Each column of the generating matrix contains an odd number of 1s; (4) Minimize the total number of 1s in each row of the generated matrix. After optimization, the total number of 1s in each row is reduced to 242 or 241. (5) The total number of 1s in each row of the generated matrix is ​​optimized to be as close as possible. After optimization, there are 5 rows with a total number of 1s of 242 and another 5 rows with a total number of 1s of 241.

[0034] Based on the advantages of this generator matrix, the ECC10 checksum generation logic is implemented. The input data is the data to be checked, datain[484:0], with a bit width of 485 bits. In each row of the generator matrix, the positions of the first 485 elements that are 1 correspond to the corresponding bits of the input data. These bits are retained and then XORed. Each row is operated on in this way. The XOR result of the first row is used as the result of bit 0 of the generated 10-bit checksum, and so on. The XOR result of the tenth row is used as the result of bit 9 of the 10-bit checksum. Since the maximum number of 1s in each row of the generator matrix is ​​242, and the number of 1s in each row is evenly distributed, the maximum number of logic levels after the implementation of the ECC10 checksum generation logic is 8 levels (e.g., ...). Figure 5 As shown), the timing convergence is satisfied within one clock cycle (clock frequency is 1.5GHz).

[0035] Furthermore, according to a preferred embodiment of the present invention, a low-latency ECC verification system in a chip interconnect interface controller is provided, wherein the receiver of the chip interconnect interface controller implements ECC10 error detection and correction functions, such as... Figure 6 The strategy adopted is to design the main data path and branch (ECC error detection and correction) of the receiver in parallel. The advantage of this strategy is that the main data path of the receiver will not have increased latency due to the ECC error detection and correction logic, and the correct data can be selected in a timely manner based on the results of ECC10 error detection and correction.

[0036] Figure 6 The "parity_gen" module in this section has the same principle as the ECC10 checksum generation in point 2, using the same generation matrix. The difference is that the input data width of this module is 495 bits. In each row of the generation matrix, the positions of the 495 elements that are 1 correspond to the corresponding bits of the input data. These bits are retained and then XORed. Each row is operated on in this way. The XOR result of the first row is used as the result of bit 0 of the 10-bit checksum, and so on. The XOR result of the tenth row is used as the result of bit 9 of the 10-bit checksum.

[0037] Figure 6 The "ECC decoder" module implements the ECC10 checksum lookup table and error correction functionality. Based on the 10-bit parity data output from the "parity_gen" module, it sequentially... Figure 6 The constant1~constant485 are compared, and 485 masks (mask0~mask484) are generated in parallel. The "maskgen0~maskgen484" module (circuit shown) Figure 7 (As shown) The final 485-bit rmask is generated in parallel. The “parity_cs” module (circuit diagram shown) Figure 8 (As shown) Generate a 1-bit check result signal "cs" in parallel; Figure 6 The results of the 486th to 496th "10-bit comparators" are processed through OR operations to generate a 1-bit status signal "es". The "cs" and "es" signals are combined to form the final 2-bit status signal, which indicates the following: 2`b00: Valid data with no errors; 2`b11: Valid data with a 1-bit error that has been corrected; 2`b01: Valid data with an error greater than 1 bit that cannot be corrected; 2`b10: Invalid information.

[0038] Furthermore, according to a preferred embodiment of the present invention, a low-latency ECC verification system is provided in a chip interconnect interface controller. Existing ECC error correction and detection logic requires three clock cycles to complete at a 1.5GHz clock frequency. In this low-latency ECC verification system, the timing of the ECC10 error correction and detection logic can be converged within two clock cycles (clock frequency of 1.5GHz). Figure 6 As shown, the tributary delay of the ECC10 check at the receiving end is guaranteed to be less than the FIFO readout delay of the main data path, so no additional delay will be added.

[0039] Furthermore, according to a preferred embodiment of the present invention, a low-latency ECC verification system in a chip interconnect interface controller is provided. Since the chip interconnect interface specification defines four payload sizes in the flit, such as... Figure 1 As shown, in typical designs, four ECC verification systems are required to adapt to different payload sizes. Each ECC verification system has ECC check bit generation, ECC error correction, and error detection functions. This extends the development cycle, increases verification workload, significantly increases chip area, and raises cost and power consumption. The low-latency ECC verification system in this invention only requires one development, targeting a 60-byte data link layer. When the data link layer is one of the other three (16 bytes, 32 bytes, or 40 bytes), a high-bit padding method is used to adapt to the data bit width of the low-latency ECC verification system in this invention, such as... Figure 9 As shown in the figure. This method can simplify design, reduce development risks, effectively reduce chip area, and lower costs and power consumption.

[0040] Furthermore, the low-latency ECC verification system based on a chip interconnect interface controller provided according to a preferred embodiment of the present invention has the following key technical points: 1. The parity bit generation logic in the ECC verification system is based on a special generation matrix obtained in advance through an optimization algorithm. Based on this special generation matrix, the parity bit generation logic of ECC10 can be completed within one clock cycle (1.5GHz in SMIC12 process), reducing clock cycle latency.

[0041] 2. In the ECC verification system, the ECC error detection and correction logic and data path at the receiving end are designed in parallel. The receiving end data path will not increase the delay caused by the ECC error detection and correction logic, and can complete ECC multi-bit error detection and 1-bit error correction, reducing latency and improving data transmission efficiency.

[0042] 3. In the ECC verification system, the massive lookup table and decoding function of the ECC error detection and correction at the receiving end are designed in parallel, which can bring the timing of this decoder to converge within one clock cycle (1.5GHz under SMIC12 technology).

[0043] 4. Only one set of ECC verification system is designed to adapt to different payload sizes in the chip interconnect interface specification, which greatly shortens the design and development cycle, reduces the verification workload, effectively reduces chip area, reduces power consumption, and reduces production costs.

[0044] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0045] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0046] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0047] The above embodiments of the present invention are merely examples for clearly illustrating the present invention and are not intended to limit the implementation of the present invention. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively describe all possible implementations here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A low-latency ECC verification system based on a chip interconnect interface controller, characterized in that, Including the sender and receiver: The transmitting end includes an ECC check bit generation module, which is used to generate a 10-bit ECC check code for the data link layer flit data based on a pre-generated specific generation matrix, and insert the check code as a tail part into the flit format; The receiving end includes a main data path and an ECC verification branch configured in parallel, wherein: The main data path includes a first synchronous FIFO, which is used to directly buffer the received flit data; The ECC verification branch includes an ECC error detection and correction module, which is used to perform parallel error detection and correction on the received flit data, and output the verification status signal and the data after error correction. The selector, based on the verification status signal, selects to output either the data from the first synchronization FIFO or the error-corrected data from the ECC error detection and correction module, wherein... The specific generated matrix is ​​a 10-row × 495-column binary matrix that satisfies the following conditions: The matrix contains distinct columns and no columns consisting entirely of zeros. Each column contains an odd number of 1s; The total number of 1s in each row is 241 or 242, and the number of 1s in each row is evenly distributed.

2. The system according to claim 1, characterized in that, The ECC check bit generation module is configured as follows: For valid data with an input bit width of 485 bits, XOR operation is performed on the corresponding data bits according to the column position of 1 in each row of the specific generation matrix to generate a 10-bit ECC check code. The maximum number of levels of the XOR logic is no more than 8, which ensures that the timing converges within a single clock cycle at a clock frequency of 1.5 GHz.

3. The system according to claim 1, characterized in that, The ECC error detection and correction module includes: The checksum generation unit uses the same specific generation matrix as the transmitter to perform an XOR operation on the 495 bits of received data including the checksum bit to generate a 10-bit checksum result. The decoder unit is used to generate 485 mask signals and verification status signals in parallel based on the verification result; The error correction unit uses the mask signal to correct erroneous bits in the received data.

4. The system according to claim 3, characterized in that, The decoder unit includes: 485 parallel comparators compare the verification result with a predefined error mode constant to generate a mask control signal; The status decision circuit generates a 2-bit check status signal based on the comparison result, which is used to indicate no error, 1-bit error corrected, or multiple-bit uncorrectable error.

5. The system according to claim 1, characterized in that, The total processing delay of the ECC verification branch does not exceed 2 clock cycles and is less than the readout delay of the first synchronous FIFO in the main data path.

6. The system according to claim 1, characterized in that, The system supports multiple flit payload sizes and expands data less than 495 bits to a uniform bit width by padding with zeros in the high bits, adapting to the same set of ECC check logic.

7. A low-latency ECC verification method based on a chip interconnect interface controller, utilizing any one of the systems described in claims 1 to 6, characterized in that, The method includes: At the transmitting end, the optimized generator matrix is ​​used to generate a 10-bit ECC checksum for the flit data within a single clock cycle; At the receiving end, the received data is sent in parallel to the main data path and the ECC verification branch; In the ECC verification branch, error detection and correction are completed within 2 clock cycles, and the verification status is output. The output of the main data path or the ECC branch is selected as the final data based on the verification status.

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