LED algorithm implementation method
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- PENG TI STORAGE TECH (NANJING) CO LTD
- Filing Date
- 2026-04-01
- Publication Date
- 2026-07-21
Smart Images
Figure CN121966835B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of lightweight cryptographic algorithm technology, and in particular to an LED algorithm implementation method. Background Technology
[0002] With the rapid development of resource-constrained devices such as the Internet of Things, automotive electronics, and portable smart terminals, the demand for lightweight information security is becoming increasingly prominent. While traditional mainstream block cipher algorithms, such as AES, have been widely validated for their security, their relatively high computational overhead and hardware resource consumption make them unsuitable for direct application in embedded environments where computing power, storage space, and energy consumption are strictly limited. Therefore, lightweight cryptographic algorithms have emerged, aiming to minimize the hardware area, power consumption, and timing delays of algorithm implementation while meeting specific security levels.
[0003] The LED algorithm, a typical lightweight block cipher algorithm, employs a SPN structure and supports various key lengths, including 64-bit, 80-bit, and 128-bit. It has attracted attention due to its low hardware implementation requirements and balanced performance. However, when mapping this algorithm to actual hardware circuits, several challenges still arise that affect its lightweight objective. Firstly, the core column confusion operation of the LED algorithm involves finite fields. Matrix multiplication on LEDs, if its multiplication logic were directly implemented, would require complex combinational circuits and multiple iterations, significantly increasing critical path latency and hardware gate resource consumption. Secondly, encryption (decryption) is an inverse operation; traditional direct implementations often use two separate hardware logics to handle encryption and decryption, failing to fully utilize its symmetry for module reuse and resulting in low hardware area utilization. Furthermore, in applications requiring frequent switching or multiple keys, the lack of efficient key caching and management mechanisms necessitates retrieving the complete key externally for each operation, increasing access latency and system power consumption. Finally, the LED algorithm's round-by-round processing is typically sequential; the next round can only begin after the previous round of data processing is complete, limiting data processing throughput and making it difficult to meet the real-time encryption and decryption requirements of high-speed data streams.
[0004] Therefore, how to deeply optimize LED algorithms at the hardware level, while ensuring the inherent security of the algorithms, further reduce resource consumption, improve computational efficiency, and enhance the flexibility of key management, has become a pressing technical problem in this field. Summary of the Invention
[0005] To address the above problems, this invention proposes an LED algorithm implementation method.
[0006] To achieve the above objectives, the present invention employs the following technical solution:
[0007] An LED algorithm implementation method includes:
[0008] The process acquires the raw data to be processed, as well as the key identifier and key mode associated with the raw data. The key identifier is obtained by accessing the key cache to obtain the corresponding key, and the total number of rounds of the processing flow is determined based on the bit length of the key. The key mode includes an encryption mode and a decryption mode.
[0009] Perform an XOR operation on the original data and the key to obtain the round key plus data;
[0010] Based on the round key and data, the total number of rounds of the processing flow is executed cyclically, where each round includes:
[0011] The round constant is obtained by querying a preset round constant table based on the current round number, and then converted into a round constant matrix. The round constant matrix is then XORed with the round key plus data to obtain the round constant plus data. Based on the key pattern and the S-box substitution rule table, the round constant plus data undergoes S-box substitution or inverse S-box substitution to obtain S-box substituted data. Based on the key pattern, a bidirectional shift register is used to row-shift the S-box substituted data to obtain row-shifted data. Based on a preset finite field multiplication intermediate value table, the row-shifted data and the MDS matrix are multiplied in a finite field by table lookup and XOR / AND operations to obtain column obfuscated data. If the current round number is a multiple of 4 and less than the total number of rounds, the column obfuscated data is XORed with the key, and the result is used as the round key plus data for the next round input. If the current round number is not a multiple of 4 and less than the total number of rounds, the column obfuscated data is used as the round key plus data for the next round input. If the current round number equals the total number of rounds, the column obfuscated data is output.
[0012] As a preferred embodiment of the present invention, the key identifier is obtained by accessing the key cache and the corresponding key is stored in the key register. When processing the next piece of raw data, the key identifier associated with the raw data being processed is compared with the key identifier in the key register. If they are the same, the corresponding key is read directly from the key register. If they are different, the key cache is accessed to obtain the corresponding key, and the key identifier associated with the raw data being processed and the obtained key are stored in the key register.
[0013] As a preferred embodiment of the present invention, determining the total number of rounds of the processing flow based on the bit length of the key includes:
[0014] When the key length is 64 bits, the total number of rounds is 32; when the key length is 80 bits or 128 bits, the total number of rounds is 48.
[0015] As a preferred embodiment of the present invention, while performing an XOR operation on the original data and the key, a round number tag is attached to the original data. The round number tag is used to identify the round of each original data when multiple original data are processed in parallel, thereby realizing pipelined parallel processing of multiple original data.
[0016] As a preferred embodiment of the present invention, based on the key mode and the S-box substitution rule table, the round constant plus data is subjected to S-box substitution or inverse S-box substitution to obtain the S-box substituted data, including:
[0017] The S-box substitution rule table includes an S-box substitution table and an S-box inverse substitution table; the round constant plus data is split into 16 four-bit nibbles; when the key mode is encryption mode, the S-box substitution table is queried to replace each four-bit nibble of the round constant plus data to obtain the S-box substituted data; when the key mode is decryption mode, the S-box inverse substitution table is queried to replace each four-bit nibble of the round constant plus data to obtain the S-box substituted data.
[0018] As a preferred embodiment of the present invention, based on the key mode, a bidirectional shift register is used to perform row shifting on the S-box-substituted data to obtain row-shifted data, including:
[0019] If the key mode is encryption mode, the bidirectional shift register is set to left circular shift mode; if the key mode is decryption mode, the bidirectional shift register is set to right circular shift mode.
[0020] As a preferred embodiment of the present invention, the finite field multiplication intermediate value table is used to store the pre-calculated intermediate value corresponding to each fixed element in the MDS matrix; the intermediate value is a four-digit hexadecimal number, which is obtained by pre-calculating four intermediate state values corresponding to each fixed element in the MDS matrix according to the finite field multiplication rules; wherein each intermediate state value is obtained by performing finite field multiplication on the fixed element and a binary multiplier that is 1 in the 0th, 1st, 2nd or 3rd bit.
[0021] As a preferred embodiment of the present invention, obtaining column obfuscated data includes:
[0022] Arrange the row-shifted data into a 4x4 state matrix;
[0023] The output matrix is obtained by multiplying the state matrix and the MDS matrix over a finite field, wherein the calculation of each output element of the output matrix includes:
[0024] a. Perform four finite field multiplications on the four fixed elements in the corresponding row of the MDS matrix and the four data elements in the corresponding column of the state matrix. Each finite field multiplication includes: based on the fixed elements, querying the finite field multiplication intermediate value table to obtain the corresponding intermediate value; converting the data elements in the state matrix into four-bit binary numbers, and performing an XOR accumulation operation with the corresponding intermediate value; performing a AND operation between the XOR accumulation result and hexadecimal F to obtain the result of the finite field multiplication.
[0025] b. Perform an XOR operation on the results of the four finite field multiplications to obtain an output element of the output matrix;
[0026] Combining all the output elements of the output matrix yields column-mixed data.
[0027] As a preferred embodiment of the present invention, the data elements in the state matrix are converted into four-bit binary numbers, and XORed and accumulated with the corresponding intermediate values, including:
[0028] When the i-th bit of the data element is 1, it is XORed and accumulated with the corresponding intermediate value of the i-th bit.
[0029] The beneficial effects of this invention are as follows: First, by pre-compiling and solidifying the round constant table and the intermediate value table for finite field multiplication, the complex round constant generation and finite field multiplication are transformed into efficient table lookup and XOR operations, significantly reducing the scale of logic circuits and power consumption. Second, by utilizing configurable key modes and bidirectional shift registers, the encryption and decryption processes share core modules such as S-box substitution (inverse S-box substitution) and row shifting, achieving high reuse of hardware resources and saving chip area. Furthermore, by adding round number tags to the raw data, multiple sets of raw data can be processed in parallel in the pipeline, effectively improving overall throughput. Simultaneously, the key caching and key identifier matching mechanism avoids frequent access to external storage, improving key management efficiency. These optimizations are made while strictly adhering to the original mathematical definition of the algorithm, fully preserving the security of the LED algorithm and being compatible with multiple standard key lengths, providing an efficient, flexible, and lightweight encryption solution for resource-constrained scenarios such as the Internet of Things and automotive electronics. Attached Figure Description
[0030] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:
[0031] Figure 1 This is a flowchart of an LED algorithm implementation method in an embodiment of the present invention;
[0032] Figure 2 This is an architecture diagram of an LED algorithm implementation method in an embodiment of the present invention. Detailed Implementation
[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention are within the scope of protection of the present invention.
[0034] like Figures 1-2 As shown, this is an embodiment of the present invention, which provides an LED algorithm implementation method, including:
[0035] S1. Obtain the raw data to be processed, as well as the key identifier and key mode associated with the raw data. The key identifier is obtained by accessing the key cache to obtain the corresponding key, and the total number of rounds of the processing flow is determined according to the bit length of the key. The key mode includes encryption mode and decryption mode.
[0036] In this embodiment, the key identifier is obtained by accessing the key cache and simultaneously stored in the key register. When processing the next piece of raw data, the key identifier associated with the processed raw data is compared with the key identifier in the key register. If they are the same, the corresponding key is read directly from the key register. If they are different, the key cache is accessed to obtain the corresponding key, and the key identifier associated with the processed raw data and the obtained key are stored in the key register. When the key length is 64 bits, the total number of rounds is 32; when the key length is 80 bits or 128 bits, the total number of rounds is 48.
[0037] Specifically, global operating parameters are set by writing parameters into the configuration register. These parameters include: key length: selected using a 2-bit binary number, such as 00 (64-bit), 01 (80-bit), or 10 (128-bit); key mode: set to encryption or decryption mode; preloaded keys: all used keys are pre-written into a key cache, such as an SRAM, via software or an external interface. Each key is associated with a unique key identifier, such as an 8-bit address or index. A complete data packet is received, which includes at least: the raw data to be processed: 64-bit plaintext (encrypted) or ciphertext (decrypted); key identifier: indicating that the raw data to be processed should use the key from the key cache or key register; and key mode: indicating whether the raw data to be processed is in encryption or decryption mode. The wheel-stepping state machine parses the data packet, extracts the raw data, key identifier, and key mode, and latches them into an internal register. This internal register is a set of dedicated flip-flops or register units located within the wheel-stepping state machine logic.
[0038] The key register is used to cache used keys and their corresponding key identifiers. The key identifier in the current data packet to be processed is compared with the key identifier stored in the key register. If the key identifiers match, it means that the key to be used by the current raw data is the same as the key corresponding to the previously processed raw data; therefore, the cached key is read directly from the key register, skipping the key cache access. If the key identifiers do not match, the key is switched, and a read operation is performed on the key cache, using the current key identifier as the address or index to read the corresponding key from the key cache. After reading the new key from the key cache, the key register is updated simultaneously, storing the new key identifier and key in the key register for use by subsequent raw data. The round-robin state machine reads the key length set in the configuration register. If the key length is configured to 64 bits, the total number of rounds in the processing flow is set to 32 rounds; if the key length is configured to 80 bits or 128 bits, the total number of rounds in the processing flow is set to 48 rounds. The raw data, key, key mode, and total number of rounds are passed to the encryption / decryption pipeline. The round-robin state machine selects the operation path according to the key mode (encryption or decryption) and begins loop control.
[0039] S2. Perform an XOR operation on the original data and the key to obtain the round key plus data;
[0040] In this embodiment, while performing an XOR operation on the original data and the key, a round number tag is attached to the original data. The round number tag is used to identify the round of each original data when multiple original data are processed in parallel, thereby realizing pipelined parallel processing of multiple original data.
[0041] Specifically, before the round-step state machine begins its cyclic control, a round number tag is attached to the raw data. This round number tag is used to identify and track each piece of raw data entering the encryption / decryption pipeline. The round number tag must contain at least the following fields: raw data ID (used to distinguish multiple raw data being processed simultaneously), current processing round number, key identifier, key mode, and processing status. An active tag table is established to record the round number tag information for all raw data currently being processed. When a new data packet (containing raw data, key identifier, and key mode) arrives at the round-step state machine, the tag management unit allocates a new, idle round number tag to the raw data in the packet, fills the key identifier and key mode from the data packet into the corresponding fields of the round number tag, initializes the current processing round number of the round number tag to 0, and sets the processing status to ready. Before the raw data enters the encryption / decryption pipeline, an initial round key addition operation is performed, i.e., an XOR operation is performed between the raw data and the key. Subsequently, the current processing round number in the round number tag associated with the raw data is immediately updated to 1, and the processing status is changed to processing.
[0042] The round-step state machine treats the raw data carrying round number tags as a whole and incorporates it into a managed scheduling queue. The round-step state machine uses the current processing round number identified by the round number tag of each raw data as the primary scheduling basis, combined with the idle state of each stage of the encryption / decryption pipeline, to determine when the raw data enters the computation sequence. The hardware circuit divides a complete round computation sequence module (round constant addition module, S-box substitution / inverse substitution module, row shifting module, column obfuscation module) into multiple fixed pipeline processing stages. The round-step state machine allows multiple raw data to enter the pipeline processing stages in an overlapping manner; that is, when the current raw data is in stage X of round N, the next raw data can enter stage Y of round M, thus overlapping the execution of different round operations of different raw data in time, achieving parallel pipeline processing. For example, in a certain clock cycle, raw data A is performing round 5 operations in stage 2, while raw data B is performing round 3 operations in stage 1, and raw data C has just completed the initial round key addition operation and is ready to enter the encryption / decryption pipeline. The system performs corresponding operations based on the key mode of the current raw data. For example, in the S-box substitution operation, the encryption mode selects the S-box substitution module, and the decryption mode selects the S-box inverse substitution module. After the raw data completes the pipeline processing stage of the column obfuscation module, the round number tag carried by the raw data is checked, and the current processing round number recorded in the round number tag is determined: if the processing round number is a multiple of 4 and less than the total number of rounds, a round key addition operation is performed. After execution, the current processing round number field of the round number tag is incremented by 1. If the current processing round number is not a multiple of 4 and less than the total number of rounds, the raw data and the round number tag are sent back to the end of the scheduling queue, waiting for the round step state machine to schedule again to start the next round of processing. If the current processing round number equals the total number of rounds, it indicates that the raw data has been processed, and the round number tag status is set to complete. The processed raw data is then output. The round number tag is then released and allocated to subsequent new raw data. Since multiple raw data sets share the same physical computing module, the round-robin state machine must ensure that only one raw data set is occupied by a pipeline processing stage within the same clock cycle during scheduling. This is achieved by checking the busy / idle flags and round number tags of each pipeline processing stage in the encryption / decryption pipeline. If resource contention occurs, the round-robin state machine will make the later-arriving raw data set wait for one cycle.
[0043] S3. Based on the round key and data, execute the total number of rounds in a loop, where each round includes:
[0044] The round constant is obtained by querying a preset round constant table based on the current round number, and then converted into a round constant matrix. The round constant matrix is then XORed with the round key plus data to obtain the round constant plus data. Based on the key pattern and the S-box substitution rule table, the round constant plus data undergoes S-box substitution or inverse S-box substitution to obtain S-box substituted data. Based on the key pattern, a bidirectional shift register is used to row-shift the S-box substituted data to obtain row-shifted data. Based on a preset finite field multiplication intermediate value table, the row-shifted data and the MDS matrix are multiplied in a finite field by table lookup and XOR / AND operations to obtain column obfuscated data. If the current round number is a multiple of 4 and less than the total number of rounds, the column obfuscated data is XORed with the key, and the result is used as the round key plus data for the next round input. If the current round number is not a multiple of 4 and less than the total number of rounds, the column obfuscated data is used as the round key plus data for the next round input. If the current round number equals the total number of rounds, the column obfuscated data is output.
[0045] Specifically, the round constant addition module includes a round constant table memory to store a preset round constant table. This round constant table includes 48 entries (corresponding to 48 rounds), and each entry stores a value, for example, one byte, which is a compact encoding of the six-bit linear feedback shift register state value corresponding to the round number. A fixed, purely combinational logic circuit is designed, whose input is the six-bit linear feedback shift register state value, and whose output is a 64-bit round constant matrix. The connection of this fixed, purely combinational logic circuit strictly follows a fixed mapping rule. The round constant table is shown in Table 1.
[0046] Table 1. Wheel Constant Table
[0047]
[0048] The fixed mapping rule is as follows: When the wheel-step state machine starts a new round and gives the current round number, the current round number is sent as an address to the wheel constant table memory. The wheel constant table memory outputs the corresponding wheel constant based on the address. This wheel constant is the state value of the six-bit linear feedback shift register corresponding to that round number. The six bits of the six-bit linear feedback shift register state value are denoted as rc5, rc4, rc3, rc2, rc1, and rc0. These six bits are input to a preset wheel constant matrix generation logic circuit, which constructs a 4x4 matrix (64 bits) with all bits initialized to 0. The preset original matrix is:
[0049]
[0050] Assign bits rc5, rc4, and rc3 to rows 0 and 2 of the first column (second column from the left) of the original matrix. Assign bits rc2, rc1, and rc0 to rows 1 and 3 of the first column of the original matrix. Leave columns 0 and 2 of the original matrix as 0. This will output the final 64-bit round constant matrix. The generation of the round constant matrix is completed in real-time via hard-wired connections. The 64-bit round constant matrix and the input 64-bit round key plus data are simultaneously fed into a 64-bit wide parallel XOR gate array. This parallel XOR gate array performs an XOR operation on each corresponding bit, ultimately outputting a 64-bit round constant plus data, which is then sent to the next S-box substitution / inverse substitution module.
[0051] In this embodiment, the S-box substitution / reverse substitution module includes an S-box substitution rule table, which includes an S-box substitution table and an S-box reverse substitution table. The round constant plus data is split into 16 four-bit nibbles. When the key mode is encryption mode, the S-box substitution table is queried to replace each four-bit nibble of the round constant plus data to obtain the S-box substituted data. When the key mode is decryption mode, the S-box reverse substitution table is queried to replace each four-bit nibble of the round constant plus data to obtain the S-box substituted data.
[0052] Specifically, two independent, read-only lookup tables are set up in the hardware: an S-box substitution table (the mapping from plaintext to ciphertext) and an S-box inverse substitution table (the mapping from ciphertext to plaintext). Each table includes 16 entries, corresponding to a 4-bit input to a 4-bit output mapping; the S-box substitution table is shown in Table 2.
[0053] Table 2 S-Box Replacement Table
[0054]
[0055] The S-box reverse substitution table is shown in Table 3:
[0056] Table 3 S-box Reverse Substitution Table
[0057]
[0058] When the 64-bit round constant plus data is input to the S-box substitution / reverse substitution module, the hardware logic automatically treats this 64-bit round constant plus data as 16 independent 4-bit nibbles, and simultaneously and independently sends these 16 independent 4-bit nibbles into 16 parallel processing units. The key mode (encryption or decryption mode) is input to the S-box substitution / reverse substitution module as a global control signal. If the key mode is encryption mode, all 16 parallel processing units are connected to the S-box substitution table; each parallel processing unit uses each received 4-bit nibble as an address to look up the corresponding 4-bit output value in the S-box substitution table. If the key mode is decryption mode, all parallel processing units switch to connecting to the S-box reverse substitution table, and each parallel processing unit uses each received 4-bit nibble as an address to look up the corresponding 4-bit output value in the S-box reverse substitution table. Finally, the 16 4-bit output values from the 16 parallel processing units are recombine into a new 64-bit data, i.e., the S-box substituted data, and output to the next row shift module.
[0059] In this implementation, if the key mode is encryption mode, the bidirectional shift register is set to left circular shift mode; if the key mode is decryption mode, the bidirectional shift register is set to right circular shift mode.
[0060] Specifically, the core of this row shift module is a configurable bidirectional shift register array, consisting of four independent bidirectional shift registers. Each bidirectional shift register is responsible for processing one row (16 bits) of data after the S-box substitution. A key mode is input to the row shift module and controls the shift direction of the bidirectional shift register array. If the key mode is encryption mode, the control circuit configures the bidirectional shift register array in left circular shift mode; if the key mode is decryption mode, it configures it in right circular shift mode. When the 64-bit S-box substitution data is input, the 64-bit S-box substitution data is loaded row by row into the aforementioned bidirectional shift register array. The bidirectional shift register array performs parallel circular shifts of the four rows of data in the S-box substitution data according to a preset direction (left or right): row 0 is not shifted, row 1 is shifted by 1 half-byte position, row 2 is shifted by 2 half-byte positions, and row 3 is shifted by 3 half-byte positions. This shift operation is completed within one clock cycle. All shifted data is read out in parallel from the bidirectional shift register array, combined into 64-bit row shifted data, and sent to the subsequent column obfuscation module.
[0061] In this embodiment, the finite field multiplication intermediate value table is used to store the pre-calculated intermediate value corresponding to each fixed element in the MDS matrix; the intermediate value is a four-digit hexadecimal number, which is obtained by pre-calculating four intermediate state values corresponding to each fixed element in the MDS matrix according to the finite field multiplication rules; wherein each intermediate state value is obtained by performing finite field multiplication on the fixed element and a binary multiplier that is 1 in the 0th, 1st, 2nd or 3rd bit.
[0062] Arrange the row-shifted data into a 4x4 state matrix;
[0063] The output matrix is obtained by multiplying the state matrix and the MDS matrix over a finite field, wherein the calculation of each element of the output matrix includes:
[0064] a. Perform four finite field multiplications on the four fixed elements in the corresponding row of the MDS matrix and the four data elements in the corresponding column of the state matrix. Each finite field multiplication includes: obtaining the corresponding intermediate value by querying the finite field multiplication intermediate value table based on the fixed elements; converting the data elements in the state matrix into four-bit binary numbers and performing an XOR accumulation operation with the corresponding intermediate value; performing a AND operation between the XOR accumulation result and hexadecimal F to obtain the result of the finite field multiplication; when the i-th bit of the data element is 1, performing an XOR accumulation operation with the corresponding i-th bit intermediate value.
[0065] b. Perform an XOR operation on the results of the four finite field multiplications to obtain an element of the output matrix;
[0066] Combining all elements of the output matrix yields column-mixed data.
[0067] Specifically, the 4x4 MDS matrix (whose fixed elements are 4-bit constants, such as 4, 1, 2, B, etc.) defined in the LED algorithm standard is directly encoded in the hardware logic. The MDS matrix in this implementation is:
[0068]
[0069] A pre-defined intermediate value table for finite field multiplication is stored in the hardware. The contents of this table are pre-generated according to the rules of finite field multiplication. Specifically, for each fixed element in the MDS matrix, the intermediate value of the XOR operation performed when that fixed element is multiplied by a 4-bit binary number whose bits are 1 only in the 0th, 1st, 2nd, or 3rd bit, is pre-calculated according to the rules of finite field multiplication. This establishes a mapping relationship from each fixed element to its corresponding set of intermediate values, thereby transforming the complex finite field multiplication into an efficient table lookup and bit-by-bit XOR operation during hardware runtime. The intermediate value table for finite field multiplication in this embodiment is shown in Table 4.
[0070] Table 4 Intermediate Values for Finite Field Multiplication
[0071]
[0072] When 64-bit row-shifted data is input to the column obfuscation module, the following steps are performed:
[0073] The input 64-bit row-shifted data is arranged into a 4x4 state matrix according to the rules of the LED algorithm. Each data element in this state matrix is a 4-bit binary number (half a byte), with a total of 16 data elements corresponding to the 64-bit row-shifted data. The four columns of data elements in the state matrix are processed in parallel or using highly pipelined serial processing, so that each column of the state matrix is independently multiplied by all rows of the MDS matrix to generate the corresponding column of the output matrix. For the current column of the state matrix, finite field multiplication is performed sequentially with the four fixed elements of the MDS matrix, and the four output elements of the corresponding column in the output matrix are calculated. The finite field multiplication specifically includes:
[0074] Step 1: The i-th row of the MDS matrix has 4 fixed elements, and the j-th column of the state matrix has 4 data elements. Perform finite field multiplication on these 4 pairs of fixed elements and data elements respectively, and then perform an XOR operation on the results of the 4 finite field multiplications.
[0075] Step 2: For a finite field multiplication of a pair of fixed elements and data elements, this is accomplished through table lookup and XOR. Specifically, it includes: using the fixed element as an index, querying the intermediate value table for finite field multiplication to immediately obtain the corresponding four intermediate values, denoted as follows: , , , Represent the data element as a 4-bit binary number, such as... , , , And each bit is used as a selection signal, if... If the value is 1, then the middle value is selected. If participation is cumulative, If the value is 1, then the middle value is selected. If participation is cumulative, If the value is 1, then the middle value is selected. If participation is cumulative, If the value is 1, then the middle value is selected. The process involves summing all selected intermediate values by performing an XOR operation to obtain a summed value. This summed value is then bitwise ANDed with the hexadecimal number 0xF (binary 1111) to obtain a finite field multiplication result of a pair of fixed elements and data elements.
[0076] Step 3: Repeat step 2 for the four pairs of fixed elements and data elements corresponding to the rows and columns to obtain four finite field multiplication results. Perform an XOR operation on these four finite field multiplication results to finally obtain the output element in the i-th row and j-th column of the output matrix.
[0077] After each column of the state matrix is multiplied by all rows of the MDS matrix using a finite field multiplication, a 4x4 output matrix is obtained. The 16 4-bit output elements of this matrix are then rearranged into a 64-bit data set in either row-major or column-major order. This 64-bit data set is the final column-mixed data. For the hardware implementation architecture of the above operation, refer to [reference needed]. Figure 2 As shown.
[0078] The wheel-step state machine internally maintains a counter for the current round number. After each round of column obfuscation, if the current round number is a multiple of 4 and less than the total number of rounds, the wheel-step state machine triggers a round key addition operation. Specifically, this involves XORing the column obfuscation data and the key in a 64-bit unit, using the result as the input for the next iteration—the next round's round key addition data. If the current round number is not a multiple of 4 and less than the total number of rounds, the column obfuscation data is directly used as the input for the next round. Regardless of whether a round key addition operation is performed, the wheel-step state machine increments the current round number counter by 1 to advance the processing flow.
[0079] The wheel-step state machine continuously compares the current round number with the total number of rounds. When the current round number is greater than or equal to the total number of rounds, it indicates that all rounds have been completed. The wheel-step state machine sends the final calculated column obfuscation data as the final result of encryption or decryption from the output interface and generates a completion signal.
[0080] In summary, this invention first transforms the most complex operations in the algorithm into simple table lookups and XOR operations through round constant pre-computation lookup, column obfuscation intermediate value pre-computation, and module reuse techniques. This eliminates the complex arithmetic logic units required in traditional implementations, significantly saving chip area and the number of logic gates. Secondly, data processing efficiency and throughput are significantly improved. Specifically, a pipeline mechanism with round number tags is introduced, allowing multiple raw data to be processed in parallel across different round numbers. Combined with a key matching and checking mechanism to reduce key reading latency, the data path is comprehensively optimized, achieving high-throughput continuous encryption and decryption. Furthermore, power consumption is effectively controlled. Specifically, a simplified circuit structure, reduced redundant computation, and optimization of SRAM access frequency collectively reduce dynamic and static power consumption. Finally, it offers high flexibility and scalability, including support for dynamic configuration of multiple key lengths, seamless switching between encryption and decryption modes, and easy adaptation to system buses of different bit widths through a multi-core parallel architecture. In summary, this invention achieves an optimized balance between area, speed, and power consumption while ensuring algorithm security, making it particularly suitable for high-performance applications with limited resources, such as the Internet of Things and embedded systems.
[0081] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any other combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product, which includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions according to this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another.
[0082] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. This storage medium can be a read-only memory, a disk, or an optical disk, etc.
[0083] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A method for implementing an LED algorithm, characterized in that, include: The process acquires the raw data to be processed, as well as the key identifier and key mode associated with the raw data. The key identifier is obtained by accessing the key cache to obtain the corresponding key, and the total number of rounds of the processing flow is determined based on the bit length of the key. The key mode includes an encryption mode and a decryption mode. Perform an XOR operation on the original data and the key to obtain the round key plus data; Based on the round key and data, the total number of rounds of the processing flow is executed cyclically, where each round includes: The round constant is obtained by querying a preset round constant table based on the current round number, and then converted into a round constant matrix. The round constant matrix is XORed with the round key plus data to obtain the round constant plus data. Based on the key mode and the S-box substitution rule table, the round constant plus data is subjected to S-box substitution or inverse S-box substitution to obtain the S-box substituted data. Based on the key mode, the S-box substituted data is row-shifted using a bidirectional shift register to obtain row-shifted data. Based on a preset finite field multiplication intermediate value table, the row-shifted data and the MDS matrix are multiplied in a finite field by table lookup and XOR and AND operations to obtain column-mixed data. The finite field multiplication intermediate value table is used to store the pre-calculated intermediate value corresponding to each fixed element in the MDS matrix; the intermediate value is a four-digit hexadecimal number, which is obtained by pre-calculating four intermediate state values corresponding to each fixed element in the MDS matrix according to the finite field multiplication rules; wherein each intermediate state value is obtained by performing finite field multiplication on the fixed element and a binary multiplier that is 1 in the 0th, 1st, 2nd or 3rd bit; The obtained column obfuscation data includes: Arrange the row-shifted data into a 4x4 state matrix; The output matrix is obtained by multiplying the state matrix and the MDS matrix over a finite field, wherein the calculation of each output element of the output matrix includes: a. Perform four finite field multiplications on the four fixed elements in the corresponding row of the MDS matrix and the four data elements in the corresponding column of the state matrix. Each finite field multiplication includes: based on the fixed elements, querying the finite field multiplication intermediate value table to obtain the corresponding intermediate value; converting the data elements in the state matrix into four-bit binary numbers, and performing an XOR accumulation operation with the corresponding intermediate value; performing a AND operation between the XOR accumulation result and hexadecimal F to obtain the result of the finite field multiplication. b. Perform an XOR operation on the results of the four finite field multiplications to obtain an output element of the output matrix; Combine all the output elements of the output matrix to obtain column-mixed data; If the current round number is a multiple of 4 and less than the total number of rounds, the column obfuscation data and the key are XORed, and the result is used as the round key plus data for the next round input; if the current round number is not a multiple of 4 and less than the total number of rounds, the column obfuscation data is used as the round key plus data for the next round input; if the current round number is equal to the total number of rounds, the column obfuscation data is executed and output.
2. The LED algorithm implementation method according to claim 1, characterized in that, The key identifier is obtained by accessing the key cache and the corresponding key is stored in the key register. When processing the next piece of raw data, the key identifier associated with the raw data being processed is compared with the key identifier in the key register. If they are the same, the corresponding key is read directly from the key register. If they are different, the key cache is accessed to obtain the corresponding key, and the key identifier associated with the raw data being processed and the obtained key are stored in the key register.
3. The LED algorithm implementation method according to claim 1, characterized in that, The total number of rounds in the processing flow is determined based on the bit length of the key, including: When the key length is 64 bits, the total number of rounds is 32; when the key length is 80 bits or 128 bits, the total number of rounds is 48.
4. The LED algorithm implementation method according to claim 1, characterized in that, While performing an XOR operation on the raw data and the key, a round number tag is attached to the raw data. The round number tag is used to identify the round of each raw data when multiple raw data are processed in parallel, so as to realize pipeline parallel processing of multiple raw data.
5. The LED algorithm implementation method according to claim 4, characterized in that, Based on the key mode and the S-box substitution rule table, the round constant plus data is subjected to S-box substitution or inverse S-box substitution to obtain the S-box substituted data, including: The S-box substitution rule table includes an S-box substitution table and an S-box inverse substitution table; the round constant plus data is split into 16 four-bit nibbles; when the key mode is encryption mode, the S-box substitution table is queried to replace each four-bit nibble of the round constant plus data to obtain the S-box substituted data; when the key mode is decryption mode, the S-box inverse substitution table is queried to replace each four-bit nibble of the round constant plus data to obtain the S-box substituted data.
6. The LED algorithm implementation method according to claim 5, characterized in that, Based on the aforementioned key mode, a bidirectional shift register is used to perform row shifting on the data after S-box substitution to obtain row-shifted data, including: If the key mode is encryption mode, the bidirectional shift register is set to left circular shift mode; if the key mode is decryption mode, the bidirectional shift register is set to right circular shift mode.
7. The LED algorithm implementation method according to claim 6, characterized in that, Convert the data elements in the state matrix into four-bit binary numbers, and perform an XOR accumulation operation with the corresponding intermediate values, including: When the i-th bit of the data element is 1, it is XORed and accumulated with the corresponding intermediate value of the i-th bit.