A method for manufacturing a semiconductor structure and a semiconductor structure

Abstract

The application provides a semiconductor structure preparation method and a semiconductor structure, and particularly relates to the semiconductor field. The semiconductor preparation method comprises the following steps: providing a substrate, wherein the substrate comprises a substrate, a gate structure formed on the substrate, and ion-doped regions respectively located in the substrate on both sides of the gate structure; forming a sacrificial layer on the surface of the substrate; performing high-energy ion sputtering treatment on the sacrificial layer; forming an initial stress layer on the surface of the sacrificial layer; and performing solidification treatment on the initial stress layer to form a stress layer. The semiconductor structure preparation method can eliminate stress concentration points of the stress layer and reduce crack generation by forming a sacrificial layer and performing ion sputtering treatment on the sacrificial layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Technology

[0002] With the development of CMOS integrated circuit manufacturing processes and the shrinking of critical dimensions, many new methods have been applied to device manufacturing processes to improve device performance. Among them, high-stress silicon nitride thin films have been introduced into integrated circuit manufacturing processes because they can effectively improve the carrier mobility of MOSFETs, thereby increasing device operating speed. In existing technologies, to increase the stress of silicon nitride thin films, a curing process is usually performed. When the thickness of the silicon nitride thin film is relatively large, it is prone to cracking and breakage, which seriously affects the performance and yield of MOSFETs. Summary of the Invention

[0003] This invention provides a method for fabricating a semiconductor structure and a semiconductor structure to reduce cracking of the stress layer.

[0004] The present invention provides a method for fabricating a semiconductor structure, comprising:

[0005] A substrate is provided, the substrate including a substrate, a gate structure formed on the substrate, and ion-doped regions respectively located in the substrate on both sides of the gate structure;

[0006] A sacrificial layer is formed on the surface of the substrate;

[0007] The sacrificial layer is subjected to high-energy ion sputtering treatment;

[0008] An initial stress layer is formed on the surface of the sacrificial layer;

[0009] The initial stress layer is cured to form a stress layer.

[0010] In one embodiment of the present invention, the thickness of the sacrificial layer is 50~100 Å.

[0011] In one embodiment of the present invention, the bias power during the high-energy ion sputtering process is 1500~2000W.

[0012] In one embodiment of the present invention, the initial stress layer is cured by ultraviolet light irradiation, the curing temperature is 350~400℃, and the curing time is 90~150s.

[0013] In one embodiment of the present invention, after the sacrificial layer is subjected to high-energy ion sputtering treatment, the thickness of the sacrificial layer is 5~10 Å.

[0014] In one embodiment of the present invention, the initial stress layer is formed by chemical vapor deposition, and the material of the initial stress layer is silicon nitride.

[0015] In one embodiment of the present invention, when the initial stress layer is formed, the flow rate of the reactants increases linearly at a preset rate to a set flow rate.

[0016] In one embodiment of the present invention, the preset rate is 200~500 sccm / s.

[0017] In one embodiment of the present invention, the substrate further includes a trench isolation structure, the trench isolation structure being located in the substrate on the side of the ion-doped region opposite to the gate structure.

[0018] The present invention also provides a semiconductor structure fabricated using any of the above-described preparation methods.

[0019] The beneficial effects of this invention are as follows: The method for fabricating a semiconductor structure proposed in this invention involves depositing a sacrificial layer and performing high-energy ion sputtering treatment on it, then depositing an initial stress layer on the surface of the high-energy ion sputtered sacrificial layer, and finally curing the initial stress layer to form a stress layer. An unexpected effect of this application is that by performing high-energy ion sputtering treatment on the sacrificial layer, the portion of the sacrificial layer located at the corner between the gate structure and the ion-doped region can be made arc-shaped. The subsequently formed stress layer inherits this arc-shaped morphology, thereby effectively eliminating stress concentration points. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0021] In the attached diagram:

[0022] Figure 1A This is a transmission electron microscope (TEM) image of a stress layer after curing treatment in the prior art;

[0023] Figure 1B This is a transmission electron microscope image of a stress layer after another curing treatment in the prior art;

[0024] Figure 2 This is a flowchart illustrating the fabrication process of a semiconductor structure provided in one embodiment of the present invention;

[0025] Figure 3 This is a schematic diagram of forming a pad oxide layer and a pad nitride layer on a substrate according to an embodiment of the present invention;

[0026] Figure 4 This is a schematic diagram of the formation of a trench provided in one embodiment of the present invention;

[0027] Figure 5 This is a schematic diagram of forming a trench isolation structure provided in one embodiment of the present invention;

[0028] Figure 6 This is a schematic diagram of removing the pad oxide layer and the pad nitride layer according to an embodiment of the present invention;

[0029] Figure 7 This is a schematic diagram of the formation of the gate structure and sidewall structure provided in one embodiment of the present invention;

[0030] Figure 8 This is a schematic diagram of the formation of an ion-doped region provided in one embodiment of the present invention;

[0031] Figure 9 This is a schematic diagram of the formation of a sacrificial layer provided in one embodiment of the present invention;

[0032] Figure 10 This is a schematic diagram of high-energy ion sputtering treatment of the sacrificial layer provided in one embodiment of the present invention;

[0033] Figure 11 This is a schematic diagram of the formation of an initial stress layer provided in one embodiment of the present invention;

[0034] Figure 12 This is a schematic diagram of the formation of a stress layer provided in one embodiment of the present invention;

[0035] Figure 13 This is a correspondence between the thickness of the stress layer and the hydrogen content and stress provided in one embodiment of the present invention.

[0036] The attached figures are labeled as follows:

[0037] 10. Substrate; 100. Substrate; 110. Pad oxide layer; 120. Pad nitride layer; 200. Gate structure; 210. Gate oxide layer; 220. Gate material layer; 221. First material layer; 222. Second material layer; 300. Ion-doped region; 310. Source; 320. Drain; 400. Photoresist layer; 500. Trench; 510. Trench isolation structure; 600. Sidewall structure; 20. Sacrificial layer; 30. Initial stress layer; 40. Stress layer. Detailed Implementation

[0038] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0039] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0040] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0041] In this document, when referring to numerical ranges, unless otherwise specified, the distribution of selectable values ​​within a numerical range is considered continuous, including the two endpoints of the range (i.e., the minimum and maximum values), and every value between these two endpoints. When multiple numerical ranges are provided to describe a feature or property, these numerical ranges can be combined.

[0042] In semiconductor fabrication, existing technologies often use ultraviolet (UV) photopolymerization to treat deposited silicon nitride (Si) films, causing the Si-H and NH bonds within the film to break and form Si-N bonds. This promotes film densification and shrinkage, introducing high tensile stress, thereby effectively improving the carrier mobility and operating speed of NMOS devices. However, when the Si nitride thickness exceeds 150 Å, the high-stress film formed by UV curing, when covering a MOS gate structure with a high aspect ratio and uneven topography (especially at sharp corners at the bottom), will produce a significant stress concentration effect. This localized stress concentration can easily lead to film cracking (e.g., ...). Figure 1A and Figure 1B The area marked with a red circle in the middle is shown. Figure 1A To enlarge by 1.2×10 5 Transmission electron microscope image at 100x magnification. Figure 1B To enlarge to 5.8×10 4(The image shows a transmission electron microscope image at magnification). Cracks formed during this process can become channels for moisture and impurities to penetrate into the device during subsequent processes, leading to leakage current and ultimately severely damaging the electrical performance and process yield of the MOS device. Current technologies often employ two or more deposition / curing processes to form silicon nitride thin films. However, when the silicon nitride thickness is greater (e.g., above 400 Å), multiple deposition / curing processes not only affect production efficiency and capacity but also accumulate thermal costs, impacting MOS performance. Therefore, this application provides a method for fabricating a semiconductor structure to reduce the risk of stress layer cracking.

[0043] Please see Figures 2 to 12 As shown, the method for fabricating the semiconductor structure provided by the present invention includes:

[0044] S1, providing such Figure 8 The substrate 10 shown includes a substrate 100, a gate structure 200 formed on the substrate 100, and ion-doped regions 300 located in the substrate 100 on both sides of the gate structure 200.

[0045] S2, such as Figure 9 As shown, a sacrificial layer 20 is formed on the surface of the substrate 10;

[0046] S3, such as Figure 10 As shown, the sacrificial layer 20 is subjected to high-energy ion sputtering treatment;

[0047] S4, such as Figure 11 As shown, an initial stress layer 30 is formed on the surface of the sacrificial layer 20;

[0048] S5, such as Figure 12 As shown, the initial stress layer 30 is cured to form the stress layer 40.

[0049] Please see Figures 3 to 8 As shown, in step S1 of this invention, the preparation process of the substrate 10 is as follows:

[0050] Please see Figure 3 As shown, a substrate 100 is first provided. The substrate 100 can be any material suitable for forming a semiconductor structure, such as undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). This invention does not limit the specific material and thickness of the substrate 100, and the substrate 100 can be a P-doped semiconductor substrate or an N-doped semiconductor substrate. The doping type of the impurities can be flexibly set according to the desired semiconductor structure. In this embodiment, the substrate 100 is, for example, a silicon substrate.

[0051] Please see Figure 3 As shown, in one embodiment of the present invention, a pad oxide layer 110 is formed on the surface of the substrate 100. The pad oxide layer 110 can serve as a protective layer for the substrate 100, protecting the substrate 100 it covers in subsequent processes and preventing unnecessary damage to the substrate 100. Furthermore, since the subsequently formed pad nitride layer 120 has high stress, dislocations are easily generated on the surface of the substrate 100 when the pad nitride layer 120 is formed on the substrate 100. The pad oxide layer 110 can provide a buffer during the formation of the pad nitride layer 120, preventing dislocations from being generated on the substrate 100 by the pad nitride layer 120. The material of the pad oxide layer 110 can be silicon dioxide or similar materials, and the pad oxide layer 110 can be formed by any one of the following methods: dry oxidation, wet oxidation, or in-situ steam generation (ISSG). In this embodiment, the pad oxide layer 110 is formed, for example, by a dry oxygen oxidation method. Exemplarily, the substrate 100 is placed in a furnace tube, oxygen is introduced, and the surface of the substrate 100 reacts with the oxygen at a high temperature to generate a dense pad oxide layer 110. Before forming the pad oxide layer 110, the preparation process of the substrate 10 may also include cleaning the substrate 100. By cleaning the substrate 100, impurities present on the surface of the substrate 100 can be removed, preventing impurities from affecting subsequent processes and thus ensuring device performance. For example, a cleaning solution can be used to clean the substrate 100, or a gas such as nitrogen can be used to purge the substrate 100 to achieve cleaning.

[0052] Please see Figure 3 As shown, in one embodiment of the present invention, after forming the pad oxide layer 110, a pad nitride layer 120 is formed on the pad oxide layer 110. The material of the pad nitride layer 120 can be silicon nitride or oxynitride; in this embodiment, the pad nitride layer 120 is, for example, silicon nitride. The pad nitride layer 120 can be prepared by any one of the following processes: low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or high-density plasma chemical vapor deposition. For example, when preparing the pad nitride layer 120 using a low-pressure chemical vapor deposition process, silicon nitride can be generated by reacting ammonia and dichlorosilane. By setting the pad nitride layer 120, it can not only serve as a mask during the subsequent formation of the trench 500, protecting the substrate 100 from damage during etching, but also protect the substrate 100 from planarization processes such as chemical mechanical polishing (CMP) involved in the fabrication of the trench isolation structure 510.

[0053] Please see Figure 4As shown, in one embodiment of the present invention, after forming the pad nitride layer 120, photoresist is coated on the surface of the pad nitride layer 120 to form a photoresist layer 400. The type of photoresist material is not limited; it can be a common positive photoresist material or a negative photoresist material. After coating the photoresist, photolithography processes such as mask exposure and development are used to pattern the coated photoresist, exposing the trench area. Using the patterned photoresist layer 400 as a mask layer, the pad nitride layer 120, the pad oxide layer 110, and the substrate 100 are etched sequentially to form trenches 500. The number, position, depth, and width of the trenches 500 are set according to actual needs and are not limited here. In this embodiment, the trenches 500 extend from the pad nitride layer 120 into the substrate 100, and the shape of the trenches 500 is rectangular. The pad nitride layer 120, the pad oxide layer 110, and part of the substrate 100 can be removed sequentially by dry etching to form a trench 500. The etching gas includes one or more of the following: chlorine (Cl2), trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), or hydrogen bromide (HBr), or a combination thereof with oxygen (O2). After etching, the photoresist layer 400 is removed by wet cleaning or ashing.

[0054] Please see Figure 5 As shown, in one embodiment of the present invention, after forming the trench 500, an insulating medium is deposited within the trench 500 until the insulating medium covers the surface of the nitride layer 120. The present invention does not limit the deposition method of the insulating medium; for example, it can be formed by deposition methods such as high-density plasma chemical vapor deposition (HDP-CVD) or high-aspect-ratio process chemical vapor deposition (HARP-CVD). The insulating medium is, for example, an insulating material such as silicon oxide or fluorosilicone glass with high adaptability to abrasion. After depositing the insulating medium, a high-temperature tempering process is performed, for example, to increase the density and stress characteristics of the insulating medium.

[0055] After depositing the insulating dielectric, the insulating dielectric is planarized, for example by chemical mechanical polishing, to obtain a trench isolation structure 510, which is at least partially exposed above the substrate 100. For example, the trench isolation structure 510 is obtained by polishing away part of the insulating dielectric. This invention does not limit the termination position of the insulating dielectric planarization and can be flexibly set according to the semiconductor device design requirements. For example, the insulating dielectric within a portion of the trench 500 can be planarized to be flush with the surface of the pad nitride layer 120. This invention does not limit the number of trench isolation structures 510 and can be adjusted according to the requirements of the desired semiconductor.

[0056] Please see Figure 6As shown, in one embodiment of the present invention, after forming the trench isolation structure 510, the pad oxide layer 110 and the pad nitride layer 120 on the surface of the substrate 100 are removed. The present invention does not limit the method for removing the pad oxide layer 110 and the pad nitride layer 120; for example, dry etching, wet etching, or a combination of dry and wet etching can be used. In this embodiment, for example, phosphoric acid is used to etch and remove the pad nitride layer 120, and hydrofluoric acid is used to remove the pad oxide layer 110. After removing the pad oxide layer 110, the insulating medium can also be etched to adjust the height of the trench isolation structure 510. Exemplarily, wet etching or dry etching is used to adjust the height of the trench isolation structure 510, for example, so that the trench isolation structure 510 is flush with the substrate 100.

[0057] Please see Figure 7 As shown, in one embodiment of the present invention, after removing the pad oxide layer 110 and the pad nitride layer 120, a gate structure 200 is formed on the substrate 100. Specifically, a gate oxide layer 210 is first formed on the surface of the substrate 100, and then a gate material layer 220 is formed on the surface of the gate oxide layer 210. In this embodiment, the material of the gate oxide layer 210 is, for example, silicon oxide. The gate oxide layer 210 is formed, for example, by thermal oxidation, chemical vapor deposition, or physical vapor deposition. The gate material layer 220 is, for example, a polysilicon layer, and the polysilicon layer can be P-type doped or N-type doped. In this embodiment, the gate material layer 220 includes a first material layer 221 and a second material layer 222, where the first material layer 221 is, for example, a polysilicon layer, and the second material layer 222 is, for example, a P-type doped or N-type doped polysilicon layer. In other embodiments, the material and thickness of the gate material layer 220 can be set according to actual needs. The gate material layer 220 and the gate oxide layer 210 are then etched using, for example, a dry etching process, a wet etching process, or a combination of dry and wet etching processes to form the gate structure 200. In other embodiments, the gate material layer 220 may also be, for example, a metal gate layer.

[0058] Please see Figure 7As shown, in one embodiment of the present invention, after forming the gate structure 200, sidewall structures 600 are formed on both sides of the gate structure 200. Specifically, a dielectric layer (not shown in the figure) is formed on the gate structure 200 and the substrate 100, and the dielectric layer includes, for example, a silicon oxide layer. The dielectric layer is formed, for example, by high-temperature thermal oxidation, including methods such as dry thermal oxidation, wet thermal oxidation, or in-situ steam generation (ISSG). The dielectric layer is then subjected to nitriding treatment, for example, by one or a combination of methods such as decoupled plasma nitriding (DPN), rapid thermal nitriding (RTN), or ammonia immersion, to nitrid the surface of the dielectric layer, forming a nitrided layer and improving the stability of the sidewall structure 600. By employing wet etching, dry etching, or a combination of wet and dry etching methods, the dielectric layers on both sides of the gate structure 200 are preserved, thereby forming single-layer or multi-layer sidewall structures 600 on both sides of the gate. This effectively controls the effects of parasitic capacitance and improves the performance of the semiconductor device. Furthermore, in this embodiment, before forming the sidewall structures 600 on both sides of the gate structure 200, lightly doped regions can be formed, for example, within the substrate 100 on both sides of the gate structure 200 via ion implantation.

[0059] Please see Figure 8 As shown, in one embodiment of the present invention, after forming the sidewall structure 600, ion-doped regions 300 are formed on the substrates 100 located on both sides of the gate structure 200. For example, impurity ions are implanted into the substrates 100 on both sides of the sidewall structure 600 using the sidewall structure 600 as a mask, or a mask layer is formed on the sidewall structure 600 and the gate material layer 220, exposing the substrates 100 on both sides of the gate structure 200, and impurity ions are implanted into the substrates 100 on both sides of the gate structure 200. In this embodiment, impurity ions are implanted into the substrates 100 on both sides of the sidewall structure 600 using the sidewall structure 600 as a mask. The implanted impurity ions are, for example, N-type impurities such as phosphorus (P) or arsenic (As), forming ion-doped regions 300 on both sides of the gate structure 200. The ion-doped regions 300 on both sides of the gate structure 200 are defined as the source 310 and the drain 320, respectively. In the present invention, the positions of the source 310 and the drain 320 can be interchanged. The present invention does not limit the method of implanting impurity ions, and the implantation depth, width or concentration of impurity ions are set according to the specific semiconductor structure, for example.

[0060] Please see Figure 9As shown, in step S2 of this invention, a sacrificial layer 20 is formed on the surface of the substrate 10. The sacrificial layer 20 covers the surface of the gate structure 200, the surface of the sidewall structure 600, the surface of the ion-doped region 300, and the surface of the trench isolation structure 510. In this invention, the sacrificial layer 20 is, for example, an oxide layer or a nitride layer, or, for example, SiN or SiO2. In this embodiment, plasma-enhanced atomic layer deposition (PEALD) is used to form the sacrificial layer 20. PEALD has good conformal properties. During the formation of the sacrificial layer 20 using PEALD, reactants are introduced in alternating pulses. One reactant pulse undergoes saturation adsorption on the surface of the substrate 10, forming a monolayer, after which the reaction automatically stops. Subsequently, another reactant is activated by plasma, causing it to react with the already adsorbed monolayer to generate a uniform solid film. This layer-by-layer growth mode ensures that the solid film can grow at the same rate on the surface of the substrate 10, guaranteeing the uniformity of the thickness of the sacrificial layer 20. This avoids the thinner areas being penetrated first during subsequent high-energy ion sputtering, exposing the underlying material and causing short circuits or contamination, or the thicker areas still having residue, leading to structural deformities and affecting subsequent processes. For example, the thickness of the sacrificial layer 20 is 50~100Å, such as any value in the range of 50~100Å, including 50Å, 70Å, 90Å or 100Å.

[0061] Please see Figure 10As shown, in step S3 of the present invention, after forming the sacrificial layer 20, the sacrificial layer 20 is subjected to high-energy ion sputtering treatment, so that the thickness of the sacrificial layer 20 at the corner between the sidewall structure 600 and the ion-doped region 300 is greater than its thickness in the vertical and horizontal directions. Therefore, the portion of the sacrificial layer 20 at the corner between the sidewall structure 600 and the ion-doped region 300 has a smooth arc shape, and the thickness of the sacrificial layer 20 in the remaining areas is reduced. For example, the bias power of the high-energy ion sputtering treatment is 1500~2000W, such as any value among 1500W, 1800W, or 2000W. Retaining a certain thickness of the sacrificial layer 20 on the surface of the substrate 10 can prevent damage to the surface of the substrate 10 during the high-energy ion sputtering treatment. The thickness of the sacrificial layer 20 after high-energy ion sputtering treatment is, for example, 5~10Å, such as any value among 5Å, 8Å, or 10Å. In high-energy ion sputtering, the gas used to generate high-energy ions can be an inert gas with a large molecular mass. During high-energy ion sputtering, when a gas with a large molecular mass is accelerated in an electric field and gains the same energy, it has greater momentum due to its larger mass. When these high-momentum ions bombard the target surface, they can more effectively transfer momentum to the target atoms, significantly improving the efficiency of material stripping and deposition per unit time. In this embodiment, the gas that generates high-energy ions is, for example, argon, and the direction of high-energy ion sputtering is, for example, perpendicular to the substrate 100 (e.g.,...). Figure 10 (As indicated by the arrow in the image). Vertically incident Ar... + Ions bombard the surface of the sacrificial layer 20 and sputter atoms out. Some of the sputtered atoms will re-deposit onto the surface of the substrate 10 after flying within the cavity. Since the corner between the sidewall structure 600 and the ion-doped region 300 is in a geometric shadow region, it is less directly bombarded by high-energy ions, resulting in less loss of the sacrificial layer 20. At the same time, it receives atoms sputtered and migrated from other strongly bombarded regions. Therefore, the thickness of the sacrificial layer 20 at the corner between the sidewall structure 600 and the ion-doped region 300 is greater than its thickness in the vertical and horizontal directions, forming a smooth arc shape.

[0062] Please see Figure 11As shown, in step S4 of this invention, after the sacrificial layer 20 is subjected to high-energy ion sputtering, an initial stress layer 30 is formed on the surface of the sacrificial layer 20. The initial stress layer 30 can be prepared by any one of the following processes: low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or high-density plasma-enhanced chemical vapor deposition. The material of the initial stress layer 30 is, for example, silicon nitride, and the nitrogen source for depositing the initial stress layer 30 is, for example, ammonia (NH3), and the silicon source is, for example, silane (SiH4). The initial stress layer 30 is formed, for example, by plasma-enhanced chemical vapor deposition. In order to avoid excessive stress difference between the subsequently formed stress layer 40 and the remaining sacrificial layer 20, resulting in poor bonding between them, the flow rate of the reactants used to form the initial stress layer 30 is linearly increased into the reaction chamber at a preset rate until the set flow rate is reached, so as to adjust the hydrogen content in the initial stress layer 30 and further adjust the stress of the subsequent stress layer 40. For example, the ammonia flow rate is increased from 0 to 1000 sccm over a period of 2-5 seconds, meaning the preset ammonia flow rate is 200-500 sccm / s, such as any value within the range of 200 sccm / s, 300 sccm / s, or 500 sccm / s. In this embodiment, the hydrogen content in the initial stress layer 30 is controlled by the ammonia flow rate. Silane can be directly introduced at a set flow rate, and the ratio of silane to ammonia can be adjusted according to actual conditions. This invention does not limit the thickness of the initial stress layer 30; it can be adjusted according to actual needs.

[0063] In the initial deposition of the initial stress layer 30, a low initial nitrogen source flow rate is set, and then the flow rate is increased linearly over time, which gradually increases the concentration of active nitrogen species (such as N atoms and NH radicals). Under a lower N / Si ratio, the film tends to form a silicon-rich SiN structure, which may contain more Si-H bonds. As the nitrogen source flow rate increases, the environment becomes more nitrogen-rich, and the film gradually approaches the stoichiometric ratio (Si3N4), at which point the proportion of NH bonds increases. Since the binding energy of NH bonds is generally lower than that of Si-H bonds, and the nitrogen-rich environment may change the growth mechanism and porosity of the film, the total bonded hydrogen (H) content in the film gradually accumulates and increases with the increase of the nitrogen source flow rate. When the nitrogen source flow rate increases to the set value and remains stable, the deposition environment reaches a new steady state, and the chemical composition (N / Si ratio, H content) in the initial stress layer 30 also stabilizes at a new level. Therefore, from the side in contact with the sacrificial layer 20 to the side away from the sacrificial layer 20, the hydrogen content of the initial stress layer 30 first increases linearly and finally reaches a stable distribution.

[0064] Please see Figure 12As shown, in step S5 of the present invention, after the initial stress layer 30 is formed, the initial stress layer 30 is cured to remove hydrogen atoms from the initial stress layer 30, forming a stress layer 40 and increasing the stress of the stress layer 40. For example, the initial stress layer 30 is cured by ultraviolet light irradiation. The curing temperature is, for example, 350~400℃, such as any value among 350℃, 370℃, or 400℃. The curing time is, for example, 90~150s, such as any value among 90s, 100s, 120s, 140s, or 150s. The curing time can be adjusted according to the thickness of the initial stress layer 30.

[0065] By performing high-energy ion sputtering on the sacrificial layer 20, the portion of the sacrificial layer 20 located at the corner between the sidewall structure 600 and the ion-doped region 300 becomes arc-shaped. The initial stress layer 30 can inherit the arc-shaped morphology of the sacrificial layer 20, fundamentally eliminating sharp corners and allowing the initial stress layer 30 to grow continuously and uniformly. Furthermore, this ensures that the inherent intrinsic stress of the stress layer 40 is smoothly distributed along the curved surface, preventing the generation of local stress peaks. Eliminating stress concentration in the stress layer 40 significantly improves its mechanical integrity, effectively reducing the risk of cracking or delamination. Simultaneously, it ensures that the stress proximity effect can be uniformly and controllably transferred to the active region of the device, thereby improving transistor performance while guaranteeing the reliability of the device in subsequent processes and long-term operation. In this invention, the stress layer 40 can serve as a contact etch stop layer (CESL) during subsequent semiconductor structure fabrication processes. During contact hole formation, the region of the stress layer 40 located at the bottom of the contact hole is removed, while the remaining region is retained. The sacrificial layer 20 below the stress layer 40 is identical to the stress layer 40; that is, the position of the contact hole corresponding to the sacrificial layer 20 is removed, while the remaining region is retained. The sacrificial layer 20 of this invention is easily removed during contact hole formation and does not affect subsequent processes.

[0066] Please see Figure 13 As shown, Figure 13 The graph shows the relationship between the thickness of stress layer 40 and the hydrogen content and stress. The horizontal axis represents the thickness of the initial stress layer 30, which is also the thickness of stress layer 40. The left vertical axis represents the hydrogen content in the initial stress layer 30, and the right vertical axis represents the stress in stress layer 40. Figure 13As can be seen, when the initial stress layer 30 is formed, the nitrogen source is introduced in a linearly increasing manner up to a set flow rate. As the thickness of the initial stress layer 30 increases, the hydrogen content in the initial stress layer 30 shows a trend of first increasing linearly and then stabilizing. Correspondingly, the curing process can remove hydrogen atoms from the initial stress layer 30, and silicon atoms combine with nitrogen atoms to form Si-N bonds. As the number of Si-N bonds increases, the stress of the stress layer 40 gradually increases. Therefore, the stress of the stress layer 40 corresponds to the hydrogen content in the initial stress layer 30; that is, the higher the hydrogen content in the initial stress layer 30, the greater the stress of the stress layer 40 formed after curing. Thus, as the thickness of the stress layer 40 increases, the stress of the stress layer 40 also shows a trend of first increasing linearly and then stabilizing. That is, from the side of the stress layer 40 that contacts the sacrificial layer 20 to the side of the stress layer 40 that is away from the sacrificial layer 20, the stress of the stress layer 40 gradually increases and then tends to stabilize, which can avoid the problem of poor bonding caused by excessive stress difference at the interface between the stress layer 40 and the sacrificial layer 20.

[0067] This invention also provides a semiconductor structure fabricated using the above-described preparation method. Please refer to [link / reference]. Figure 12 As shown, the semiconductor structure of the present invention includes a substrate 10, a sacrificial layer 20, and a stress layer 40. The sacrificial layer 20 is formed on the surface of the substrate 10, and the stress layer 40 is formed on the surface of the sacrificial layer 20. The substrate 10 includes a substrate 100, a gate structure 200 formed on the substrate 100, and ion-doped regions 300 located on both sides of the gate structure 200 within the substrate 100. The sacrificial layer 20 covers the gate structure 200 and the ion-doped regions 300, and the portion of the sacrificial layer 20 located at the corner between the gate structure 200 and the ion-doped region 300 is arc-shaped, which can effectively eliminate stress concentration points in the stress layer 40 and reduce the risk of cracking of the stress layer 40. It should be noted that, based on this structure, the semiconductor structure may also include other structures.

[0068] In summary, the semiconductor structure fabrication method proposed in this invention involves depositing a sacrificial layer and performing high-energy ion sputtering treatment on it, followed by depositing an initial stress layer on the surface of the high-energy ion sputtered sacrificial layer, and then curing the initial stress layer to form a stress layer. An unexpected benefit of this application is that by performing high-energy ion sputtering treatment on the sacrificial layer, the portion of the sacrificial layer located at the corner between the gate structure and the ion-doped region can be made arc-shaped. The subsequently formed stress layer inherits this arc-shaped morphology, thereby effectively eliminating stress concentration points. Even with a large stress layer thickness, this method can effectively reduce the generation of stress layer cracks with only a single deposition / curing step. Furthermore, compared to traditional processes requiring multiple deposition / curing cycles, this approach can not only increase wafer throughput by 50%~60% per hour but also avoid the thermal budget accumulation problem caused by multiple heat treatments, which is beneficial for maintaining device thermal stability and process controllability.

[0069] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a substrate, a gate structure formed on the substrate, sidewall structures located on both sides of the gate structure, and ion-doped regions located in the substrate on both sides of the gate structure; A sacrificial layer is formed on the surface of the substrate; The sacrificial layer is subjected to high-energy ion sputtering treatment, so that the portion of the sacrificial layer located at the corner between the sidewall structure and the ion-doped region is rounded, and the thickness of the sacrificial layer in the remaining area is reduced; An initial stress layer is formed on the surface of the sacrificial layer; The initial stress layer is cured to form a stress layer.

2. The preparation method according to claim 1, characterized in that, Before the sacrificial layer is subjected to high-energy ion sputtering, the thickness of the sacrificial layer is 50~100 Å.

3. The preparation method according to claim 1, characterized in that, The bias power during the high-energy ion sputtering process is 1500~2000W.

4. The preparation method according to claim 1, characterized in that, The initial stress layer is cured by ultraviolet light irradiation at a temperature of 350-400°C for a time of 90-150 seconds.

5. The preparation method according to claim 1, characterized in that, After the sacrificial layer is subjected to high-energy ion sputtering, the thickness of the sacrificial layer is 5~10 Å.

6. The preparation method according to claim 1, characterized in that, The initial stress layer is formed by chemical vapor deposition, and the material of the initial stress layer is silicon nitride.

7. The preparation method according to claim 1, characterized in that, When the initial stress layer is formed, the flow rate of the reactants increases linearly at a preset rate to the set flow rate.

8. The preparation method according to claim 7, characterized in that, The preset rate is 200~500 sccm / s.

9. The preparation method according to claim 1, characterized in that, The substrate further includes a trench isolation structure located within the substrate on the side of the ion-doped region opposite to the gate structure.

10. A semiconductor structure, characterized in that, It is prepared using the preparation method according to any one of claims 1 to 9.

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