A trench type double gate power MOS structure implementation method
By employing a double-layer gate structure and a gradient electric field buffer dielectric in trench power MOSFET devices, the problems of large gate-drain capacitance and electric field concentration are solved, the breakdown voltage and switching frequency are improved, the manufacturing process is simplified, and the device reliability and yield are enhanced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI LEWA MICROELECTRONICS TECHNOLOGY CO LTD
- Filing Date
- 2026-03-25
- Publication Date
- 2026-06-19
AI Technical Summary
In pursuit of high switching speed and high breakdown voltage, existing trench power MOSFET devices suffer from large gate-drain charge and output capacitance. Furthermore, there is a mutual constraint between the device's breakdown voltage and on-resistance. Traditional manufacturing processes are complex and prone to introducing process damage.
A trench-type double-layer gate structure is adopted. By forming a shielded gate electrode on a silicon substrate, and using a self-aligned composite sidewall structure and multi-stage in-situ oxidation to form a gradient electric field buffer inter-gate dielectric, including a combination of silicon oxynitride layer and silicon dioxide layer, the direct oxidation of the single crystal silicon at the bottom of the trench is avoided, simplifying the process flow.
It reduces gate-drain capacitance, optimizes electric field distribution, improves breakdown voltage and switching frequency, simplifies manufacturing process, and improves device structural accuracy and production yield.
Smart Images
Figure CN121968643B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device manufacturing technology, specifically to a method for implementing a trench-type double-gate power MOS structure. Background Technology
[0002] Currently, power metal-oxide-semiconductor field-effect transistors (MOSFETs) are core components of power electronic systems. Trench gate structures play a crucial role due to their low on-resistance and high channel density. With the increasing demands for power conversion efficiency and switching frequency in fields such as power management and new energy vehicles, optimizing key performance characteristics of power MOSFETs, such as breakdown voltage, on-resistance, and switching speed, has become a continuous driving force for technological development.
[0003] Regarding the aforementioned issues, a common technical solution is the shielded gate trench MOSFET. Its implementation typically includes the following steps: First, a trench is etched onto the epitaxial layer. Next, a gate oxide layer is grown within the trench. Then, a first layer of polysilicon is deposited and etched back to form the shielded gate electrode. Afterward, an inter-gate dielectric layer is deposited to isolate the shielded gate. Finally, a second layer of polysilicon is deposited and patterned to form the control gate.
[0004] Existing structures still face limitations in performance and manufacturing processes, with the electric field concentration at the bottom of the trench being particularly prominent. This directly restricts the improvement of device breakdown voltage. To alleviate the electric field, on-resistance often needs to be sacrificed, creating an inherent performance contradiction. In addition, the large gate-drain capacitance in traditional single-gate structures has also become a bottleneck limiting device switching speed and operating frequency. The shielded gate structure introduced to solve these problems introduces new challenges in its manufacturing process. The process flow is usually more complex, and the difficulty of multiple photolithography alignments increases manufacturing uncertainty. More seriously, some processes involve direct thermal oxidation of single-crystal silicon at the bottom of the trench, which can easily introduce process damage, thus affecting the long-term reliability and production yield of the device.
[0005] Therefore, the present invention provides a method for implementing a trench-type double-gate power MOS structure to overcome the shortcomings of the prior art. Summary of the Invention
[0006] To address the shortcomings of existing technologies, this invention provides a method for implementing a trench-type double-gate power MOSFET structure. This method solves the problem that existing trench-type power MOSFET devices, while pursuing high switching speed and high breakdown voltage, have large gate-drain charges and output capacitances, and that there is a mutual constraint between the device's breakdown voltage and specific on-resistance.
[0007] To achieve the above objectives, the present invention provides a method for implementing a trench-type double-gate power MOS structure, comprising the following steps:
[0008] S1. An epitaxial layer is grown on a silicon substrate, a main trench is formed on the epitaxial layer by an etching process, and a shielding gate electrode is formed in the bottom region of the main trench.
[0009] S2. On the epitaxial layer and inside the main trench, a polysilicon layer to be converted, a silicon nitride sacrificial layer and a hard mask layer are deposited in a conformal manner.
[0010] S3. Perform anisotropic dry etching on the deposited polysilicon layer to be converted, silicon nitride sacrificial layer and hard mask layer to form a self-aligned composite sidewall structure along the sidewall of the main trench, and expose the polysilicon layer to be converted at the bottom of the main trench.
[0011] S4. Perform multi-stage in-situ oxidation on the polysilicon layer to be converted at the bottom of the exposed main trench, transforming it into an inter-gate dielectric with gradient electric field buffering characteristics. The inter-gate dielectric has a layered structure, with a silicon oxynitride layer at the bottom and a silicon dioxide layer on top. This step is one of the core components of this technical solution. By oxidizing the pre-deposited polysilicon layer in situ, rather than directly oxidizing the single-crystal silicon at the bottom of the trench, process damage to the bottom region of the trench is avoided. The resulting inter-gate dielectric with a gradient dielectric constant can effectively modulate the electric field at the bottom of the trench. According to Gauss's law in dielectrics, at the interface between two dielectrics, if there are no free charges, the normal component of the electric displacement vector is continuous, i.e. ,that is .in, It is the electric displacement vector. Where is the dielectric constant. The electric field strength is given. The silicon oxynitride layer is designated as the first dielectric, and the silicon dioxide layer as the second dielectric. Due to the dielectric constant of the silicon oxynitride layer... The dielectric constant is higher than that of the silicon dioxide layer. ,Right now Therefore, the electric field strength in the silicon oxynitride layer The electric field strength will be less than that in the silicon dioxide layer. This structure shifts the high electric field region from the interface immediately adjacent to the bottom of the trench to the interior of the silicon dioxide layer with a lower dielectric constant, reducing the peak electric field intensity in the monocrystalline silicon region at the bottom of the trench, thereby improving the breakdown voltage of the device.
[0012] S5. Selectively remove the silicon nitride sacrificial layer to expose the silicon sidewalls above the main trench.
[0013] S6. A control gate oxide is grown on the exposed silicon sidewall of the main trench, and then the control gate polysilicon is deposited and etched back or planarized to form a control gate that fills the main trench.
[0014] S7, and subsequent device manufacturing processes, including source and body region formation, interlayer dielectric deposition, contact hole etching, and metallization.
[0015] In one specific embodiment, step S1, forming a shielding gate electrode in the bottom region of the main trench, specifically includes: implanting an N-type dopant, such as phosphorus or arsenic, into the silicon substrate in the bottom region of the main trench by ion implantation to form a heavily doped conductive region as the shielding gate electrode.
[0016] Preferably, in step S2, the polycrystalline silicon layer to be converted is formed by low-pressure chemical vapor deposition to obtain excellent shape retention and thickness uniformity.
[0017] In one specific embodiment, in step S3, the anisotropic dry etching is achieved using reactive ion etching or inductively coupled plasma reactive ion etching to ensure the verticality of the etching and the precise formation of the sidewall structure.
[0018] In one specific embodiment, step S4, the multi-stage in-situ oxidation specifically includes:
[0019] In the first stage, oxidation is carried out at high temperature in an atmosphere rich in nitrogen and with controlled oxygen partial pressure, so that a silicon oxynitride layer is formed on the surface of the polycrystalline silicon layer to be converted.
[0020] In the second stage, oxidation is carried out at high temperature in a pure oxygen or water vapor-rich atmosphere to completely convert the remaining polycrystalline silicon layer to be converted into a silicon dioxide layer.
[0021] In the third stage, high-temperature annealing is performed to passivate defects at the interface between the gate dielectric and the interface, thereby reducing the interface state density.
[0022] As a technical feature of the foregoing embodiments, the dielectric constant of the silicon oxynitride layer formed in the first stage is higher than that of the silicon dioxide layer formed in the second stage, which is the basis for realizing the inter-gate dielectric gradient electric field buffering function.
[0023] Preferably, in step S5, the selective removal of the silicon nitride sacrificial layer is performed using a hot phosphoric acid wet etching method, which has a high selectivity for silicon dioxide and silicon.
[0024] In one specific embodiment, in step S6, the control gate oxide is grown by thermal oxidation or atomic layer deposition to form a high-quality gate oxide layer.
[0025] In one specific embodiment, in step S6, the deposited control gate polysilicon is formed by low-pressure chemical vapor deposition, and the planarization is achieved by chemical mechanical polishing to obtain a flat surface morphology.
[0026] Furthermore, in step S7, the subsequent device manufacturing process specifically includes: forming a P-type body region and an N+ type source region by ion implantation on the surface region of the epitaxial layer, depositing interlayer dielectric and etching to form contact holes, and depositing a metal layer by physical vapor deposition and etching to form source, gate and drain electrode leads.
[0027] This invention provides a method for implementing a trench-type double-gate power MOS structure. It has the following advantages:
[0028] 1. This invention solves the problem of large gate-drain capacitance in existing power MOSFETs by forming a shielded gate electrode at the bottom of the trench and isolating it from the control gate using a gate dielectric formed by a self-aligned process. This achieves the technical effect of reducing gate-drain charge and output capacitance, thereby reducing switching losses and increasing the operating frequency of the device.
[0029] 2. This invention solves the problem of electric field concentration at the bottom of the trench in traditional structures by performing multi-stage in-situ oxidation on a pre-deposited polycrystalline silicon layer to form a gradient inter-gate dielectric with a high-dielectric-constant silicon oxynitride layer at the bottom and a low-dielectric-constant silicon dioxide layer at the top. This achieves the technical effects of optimizing the electric field distribution, improving the device breakdown voltage, and improving the constraint relationship between breakdown voltage and on-resistance.
[0030] 3. This invention uses a self-aligned composite sidewall structure to precisely define the formation areas of the inter-gate dielectric and the control gate, and uses in-situ oxidation of the polysilicon layer to be converted to form the inter-gate dielectric. This solves the problems of complex traditional dual-gate process flow, difficulty in multiple photolithography alignments, and easy introduction of process damage at the bottom of the trench. It achieves the technical effects of simplifying the manufacturing process, improving the accuracy and reliability of device structure, and improving production yield. Attached Figure Description
[0031] Figure 1 This is a schematic diagram of the process flow for realizing the trench-type double-gate power MOS structure of the present invention;
[0032] Figure 2 This is a cross-sectional schematic diagram of the trench-type double-gate power MOS structure of the present invention after completing step S1;
[0033] Figure 3 This is a cross-sectional schematic diagram of the trench-type double-gate power MOS structure of the present invention after completing step S2;
[0034] Figure 4 This is a cross-sectional schematic diagram of the trench-type double-gate power MOS structure of the present invention after completing step S3;
[0035] Figure 5 This is a cross-sectional schematic diagram of the trench-type double-gate power MOS structure of the present invention after completing step S4;
[0036] Figure 6 This is a cross-sectional schematic diagram of the trench-type double-gate power MOS structure of the present invention after completing step S5;
[0037] Figure 7 This is a cross-sectional schematic diagram of the trench-type double-gate power MOS structure of the present invention after completing step S6;
[0038] Figure 8 This is a cross-sectional schematic diagram of the trench-type double-gate power MOS structure of the present invention after completing step S7.
[0039] Among them, 1. main trench; 2. shielding gate electrode; 3. epitaxial layer; 4. silicon substrate; 5. silicon nitride sacrificial layer; 6. polysilicon layer; 7. hard mask layer; 8. silicon dioxide layer; 9. inter-gate dielectric; 10. silicon oxynitride layer; 11. control gate polysilicon; 12. metal layer; 13. inter-layer dielectric; 14. source region; 15. body region. Detailed Implementation
[0040] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0041] Please see the appendix Figure 1 , Figure 1 This is a schematic diagram of the process flow for implementing a trench-type double-gate power MOS structure according to an embodiment of the present invention. The embodiment of the present invention provides a method for implementing a trench-type double-gate power MOS structure, including the following steps:
[0042] Step S1: An epitaxial layer 3 is grown on a silicon substrate 4, a main trench 1 is etched on the epitaxial layer 3, and a shielding gate electrode 2 is formed in the bottom region of the main trench 1.
[0043] Step S2: On the epitaxial layer 3 and inside the main trench 1, the polysilicon layer 6 to be converted, the silicon nitride sacrificial layer 5 and the hard mask layer 7 are deposited in a conformal manner.
[0044] Step S3: Anisotropic dry etching is performed on the deposited polysilicon layer 6 to be converted, silicon nitride sacrificial layer 5 and hard mask layer 7 to form a self-aligned composite sidewall structure along the sidewall of the main trench 1 and expose the polysilicon layer 6 to be converted at the bottom of the main trench 1.
[0045] Step S4: Perform multi-stage in-situ oxidation on the polysilicon layer 6 to be converted at the bottom of the exposed main trench 1 to convert it into an inter-gate dielectric 9 with gradient electric field buffering characteristics. The bottom of the inter-gate dielectric 9 is a silicon oxynitride layer 10, and the top of the inter-gate dielectric 9 is a silicon dioxide layer 8.
[0046] Step S5: Selectively remove the silicon nitride sacrificial layer 5 to expose the silicon sidewalls on the upper part of the main trench 1;
[0047] Step S6: Growing control gate oxide on the exposed silicon sidewalls of the main trench 1, and then depositing and etching back or planarizing control gate polysilicon 11 to form a control gate filling the main trench 1.
[0048] Step S7, and subsequent device manufacturing processes, including the formation of source region 14 and body region 15, deposition of interlayer dielectric 13, contact hole etching and metallization.
[0049] A core aspect of this technical solution is that a self-aligned composite sidewall structure is formed on the sidewall of the main trench 1 through the three-layer composite film deposited in step S2 and the anisotropic etching in step S3. This structure not only precisely defines the area for the subsequent control gate formation, but also serves as a mask, so that the polysilicon layer 6 to be converted at the bottom of the main trench 1 is precisely exposed.
[0050] Based on this structure, in step S4, the exposed polysilicon layer 6 to be converted undergoes multi-stage in-situ oxidation to form the inter-gate dielectric 9. This method avoids direct high-temperature oxidation of the single-crystal silicon epitaxial layer 3 at the bottom of the main trench 1, thereby reducing process damage and stress defects introduced in the critical trench corner region. The resulting inter-gate dielectric 9 with gradient electric field buffering characteristics is based on the physical principle that, according to Gauss's law in dielectrics, at the interface between two dielectrics, if there are no free charges, the normal component of the electric displacement vector is continuous, i.e. ,that is .in, It is the electric displacement vector. Where is the dielectric constant. The electric field strength is given. The silicon oxynitride layer 10 is designated as the first dielectric, and the silicon dioxide layer 8 as the second dielectric. Due to the dielectric constant of the silicon oxynitride layer 10... The dielectric constant is higher than that of silicon dioxide layer 8. ,Right now Therefore, the electric field strength E1 in the silicon oxynitride layer 10 will be less than the electric field strength in the silicon dioxide layer 8. This structure shifts the high electric field region from the interface adjacent to the bottom of the trench to the interior of the silicon dioxide layer 8, which has a lower dielectric constant, thereby reducing the peak electric field intensity in the monocrystalline silicon region at the bottom of the trench and thus improving the breakdown voltage of the device.
[0051] After the gradient gate dielectric 9 is formed, the silicon nitride sacrificial layer 5 is selectively removed in step S5 to expose the silicon sidewalls on the upper part of the main trench 1, providing a precise process window for the subsequent growth of the control gate oxide and the formation of the control gate. Finally, the fabrication of the entire double-gate power MOS device is completed through steps S6 and S7.
[0052] See attached document Figure 2 , Figure 2 This is a cross-sectional schematic diagram of a trench-type double-gate power MOS structure after completing step S1, according to an embodiment of the present invention.
[0053] Step S1 of the method of the present invention, the formation of the main trench 1 and the preparation of the shielding gate electrode 2, specifically includes the following operations.
[0054] First, an N+ type heavily doped silicon substrate 4 is provided. An N- type lightly doped silicon epitaxial layer 3 is grown on the silicon substrate 4 by chemical vapor deposition (CVD). The resistivity and thickness of the epitaxial layer 3 are set according to the breakdown voltage requirements of the final device.
[0055] Next, the main trench 1 is formed on the surface of the epitaxial layer 3 by photolithography and etching processes. This process includes: depositing a hard mask material, such as silicon dioxide layer 8 or silicon nitride, on the upper surface of the epitaxial layer 3; coating photoresist on the hard mask layer 7 and exposing and developing it to form a preset trench pattern on the photoresist; using the patterned photoresist as a mask, transferring the pattern to the underlying hard mask layer 7 by dry etching; after removing the remaining photoresist, using the patterned hard mask layer 7 as a mask, using anisotropic dry etching techniques such as reactive ion etching (RIE) to etch the main trench 1 with vertical sidewalls in the epitaxial layer 3, the depth of the main trench 1 extending through the junction depth of the body region 15 to be formed subsequently.
[0056] After the main trench 1 is formed, a shielding gate electrode 2 is formed at the bottom region of the main trench 1. Specifically, this step involves implanting an N-type dopant, such as phosphorus or arsenic ions, into the epitaxial layer 3 region at the bottom of the main trench 1 using ion implantation at a set implantation energy and dose. The implantation dose is set to a high dose to form a heavily doped N+ conductive region in the implanted area. After ion implantation, a high-temperature annealing process is performed to repair lattice damage caused during ion implantation and to electrically activate the implanted dopant atoms in the lattice, thereby forming a low-resistivity conductive region that serves as the shielding gate electrode 2.
[0057] See attached document Figure 3 , Figure 3 This is a cross-sectional schematic diagram of a trench-type double-gate power MOS structure after completing step S2, according to an embodiment of the present invention.
[0058] After completing step S1, step S2 of the method of the present invention is the conformal deposition of the composite functional film, which specifically includes the sequential deposition of three different functional films.
[0059] Specifically, on the structure formed in step S1, a polysilicon layer 6 to be converted is first deposited. This layer is formed using a low-pressure chemical vapor deposition (LPCVD) process. Low pressure refers to a reaction environment significantly lower than standard atmospheric pressure, typically ranging from 10 mTorr to 10 Torr. This low-pressure environment increases the mean free path of the reactant gas molecules, thereby improving the uniformity and conformality of the film deposition. In this process, silane is used as the reactant gas in a low-pressure environment, undergoing thermal decomposition within a specific temperature range (e.g., 600-650°C) to deposit a polysilicon layer 6 on all exposed surfaces. The characteristics of the LPCVD process ensure high conformality, guaranteeing that the deposited polysilicon layer 6 can cover the vertical sidewalls of the main trench 1, the trench bottom, and the upper surface of the epitaxial layer 3 with a uniform thickness. The thickness of this polysilicon layer 6 is a pre-set value based on device design parameters, which directly determines the final thickness of the gate dielectric 9 formed in subsequent steps.
[0060] On the polysilicon layer 6 to be converted, a silicon nitride sacrificial layer 5 is then conformally deposited. This layer is also formed using an LPCVD process, with dichlorosilane and ammonia as the reaction source gases. The deposited silicon nitride sacrificial layer 5 is dense and uniform. This silicon nitride sacrificial layer 5 is used as a sacrificial layer in subsequent process steps, and its thickness is precisely controlled to determine the lateral spacing between the subsequently formed inter-gate dielectric 9 and the control gate oxide.
[0061] Finally, a hard mask layer 7 is deposited on the silicon nitride sacrificial layer 5. This hard mask layer 7 can be a silicon dioxide layer 8. The silicon dioxide layer 8 can be formed by methods such as plasma-enhanced chemical vapor deposition (PECVD). In the subsequent step S3, this hard mask layer 7 serves as the main masking layer in the anisotropic dry etching process. The selection of its material and thickness must ensure a high etching selectivity for the underlying silicon nitride sacrificial layer 5 and the polysilicon layer 6 to be converted.
[0062] See attached document Figure 4 , Figure 4 This is a cross-sectional schematic diagram of a trench-type double-gate power MOS structure after completing step S3, according to an embodiment of the present invention.
[0063] After completing the conformal deposition of the three functional thin films in step S2, step S3 of the present invention, the formation of the self-aligned composite sidewall structure, specifically includes performing an overall anisotropic dry etching on the deposited polysilicon layer 6 to be converted, silicon nitride sacrificial layer 5 and hard mask layer 7.
[0064] In one specific embodiment, anisotropic dry etching is achieved using reactive ion etching (RIE) or inductively coupled plasma reactive ion etching (ICP-RIE). This process introduces a specific reactive gas to form plasma and uses an electric field to accelerate the ions in the plasma, causing them to bombard the wafer surface in a vertical direction, thereby achieving an anisotropic effect where the vertical etching rate is much greater than the lateral etching rate.
[0065] This anisotropic dry etching is an etch-back process that removes the three-layer composite film from all horizontal surfaces, including the film on the upper surface of epitaxial layer 3 and the film at the bottom of the main trench 1. Due to the high anisotropy of the etching, most of the three-layer composite film deposited on the vertical sidewalls of the main trench 1 is retained, thus forming a self-aligned composite sidewall structure on both sidewalls of the main trench 1, consisting of a polysilicon layer 6 to be converted, a silicon nitride sacrificial layer 5, and a hard mask layer 7. The self-aligned composite sidewall structure refers to a mask structure composed of multiple layers of different materials that spontaneously forms on the sidewalls without the need for additional photolithography masks for alignment. It utilizes the existing three-dimensional morphology of the main trench 1, combined with conformal deposition of the film and anisotropic etching processes.
[0066] The etching process is precisely controlled, stopping once the hard mask layer 7 and the silicon nitride sacrificial layer 5 at the bottom of the main trench 1 are completely removed. This operation precisely exposes the upper surface of the polysilicon layer 6 to be converted at the bottom of the main trench 1, preparing it for subsequent multi-stage in-situ oxidation in step S4. This self-aligned process eliminates the need for additional photolithography steps to define the sidewall structure, simplifying the process flow and improving the dimensional accuracy of the device structure.
[0067] See attached document Figure 5 , Figure 5 This is a cross-sectional schematic diagram of a trench-type double-gate power MOS structure after completing step S4, according to an embodiment of the present invention.
[0068] After forming a self-aligned composite sidewall structure and exposing the polysilicon layer 6 to be converted at the bottom of the main trench 1, step S4 of the method of the present invention, multi-stage in-situ oxidation of the gradient inter-gate dielectric 9, specifically includes a multi-stage, controlled thermal oxidation process on the exposed polysilicon layer 6 to be converted, completely converting it into a layered inter-gate dielectric 9 with gradient dielectric constant characteristics.
[0069] In one specific embodiment, the multi-stage in-situ oxidation includes the following three consecutive stages:
[0070] In the first stage, heat treatment is performed under high-temperature conditions in a nitrogen-rich atmosphere with controlled oxygen partial pressure. Here, "high temperature" refers to the temperature range capable of inducing chemical reactions such as thermal oxidation or repairing lattice defects; in semiconductor processes, this is typically set between 800°C and 1200°C. In this atmosphere, nitrogen species react with the surface of the polycrystalline silicon layer 6 to be converted, forming a dense silicon oxynitride layer 10. The process parameters for this stage, including temperature, reaction time, and oxygen partial pressure, are precisely controlled to determine the final thickness and nitrogen concentration of the formed silicon oxynitride layer 10.
[0071] In the second stage, after completing the first stage, the process environment is switched to a high-temperature, pure oxygen, or water vapor-rich atmosphere. In this oxidizing environment, the remaining polycrystalline silicon layer 6 to be converted, located below the newly formed silicon oxynitride layer 10, is completely oxidized and transformed into a silicon dioxide layer 8.
[0072] Through the above two stages, the original polysilicon layer 6 to be converted is completely and in situ converted from bottom to top into a double-layer dielectric structure, which is the gate dielectric 9 of the present invention. The bottom of the gate dielectric 9 is the silicon oxynitride layer 10 formed in the first stage, and the top is the silicon dioxide layer 8 formed in the second stage.
[0073] The third stage involves high-temperature annealing. After the oxidation process is complete, the entire structure is annealed at high temperature in an inert gas atmosphere (such as nitrogen or argon). This step is used to passivate the bulk defects of the inter-gate dielectric 9 and the interface defects between the inter-gate dielectric 9 and the bottom silicon epitaxial layer 3 of the main trench 1, thereby reducing the interface state density and improving the electrical quality and reliability of the dielectric layer.
[0074] The dielectric constant of the silicon oxynitride layer 10 formed in the first stage is higher than that of the silicon dioxide layer 8 formed in the second stage. This gradient distribution of dielectric constant allows the inter-gate dielectric 9 to modulate the electric field at the bottom of the main trench 1. According to Gauss's law, at the interface between the silicon oxynitride layer 10 and the silicon dioxide layer 8, the normal component of the electric displacement vector is continuous, i.e. ,that is .in, It is the electric displacement vector. Where is the dielectric constant. The electric field strength is given. The silicon oxynitride layer 10 is designated as dielectric 1, and the silicon dioxide layer 8 as dielectric 2. Due to the dielectric constant of the silicon oxynitride layer 10... The dielectric constant is higher than that of silicon dioxide layer 8. ,Right now Therefore, the electric field strength in the silicon oxynitride layer 10 The electric field strength will be less than that in the silicon dioxide layer 8. This structure shifts the high electric field region from the interface adjacent to the bottom of the trench to the interior of the silicon dioxide layer 8, which has a lower dielectric constant, thereby reducing the peak electric field intensity in the monocrystalline silicon region at the bottom of the trench and thus improving the breakdown voltage of the device.
[0075] See attached document Figure 6 , Figure 6 This is a cross-sectional schematic diagram of a trench-type double-gate power MOS structure after completing step S5, according to an embodiment of the present invention.
[0076] After the gradient intergate dielectric 9 is formed in step S4, step S5 of the method of the present invention, selective removal of silicon nitride sacrificial layer 5, specifically includes wet etching of silicon nitride sacrificial layer 5 in composite sidewall structure.
[0077] In one specific embodiment, the selective removal process employs a hot phosphoric acid wet etching method. This process involves immersing the wafer with the device structure into a concentrated phosphoric acid solution with the temperature maintained within a specific range (e.g., 150°C to 180°C).
[0078] The principle behind this method is that hot phosphoric acid has a high etching rate for the silicon nitride sacrificial layer 5, while its etching rate for the silicon dioxide layer 8 and single-crystal silicon is extremely low. This high etching selectivity ensures that while the silicon nitride sacrificial layer 5 is completely removed, the inter-gate dielectric 9 formed in step S4 at the bottom of the main trench 1 and the hard mask layer 7 located outside the composite sidewall structure are not substantially eroded, and their structure and thickness are maintained.
[0079] This etching process completely removes the silicon nitride sacrificial layer 5 on the sidewalls of the main trench 1. The final result of this operation is the exposure of the monocrystalline silicon sidewalls on the upper part of the main trench 1, which were previously covered by the composite sidewall structure. The exposed monocrystalline silicon sidewall surface is clean and undamaged, providing a process interface for the high-quality control gate oxide growth in the subsequent step S6.
[0080] See attached document Figure 7 , Figure 7 This is a cross-sectional schematic diagram of a trench-type double-gate power MOS structure after completing step S6, according to an embodiment of the present invention.
[0081] After selectively removing the silicon nitride sacrificial layer 5 in step S5, step S6 of the method of the present invention, the formation of the control gate, specifically includes two consecutive processes: growing the control gate oxide and depositing and planarizing polysilicon.
[0082] First, a high-quality control gate oxide layer is grown on the silicon sidewall of the main trench 1 exposed in step S5. Here, the gate oxide layer is an insulating dielectric film between the control gate material and the semiconductor silicon sidewall. It primarily serves to achieve complete electrical isolation between the control gate and the semiconductor channel, and acts as a dielectric to transmit the gate piezoelectric field to control the device's operation. In one specific embodiment, the control gate oxide is grown via thermal oxidation, where the wafer is placed in a high-temperature (e.g., 900°C to 1100°C) oxidation furnace, and in an atmosphere of pure oxygen or water vapor, the single-crystal silicon on the silicon sidewall surface reacts with an oxidant to directly grow a dense silicon dioxide layer 8. In another embodiment, the control gate oxide is grown via atomic layer deposition (ALD), a process that involves alternately introducing different precursor gases to perform a self-limiting chemical reaction on the silicon sidewall surface, depositing an insulating dielectric layer, such as silicon dioxide layer 8 or a high-dielectric-constant material, atomically layer by atomic.
[0083] After the control gate oxide is formed, the control gate polysilicon 11 is deposited and planarized. In one embodiment, a layer of control gate polysilicon 11 is deposited on the upper surface of the entire device structure using a low-pressure chemical vapor deposition (LPCVD) process. This control gate polysilicon 11 completely fills the remaining space defined by the control gate oxide within the main trench 1 and covers the upper surface of the composite sidewall structure and the epitaxial layer 3. To make it conductive, the control gate polysilicon 11 can be in-situ doped during the deposition process.
[0084] After deposition, the control gate polysilicon 11 is planarized using a chemical mechanical polishing (CMP) process. The CMP process removes excess control gate polysilicon 11 from the upper surface of the epitaxial layer 3 and above the composite sidewall structure through the synergistic effect of chemical etching and mechanical polishing, until the upper surface of the hard mask layer 7 is exposed, thus ensuring that the control gate polysilicon 11 remains only inside the main trench 1. This step ultimately forms a control gate encapsulated by gate oxide and filling the upper part of the main trench 1.
[0085] See attached document Figure 8 , Figure 8 This is a schematic cross-sectional view of a trench-type double-gate power MOS structure after step S7 is completed, according to an embodiment of the present invention.
[0086] After the control gate is formed in step S6, step S7 of the present invention implements the device manufacturing process, which specifically includes a series of back-end processes such as forming source region 14 and body region 15, depositing interlayer dielectric 13, etching contact holes, and metallization.
[0087] In one specific embodiment, the subsequent device manufacturing process specifically includes:
[0088] (1) Ion implantation is performed on the surface region of epitaxial layer 3 to form a P-type body region 15 and an N+ type source region 14. This process uses the control gate and composite sidewall structure in the main trench 1 as a self-aligned mask. First, a P-type dopant (e.g., boron ions) is implanted to form the P-type body region 15. Subsequently, under the same mask, an N-type dopant (e.g., arsenic or phosphorus ions) is implanted at a higher dose to form a shallower N+ type source region 14 within the P-type body region 15. After implantation, a rapid thermal annealing (RTA) process is performed to electrically activate the implanted dopant and repair lattice damage.
[0089] (2) An interlayer dielectric 13 is deposited on the upper surface of the entire device structure. The interlayer dielectric 13 is an insulating layer, such as boron-phosphorus-doped silicate glass (BPSG), which can be formed by plasma-enhanced chemical vapor deposition (PECVD). After deposition, the interlayer dielectric 13 is subjected to a thermal leveling treatment or chemical mechanical polishing to obtain a flat surface, providing a basis for subsequent metallization processes.
[0090] (3) Etching to form contact holes. The pattern of contact holes is formed on the upper surface of the interlayer medium 13 by standard photolithography process, and anisotropic dry etching is used to penetrate the interlayer medium 13 until the upper surface of the N+ type source region 14 and the control gate is exposed.
[0091] (4) Metallization. One or more metal layers 12 are deposited on the entire device surface by means of physical vapor deposition (PVD) or similar methods. In one embodiment, the metal layer 12 can be titanium / titanium nitride as a barrier layer and an adhesion layer, and aluminum or copper as the main conductive layer. After deposition, the metal layer 12 is patterned by another photolithography and etching process to form the source electrode connected to the N+ type source region 14 and the gate electrode connected to the control gate. Finally, the back side of the silicon substrate 4 is thinned and the metal layer 12 is deposited to form the drain electrode.
[0092] This invention provides a method for implementing a trench-type double-gate power MOS structure. The following will describe the aforementioned process steps in series through a specific, non-limiting embodiment.
[0093] First, an N+ heavily doped silicon substrate 4 is provided, and an N- lightly doped epitaxial layer 3 is grown on the silicon substrate 4 using chemical vapor deposition. Then, a main trench 1 is formed on the epitaxial layer 3 using photolithography and reactive ion etching. After the main trench 1 is formed, N-type dopant is implanted into the epitaxial layer 3 region at the bottom of the main trench 1 using ion implantation, and then subjected to high-temperature annealing to form a heavily doped conductive region that serves as the shielding gate electrode 2.
[0094] Next, conformal deposition of three thin films is performed sequentially on the entire structure. Specifically, a polysilicon layer 6 of predetermined thickness to be converted is first deposited by low-pressure chemical vapor deposition, followed by a silicon nitride sacrificial layer 5, and finally a silicon dioxide layer 8 as a hard mask.
[0095] After thin film deposition, reactive ion etching is used to perform an overall anisotropic dry etching on the three-layer composite thin film. This etching process removes the film on all horizontal surfaces, thereby forming a self-aligned composite sidewall structure consisting of the polysilicon layer to be converted 6, the silicon nitride sacrificial layer 5, and the hard mask layer 7 on the vertical sidewall of the main trench 1, while simultaneously precisely exposing the polysilicon layer to be converted 6 at the bottom of the main trench 1.
[0096] Subsequently, the exposed polysilicon layer 6 to be converted undergoes multi-stage in-situ oxidation. In the first stage, treatment is performed in a high-temperature nitrogen-rich atmosphere to form a silicon oxynitride layer 10 on the surface of the polysilicon layer 6. In the second stage, oxidation continues in a high-temperature water vapor-rich atmosphere to completely convert the remaining polysilicon layer 6 into a silicon dioxide layer 8. Finally, high-temperature annealing is performed in an inert gas atmosphere to passivate defects. This process ultimately forms a gradient inter-gate dielectric 9 at the bottom of the main trench 1, with a high-dielectric-constant silicon oxynitride layer 10 at the bottom and a low-dielectric-constant silicon dioxide layer 8 at the top.
[0097] After forming the inter-gate dielectric 9, a hot phosphoric acid wet etching process is used to selectively remove the silicon nitride sacrificial layer 5 in the composite sidewall structure, thereby exposing the monocrystalline silicon sidewalls above the main trench 1.
[0098] A high-quality control gate oxide layer is grown on the exposed silicon sidewalls via thermal oxidation. Then, a layer of control gate polysilicon 11 is deposited to fill the main trench 1 via low-pressure chemical vapor deposition, and the control gate polysilicon 11 is planarized using a chemical mechanical polishing process to finally form the control gate.
[0099] Finally, subsequent device manufacturing processes are performed. These processes include: forming a P-type body region 15 and an N+ type source region 14 on the surface of the epitaxial layer 3 by ion implantation; depositing an interlayer dielectric 13 and etching to form contact holes; and depositing and etching source and gate electrode leads through the metal layer 12, and forming a drain electrode on the back side of the silicon substrate 4, thereby completing the fabrication of the entire trench-type double-gate power MOS device.
Claims
1. A trench double gate power MOS structure implementation method, characterized in that, Includes the following steps: S1. An epitaxial layer (3) is grown on a silicon substrate (4), a main trench (1) is etched on the epitaxial layer (3), and a shielding gate electrode (2) is formed in the bottom region of the main trench (1). S2. On the epitaxial layer (3) and inside the main trench (1), a polysilicon layer (6), a silicon nitride sacrificial layer (5) and a hard mask layer (7) are deposited in a conformal manner. S3. Anisotropic dry etching is performed on the deposited polysilicon layer (6), silicon nitride sacrificial layer (5) and hard mask layer (7) to form a self-aligned composite sidewall structure along the sidewall of the main trench (1) and expose the polysilicon layer (6) to be converted at the bottom of the main trench (1). S4. Perform multi-stage in-situ oxidation on the polysilicon layer (6) to be converted at the bottom of the exposed main trench (1) to convert the polysilicon layer (6) to be converted at the bottom of the exposed main trench (1) into an inter-gate dielectric (9) with gradient electric field buffering characteristics. The bottom of the inter-gate dielectric (9) is a silicon oxynitride layer (10), and the top of the inter-gate dielectric (9) is a silicon dioxide layer (8). S5. Selectively remove the silicon nitride sacrificial layer (5) to expose the silicon sidewalls on the upper part of the main trench (1); S6. A control gate oxide is grown on the silicon sidewall of the exposed main trench (1), and then the control gate polysilicon (11) is deposited and etched back or planarized to form a control gate that fills the main trench (1). S7, and subsequent device manufacturing processes, including source region (14) and body region (15) formation, interlayer dielectric (13) deposition, contact hole etching and metallization.
2. The trench-type double-gate power MOS structure implementation method according to claim 1, wherein, In step S1, forming a shielding gate electrode (2) in the bottom region of the main trench (1) specifically includes: implanting a dopant into the silicon substrate (4) in the bottom region of the main trench (1) by ion implantation to form a heavily doped conductive region as the shielding gate electrode (2).
3. The trench-type double-gate power MOS structure implementation method according to claim 1, wherein, In step S2, the polycrystalline silicon layer (6) to be converted is formed by low-pressure chemical vapor deposition.
4. The trench-type double-gate power MOS structure implementation method according to claim 1, wherein, In step S3, the anisotropic dry etching is achieved using reactive ion etching or inductively coupled plasma reactive ion etching.
5. The method for implementing a trench-type double-gate power MOS structure according to claim 1, characterized in that, In step S4, the multi-stage in-situ oxidation specifically includes: In the first stage, oxidation is carried out at high temperature in an atmosphere rich in nitrogen and with controlled oxygen partial pressure, so that a silicon oxynitride layer (10) is formed on the surface of the polycrystalline silicon layer (6) to be converted. In the second stage, oxidation is carried out at high temperature in a pure oxygen or water vapor-rich atmosphere to completely convert the remaining polycrystalline silicon layer (6) to be converted into a silicon dioxide layer (8). In the third stage, high-temperature annealing is performed to passivate the defects of the inter-gate dielectric (9).
6. The trench-type double-gate power MOS structure implementation method according to claim 5, wherein, The dielectric constant of the silicon oxynitride layer (10) formed in the first stage is higher than that of the silicon dioxide layer (8) formed in the second stage.
7. The method for implementing a trench-type double-gate power MOS structure according to claim 1, characterized in that, In step S5, the selective removal of the silicon nitride sacrificial layer (5) is performed using a hot phosphoric acid wet etching method.
8. The method for implementing a trench-type double-gate power MOS structure according to claim 1, characterized in that, In step S6, the control gate oxide is grown by thermal oxidation or atomic layer deposition.
9. The method for implementing a trench-type double-gate power MOS structure according to claim 1, characterized in that, In step S6, the deposited control gate polysilicon (11) is formed by low-pressure chemical vapor deposition, and the planarization is achieved by chemical mechanical polishing.
10. A method for implementing a trench-type double-gate power MOS structure according to claim 1, characterized in that, In step S7, the subsequent device manufacturing process specifically includes: performing ion implantation on the surface region of the epitaxial layer (3) to form a source region (14) and a body region (15), depositing an interlayer dielectric (13) and etching to form contact holes, and depositing a metal layer (12) to form electrode leads.