Semifloating gate transistor and method of manufacturing the same, memory device including the same

Abstract

The application provides a kind of semi-floating gate transistor and its preparation method, the memory device comprising it, belong to semiconductor technical field.The semi-floating gate transistor includes: substrate, substrate has first well region, second well region below first well region, and the trench that is passed through first well region;Floating gate layer includes first floating gate part and second floating gate part, first floating gate part is located in the trench, second floating gate part is adjacent to first floating gate part on, and it is laterally extended to contact with first well region along first direction;Control gate is located on the surface of second floating gate part;Wherein second floating gate part has recess structure extending along second direction, first well region has first protruding part and second protruding part embedded into recess structure, first protruding part and second protruding part are spaced apart from each other along first direction and each is extended into fin shape along second direction, wherein second direction and first direction intersect.The application achieves the effect of improving charge erasing speed and improving device life.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semi-floating gate transistor and a method for fabricating the same, and a memory device comprising the same. Background Technology

[0002] As transistor sizes shrink, the scaling speed of Static Random Access Memory (SRAM) cells can no longer keep up with the scaling of logic transistors, causing SRAM to occupy an increasingly larger relative area on the chip, becoming an "area black hole."

[0003] To address this, a semi-floating gate transistor (SFGT) has been proposed. The SFGT itself can function as a memory cell, integrating a standard metal-oxide-semiconductor field-effect transistor (MOSFET) with a "semi-floating gate" for charge storage. This means that more memory devices can be integrated within the same chip area, or the chip size can be significantly reduced while maintaining the same storage capacity, thus lowering costs.

[0004] However, while SFGT has a faster read speed, approaching that of SRAM, its write (injecting or erasing charge) is generally slower than SRAM, requires higher voltage, and has a shorter device lifespan, leaving room for further improvement. Summary of the Invention

[0005] In view of this, in order to at least partially solve at least one of the aforementioned technical problems, this application provides a semi-floating gate transistor and a method for fabricating the same, and a memory device comprising the same.

[0006] To achieve the above objectives, the technical solution of this application is as follows:

[0007] According to one embodiment of this application, a semi-floating gate transistor is provided, comprising: a substrate having a first well region, a second well region below the first well region, and a trench penetrating the first well region; a floating gate layer including a first floating gate portion and a second floating gate portion, the first floating gate portion being located within the trench, the second floating gate portion being adjacent to the first floating gate portion and extending laterally along a first direction to contact the first well region, the first direction being perpendicular to the plane containing the sidewall of the trench; and a control gate located on the surface of the second floating gate portion; wherein the second floating gate portion has a groove structure extending along a second direction, the first well region having a first protrusion and a second protrusion embedded in the groove structure, the first protrusion and the second protrusion being spaced apart from each other along the first direction and each extending in a fin shape along the second direction, wherein the second direction intersects the first direction.

[0008] In some alternative embodiments, the semi-floating gate transistor further includes an insulating portion extending in a second direction, the insulating portion filling the space between the first protrusion and the second protrusion.

[0009] In some alternative embodiments, the groove structure has a bottom surface, and the ends of the insulating portion, the first protrusion, and the second protrusion are respectively abutted against the bottom surface.

[0010] In some alternative implementations, the insulation comprises an oxide.

[0011] In some alternative implementations, in the third direction, the height of each of the first protrusion and the second protrusion is not higher than 1 / 2 of the depth of the trench; or, the ratio of the height of each of the first protrusion and the second protrusion to the depth of the trench is 0.3 to 0.4.

[0012] In some alternative embodiments, the ratio of the height of the first protrusion and the second protrusion to the height of the second floating gate is 0.15 to 0.5 in the thickness direction of the substrate; wherein the third direction is perpendicular to the plane containing the first direction and the second direction.

[0013] In some alternative embodiments, in the first direction, the width of the first protrusion is w1, the width of the second protrusion is w2, and the width of the contact portion between the second floating gate portion and the first well region is w3, wherein w1 / w3 is 0.25~0.3, and / or, w2 / w3 is 0.25~0.3; and / or, in the first direction, the width of the interval between the first protrusion and the second protrusion is w4, and the width of the contact portion between the second floating gate portion and the first well region is w3, wherein w4 / w3 is 0.25~0.3.

[0014] In some alternative embodiments, the first well region further has at least one third protrusion, which is spaced apart from each other along a first direction and each extends in a fin shape along a second direction, the third protrusion being disposed on the side of the second protrusion away from the groove;

[0015] The second floating gate portion also has a protruding structure extending along the second direction, which is embedded between the third protrusion and the second protrusion and between adjacent third protrusions.

[0016] In some alternative implementations, the trench is embedded within the second well region.

[0017] In some alternative embodiments, the semi-floating gate transistor may further include: a first gate dielectric layer located between the first floating gate portion and the substrate; a second gate dielectric layer located between the second floating gate portion and the control gate, and on the surface of the substrate; and a source region and a drain region disposed on both sides of the control gate and located within the first well region.

[0018] According to another embodiment of this application, a method for fabricating a semi-floating gate transistor is provided, comprising: forming a first well region and a second well region on a substrate, wherein the second well region is below the first well region; forming a trench penetrating the first well region on the substrate, and forming a first gate dielectric layer on the surface of the trench; forming a first floating gate portion in the trench and on the surface of the first gate dielectric layer; forming a first protrusion and a second protrusion spaced apart from each other at a position in the first well region near the first floating gate portion, wherein the first protrusion and the second protrusion each extend in a fin shape along a second direction intersecting the first direction, the first direction being perpendicular to the plane containing the sidewall of the trench; forming a second floating gate portion on the first floating gate portion, the second floating gate portion extending laterally along the first direction to contact the first well region, such that the first protrusion and the second protrusion are embedded in the second floating gate portion; sequentially forming a second gate dielectric layer and a control gate on the second floating gate portion; and forming a source region and a drain region in the first well region located on both sides of the control gate.

[0019] In some alternative embodiments, forming a first floating gate portion on the surface of the first gate dielectric layer includes: filling a trench on the surface where the first gate dielectric layer is formed with a first floating gate material and etching back the first floating gate material to expose the first gate dielectric layer above the trench; removing the exposed first gate dielectric layer; and further filling the trench with the first floating gate material to form a first floating gate portion, the surfaces of the first floating gate portion and the first well region being flush.

[0020] In some alternative embodiments, forming the first protrusion and the second protrusion includes: forming a second hard mask on the surface of the first well region near the first floating gate portion, wherein the second hard mask is a sidewall structure; and etching the first well region and the first floating gate portion based on the second hard mask to form the first protrusion and the second protrusion on the first well region.

[0021] In some alternative embodiments, before forming the second floating gate portion on the first floating gate portion, the preparation method further includes forming an insulating portion between the first protrusion portion and the second protrusion portion.

[0022] According to another embodiment of this application, a storage device is also provided, the storage device including a plurality of semi-floating gate transistors as described above.

[0023] In some alternative embodiments, the memory device is configured such that: in response to a first bias voltage applied to the control gate of the semi-floating gate transistor and a first drain voltage applied between the source and drain regions, the parasitic field-effect transistor of the semi-floating gate transistor is turned on, and charge carriers flow into the floating gate layer through a contact region where the first well region and the floating gate layer are in contact, wherein more charge carriers flow in through the first protrusion than through the second protrusion; in response to a second bias voltage applied to the control gate and a second drain voltage with the opposite polarity to the second bias voltage applied between the source and drain regions, the PN junction of the contact region is forward biased, and charge carriers flow out of the floating gate layer through the contact region, wherein more charge carriers flow out through the second protrusion than through the first protrusion.

[0024] According to the SFGT provided in the embodiment of this application, a carrier transport window is formed at the contact point between the floating gate layer and the first well region. At this transport window, the first well region has a first protrusion and a second protrusion spaced apart, which are embedded in the floating gate layer to form a fin-shaped structure in contact with the second floating gate. An unexpected effect of this is that the contact area between the first well region and the floating gate layer can be significantly increased. During charge injection, since the first and second protrusions are embedded in the floating gate layer in a raised manner, the recessed spacer between them does not significantly disrupt the carrier injection mechanism, such as the parasitic field-effect transistor formed on the trench sidewall. Thus, charge injection can be achieved by utilizing the conduction of the parasitic field-effect transistor. At this time, the increased contact area from the sidewalls of the first and second protrusions can be used to increase the charge injection speed. During charge erasure, a suitable bias voltage is used to control the forward bias of the PN junction between the floating gate layer and the first well region, allowing carriers to flow out of the floating gate layer. At this time, the increased contact area from the sidewalls of the first and second protrusions can be used to increase the charge erasure speed. Therefore, this application can significantly improve the write and erase speed of SFGT. Attached Figure Description

[0025] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0026] Figure 1 This is a schematic cross-sectional view of a semi-floating gate transistor according to an embodiment of this application;

[0027] Figure 2 This is a schematic cross-sectional view of a semi-floating gate transistor according to another embodiment of this application;

[0028] Figure 3 This is a schematic flowchart illustrating the fabrication method of a semi-floating gate transistor according to an embodiment of this application;

[0029] Figures 4A to 4V This is a schematic cross-sectional view of some stages in the formation process of the semi-floating gate transistor according to an embodiment of this application.

[0030] In the above figures, the meanings of the reference numerals are as follows:

[0031] 10. Substrate;

[0032] 101. First pit region;

[0033] 102. Second well region;

[0034] 103. Trench;

[0035] 104. First protrusion;

[0036] 105. Second protrusion;

[0037] 1061, Source Region;

[0038] 1062. Leakage area;

[0039] 107. The third protrusion;

[0040] 11. First gate dielectric layer;

[0041] 12. Floating grid layer;

[0042] 121. First floating gate section;

[0043] 121a. Material of the first floating gate;

[0044] 122. Second floating gate section;

[0045] 122a. Second floating gate material;

[0046] 13. Second gate dielectric layer;

[0047] 14. Control gate;

[0048] 14a. Control grid material;

[0049] 15. Insulation components;

[0050] 15a. Insulating materials;

[0051] 20. First mask layer;

[0052] 21. Silicon oxide layer;

[0053] 22. Silicon nitride layer;

[0054] 31. First hard mask;

[0055] 32. Second hard mask;

[0056] 40. Photoresist. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0058] In the following detailed description, numerous specific details are set forth for ease of explanation to provide a thorough understanding of the embodiments of this application. However, it will be apparent that one or more embodiments may be implemented without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0059] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "comprising" as used herein indicates the presence of features, steps, or operations, but does not exclude the presence or addition of one or more other features.

[0060] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0061] In this application, the relative position between two components (e.g., a membrane or region), as referred to by terms such as "above," "on," or "above," can mean that the two components are in direct contact or that they are not in direct contact. Similarly, the relative position between two components, as referred to by terms such as "below," "under," or "below," can mean that the two components are in direct contact or that they are not in direct contact. For example, when one component (e.g., a membrane or region) is referred to as "on another component," it can be directly on the other component, or there may be other components between them. On the other hand, when a component is referred to as "directly on another component," there are no components between them. Furthermore, when one component is referred to as "on another component," the two components have a vertical relationship in the planar view, and this component can be above or below the other component, thus this vertical relationship depends on the orientation of the device.

[0062] SFGT, as a novel microelectronic device, can replace traditional SRAM in memory applications. Unlike traditional floating-gate transistors, SFGT uses a hole in the gate dielectric layer between the floating gate layer and the substrate as a carrier transport window, allowing for carrier storage via a floating gate and featuring low voltage and low power consumption. In realizing this concept, it was found that SFGT has a faster read speed than SRAM, approaching SRAM's performance, making it suitable for cache operations. However, writing (injecting or erasing charge) to SFGT is typically slower than SRAM and requires higher voltage (although lower than traditional Flash). Therefore, further improvements in SFGT's write and erase speeds are needed to enhance device performance. Furthermore, it was discovered that both writing and erasing charge in SFGT require electrons to cross the interface between the floating gate layer and the substrate. With increasing write / erase cycles, this electron migration can damage the interface quality between the floating gate layer and the substrate, thus affecting the overall device lifespan.

[0063] Figure 1 This is a schematic cross-sectional view of a semi-floating gate transistor according to an embodiment of this application.

[0064] like Figure 1 As shown, the SFGT in this embodiment may include a substrate 10, a floating gate layer 12, and a control gate 14.

[0065] The substrate 10 has a first well region 101, a second well region 102 located below the first well region 101, and a trench 103 penetrating the first well region 101 (see [link]). Figure 4B The floating gate layer 12 includes a first floating gate portion 121 and a second floating gate portion 122. The first floating gate portion 121 is located within the trench 103, and the second floating gate portion 122 is adjacent to the first floating gate portion 121 and extends laterally along the first direction X to contact the first well region 101. A control gate 14 is located on the surface of the second floating gate portion. The second floating gate portion 122 has a groove structure extending along the second direction Y (perpendicular to the plane of the paper in the figure). The first well region 101 has a first protrusion 104 and a second protrusion 105 embedded in the groove structure. The first protrusion 104 and the second protrusion 105 are spaced apart from each other along the first direction X and each extends into a fin shape along the second direction Y. The first direction X and the second direction Y intersect. In some examples, the first direction X may be perpendicular to the plane containing the sidewall of the trench.

[0066] According to some embodiments of this application, a carrier transport window is formed at the contact point between the second floating gate portion 122 and the first well region 101 of the floating gate layer 12 (located in...). Figure 1(The location indicated by the dashed box in the middle), and at this transmission window, the first well region 101 has a first protrusion 104 and a second protrusion 105 spaced apart, which are embedded in the groove structure of the second floating gate portion 122, so that they form sidewalls that contact the floating gate layer 12. An unexpected effect of this is that the contact area between the first well region 101 and the floating gate layer 12 can be significantly increased. During charge injection, the first protrusion 104 and the second protrusion 105 are embedded in the floating gate layer 12 in a raised manner, and the recessed spacer region between them does not significantly disrupt the carrier injection mechanism, such as the parasitic field-effect transistor formed on the trench sidewall. Thus, charge injection can be achieved by utilizing the conduction of the parasitic field-effect transistor. At this time, the increased contact area of ​​the sidewalls of the first protrusion 104 and the second protrusion 105 can be used to improve the charge injection speed. During charge erasure, the PN junction between the floating gate layer 12 and the first well region 101 is forward biased by using a suitable bias voltage, allowing carriers to flow out of the floating gate layer 12. At this time, the increased contact area of ​​the sidewalls of the first protrusion 104 and the second protrusion 105 can be used to improve the charge erasure speed. Therefore, this application can at least significantly improve the write and erase speed of the SFGT.

[0067] According to some embodiments of this application, the substrate 10 may include semiconductor materials, such as elemental semiconductor materials like silicon and germanium, compound semiconductor materials such as group IV compound semiconductor materials like silicon-germanium, group III-V compound semiconductor materials like gallium nitride or gallium arsenide, or two-dimensional semiconductor materials such as molybdenum disulfide. The substrate 10 may also include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0068] According to some embodiments of this application, the first well region 101 and the second well region 102 may have opposite doping types, for example, one of them is an n-well and the other is a p-well. Exemplarily, if the first well region 101 is an n-well and the second well region 102 is a p-well, the formed semi-floating gate transistor is an n-type transistor; or, if the first well region 101 is a p-well and the second well region 102 is an n-well, then the semi-floating gate transistor is a p-type transistor.

[0069] In some examples, a first well region 101 and a second well region 102 can be formed on the substrate 10 by ion implantation. For example, n-type doping can be achieved by introducing donor impurities such as phosphorus (P), arsenic (As) or antimony (Sb) into the substrate material to obtain an n-well; p-type doping can be achieved by introducing acceptor impurities such as boron (B), aluminum (Al) or gallium (Ga) into the substrate material to obtain a p-well.

[0070] The first well region 101 may be disposed on the surface of the substrate 10 (e.g., Figure 1The second well region 102 may be adjacent to the first well region 101. The first well region 101 and the second well region 102 can be formed at different depths in the substrate 10 by ion implantation at different depths.

[0071] According to some embodiments of this application, for example... Figure 1 As shown, the cross-section of trench 103 can be U-shaped or similar, and can be recessed from the surface of substrate 10. The conductive channel of the semi-floating gate transistor can be formed at the bottom of trench 103, and its working principle is similar to that of a conventional MOSFET.

[0072] According to some embodiments of this application, the floating gate layer 12 is suitable for storing charge carriers, and its material can be polycrystalline silicon or the like, and it can be prepared by processes such as chemical vapor deposition. The floating gate layer 12 and the first well region 101 are in contact to form a carrier transport window.

[0073] According to some embodiments of this application, the conductivity type of the floating gate layer 12 is opposite to that of the first well region 101, thereby forming a PN junction between the floating gate layer 12 and the first well region 101. The forward bias of the PN junction can be controlled by a suitable bias voltage to achieve efficient and low-voltage charge erasure performance. For example, the first well region is an n-well, and the floating gate layer 12 can be a p-type doped polysilicon layer; or the first well region is a p-well, and the floating gate layer 12 can be an n-type doped polysilicon layer. Taking a 40-60nm SFGT as an example, the dopant ion concentration in the floating gate layer 12 is greater than or equal to 1.25E13cm⁻¹. -3 .

[0074] According to some embodiments of this application, in the floating gate layer 12, the first floating gate portion 121 and the second floating gate portion 122 indicate that they are disposed in different positions or fabricated in different process steps, but this does not necessarily mean that there is a clear interface between the first floating gate portion 121 and the second floating gate portion 122. The material and conductivity type of the first floating gate portion 121 and the second floating gate portion 122 can be the same.

[0075] According to some embodiments of this application, the material of the control gate 14 may be polycrystalline silicon, which can be prepared by processes such as chemical vapor deposition, but is not limited thereto. In other examples, the control gate 14 may also be a metal gate electrode, including a work function layer such as a metal nitride such as titanium nitride or tantalum nitride, and a conductive layer such as a metal such as tungsten or aluminum.

[0076] According to some embodiments of this application, the first protrusion 104 and the second protrusion 105 are embedded in the groove structure of the second floating gate portion 122, thereby interlocking between the first protrusion 104 and the second protrusion 105 and the second floating gate portion 122. The first protrusion 104 and the second protrusion 105 may protrude relative to the surface of the substrate 10, thereby forming raised "fin-shaped structures". In addition to the top surface, the first protrusion 104 and the second protrusion 105 may also contact the second floating gate portion 122 through one or two opposite sidewalls.

[0077] In some examples, the second floating gate portion 122 can be embedded between the first protrusion portion 104 and the second protrusion portion 105 (not shown in the figure), that is, the two opposite side walls of the first protrusion portion 104 and the second protrusion portion 105 are in contact with the second floating gate portion 122, which is beneficial to significantly increasing the contact area for carriers to flow into and out of the floating gate layer 12, thereby significantly improving the carrier erasing and writing speed.

[0078] But it is not limited to this, such as Figure 1 As shown, the semi-floating gate transistor may further include an insulating portion 15 extending along the second direction Y, filling the space between the first protrusion 104 and the second protrusion 105. In this case, the first protrusion 104 and the second protrusion 105 can each contact the second floating gate portion 122 through a sidewall (and a top surface). Although the increase in the contact area for carrier inflow and outflow from the floating gate layer 12 is smaller compared to the embodiment described above where the second floating gate portion 122 is embedded between the first protrusion 104 and the second protrusion 105, it is still a significant improvement compared to conventional semi-floating gate transistors. Furthermore, it is worth mentioning that because the insulating portion 15 is provided between the first protrusion 104 and the second protrusion 105, the main paths for carrier inflow and outflow from the floating gate layer 12 can be adjusted to be different, thereby increasing the number of times the SFGT can operate and thus improving its lifespan.

[0079] Specifically, when injecting charge into the floating gate layer, the parasitic field-effect transistor at the control trench sidewall is turned on, and charge carriers flow into the floating gate layer 12 through the contact region where the first well region 101 and the floating gate layer 12 are in contact. More charge carriers flow in through the first protrusion 104 than through the second protrusion. Conversely, when erasing the charge stored in the floating gate layer 12, charge carriers flow out of the floating gate layer 12 through the contact region. By applying an appropriate bias to the drain region, more charge carriers flow out through the second protrusion 105 than through the first protrusion 104. Since the main interfaces for charge carrier inflow and outflow from the floating gate layer 12 are different under the write and erase charge states, the impact of carrier migration on the transmission window is effectively reduced, thereby significantly increasing the number of times the SFGT can be operated, and thus effectively increasing the lifespan of the SFGR device.

[0080] According to some embodiments of this application, the groove structure of the second floating gate portion 122 has a bottom surface, and the ends of the insulating portion 15, the first protrusion 104, and the second protrusion 105 are respectively attached to the bottom surface. Thus, the coplanar pattern between the insulating portion 15 and the first and second protrusions 104 can be naturally formed after etching the first and second protrusions 104, filling the insulating portion 15 with material, and then chemically mechanically polishing (CMP), without the need for additional masks or alignment. Furthermore, it is more process-friendly when subsequently using photoresist to mask the insulating portion 15 in the spacing area to etch the material of the insulating portion 15 at other locations. Further, by attaching to the bottom surface within the groove structure of the second floating gate portion 122, it is beneficial to improve interface contact and thus enhance the write performance of the device.

[0081] According to some embodiments of this application, in the second direction Y, the length of the insulating portion 15 can be the same as the length of the first well region 101. In this way, the mask used to form the first protrusion 104 and the second protrusion 105 can be reused, simplifying the process. At the same time, it is also beneficial to effectively control the path of charge carriers flowing into and out of the floating gate layer 12.

[0082] According to some embodiments of this application, the insulating portion 15 may include an oxide, such as silicon oxide, which may be prepared using a chemical vapor deposition process, but is not limited thereto. For example, it may also include at least one of silicon nitride or other low-k dielectric materials. Using a low-k dielectric material, such as silicon oxide, is advantageous in achieving low parasitic capacitance while ensuring insulation performance.

[0083] According to some embodiments of this application, in the third direction Z, the height of the first protrusion 104 and the second protrusion 105 (relative to the surface of the substrate 10) is no higher than 1 / 2 of the depth of the trench 103 (relative to the surface of the substrate 10), and the third direction Z can be perpendicular to the plane containing the first direction X and the second direction Y. If the height of the first protrusion 104 and the second protrusion 105 is too high, then when forming the insulating portion 15 subsequently, the etching process for etching the material of the insulating portion 15 at other locations will require high technical process requirements, such as etching selectivity.

[0084] If the heights of the first protrusion 104 and the second protrusion 105 are too low, it will be detrimental to increasing the contact area between their sidewalls, which in turn will negatively impact the charge erasure and writing speed. In particular, when the space between them is filled with insulating portion 15, the thickness of insulating portion 15 will also decrease, resulting in an insignificant effect on adjusting the path of charge carriers flowing into and out of the floating gate layer 12, which will further hinder the improvement of service life.

[0085] Therefore, the ratio of the height of the first protrusion 104 and the second protrusion 105 to the depth of the groove 103 can be 0.3 to 0.4, for example, 0.3, 0.32, 0.33, 0.35, 0.38, 0.39, 0.4, etc., to balance the ease of the manufacturing process with the charge erasure speed and service life.

[0086] According to some embodiments of this application, in the third direction Z, the ratio of the height of the first protrusion 104 and the second protrusion 105 to the height of the second floating gate 122 is 0.15 to 0.5. This is more conducive to balancing the ease of manufacturing process with the charge erasure speed and service life.

[0087] According to some embodiments of this application, the first protrusion 104 is closer to the groove 103 than the second protrusion 105. Figure 1 In the example, the sidewall of the first protrusion 104 is shown flush with the sidewall of the trench 103, but this is not a limitation. For example, due to manufacturing process reasons, the sidewall of the first protrusion 104 may be offset relative to the sidewall of the trench 103, for example, offset in a direction away from the trench 103. The semi-floating gate transistor includes a parasitic field-effect transistor formed at the sidewall of the trench 103.

[0088] For example, when the first well region 101 is an n-well, the second well region 102 is a p-well, and the floating gate layer 12 is a p-type doped layer, the parasitic field-effect transistor on the trench sidewall is a p-type transistor (PMOS).

[0089] Based on some embodiments of this application, and further referenced Figure 1In the first direction X, the width of the first protrusion 104 is w1, and the width of the second protrusion 105 is w2. w1 and w2 can be the same or different. The width of the contact portion located between the second floating gate portion 122 and the first well region 101 is w3, where w1 / w3 is 0.25~0.3, and w2 / w3 is 0.25~0.3; for example, it can be 0.25, 0.26, 0.27, 0.28, 0.29, 0.3, etc. In this way, by controlling the aforementioned ratios within a suitable range, the first protrusion 104 and the second protrusion can be effectively used to increase the contact area when injecting or erasing charges in the floating gate layer, thereby improving the write speed. If the width of the first protrusion 104 or the second protrusion 105 is too wide, leakage may easily occur due to the excessively large protrusion window; if it is too narrow, it will be difficult to effectively regulate the carrier transport path.

[0090] Based on some embodiments of this application, and further referenced Figure 1 In the first direction X, the width w4 is the distance between the first protrusion 104 and the second protrusion 105, i.e., the width of the insulating portion 15 is w4, and the width w3 is the width of the contact portion between the second floating gate portion 122 and the first well region 101, where w4 / w3 is 0.25 to 0.3; for example, it can be 0.25, 0.26, 0.27, 0.28, 0.29, 0.3, etc. In this way, by controlling the aforementioned ratio within a suitable range, the path of charge carriers flowing into and out of the floating gate layer 12 can be more effectively controlled in conjunction with the insulating portion 15.

[0091] According to some embodiments of this application, the number of protrusions in the first well region 101 may exceed two. Specifically, Figure 2 This is a schematic cross-sectional view of a semi-floating gate transistor according to another embodiment of this application, as shown below. Figure 2 As shown, the first well region 101 may also have at least one third protrusion 107 (for ease of understanding, only one third protrusion 107 is shown in the figure, but its number is not limited to this), which are spaced apart from each other along the first direction X and each extends in a fin shape along the second direction Y. The third protrusion 107 is located on the side of the second protrusion 105 away from the trench 103. The second floating gate portion 122 also has a protrusion structure extending along the second direction Y, which is embedded between the third protrusion 107 and the second protrusion 105 and between adjacent third protrusions 107. In this way, the contact area between the first well region 101 and the floating gate layer 12 can be further increased, which is more advantageous for improving the write speed, especially the speed of erasing charge.

[0092] According to some embodiments of this application, the trench 103 is embedded within the second well region. In this case, by precisely stopping the bottom of the trench within the second well region 102, it is possible to prevent the source and drain regions from communicating, thus avoiding a short circuit.

[0093] According to some embodiments of this application, the semi-floating gate transistor may further include: a first gate dielectric layer 11 and a second gate dielectric layer 13 located between the first floating gate portion 121 and the substrate 10; the second gate dielectric layer 13 located between the second floating gate portion 122 and the control gate 14, and on the surface of the substrate 10.

[0094] According to some embodiments of this application, a first gate dielectric layer 11 is located on the surface of trench 103. The top end of the first gate dielectric layer 11 may not extend beyond the surface of substrate 10, for example, it may be approximately flush with the surface of substrate 10. The thickness of the first gate dielectric layer 11 may be 4 nm to 8 nm, for example, 4 nm, 4.5 nm, 5 nm, 5.5 nm, 6 nm, 6.5 nm, 7 nm, 7.5 nm, 8 nm, etc. Exemplarily, substrate 10 may be a silicon substrate, in which case the first gate dielectric layer 11 can be formed on the sidewalls and bottom surface of the subsequently formed trench through an oxidation process, and the material of the formed first gate dielectric layer 11 is silicon oxide, which can simplify the process. Of course, it is not limited to this, and the first gate dielectric layer 11 may also be epitaxially grown by deposition methods such as atomic layer deposition, and the first gate dielectric layer may include, for example, silicon oxide, or a high-k gate dielectric such as at least one of hafnium oxide, zirconium oxide, and hafnium zirconium oxide.

[0095] According to some embodiments of this application, the materials and fabrication processes of the second gate dielectric layer 13 and the first gate dielectric layer 11 are similar, and will not be described again here. The second gate dielectric layer 13 achieves insulation between the floating gate layer 12 and the control gate 14, and the control gate is controlled through the coupling effect between the control gate 14 and the floating gate layer 12.

[0096] According to some embodiments of this application, the semi-floating gate transistor may further include a source region 1061 and a drain region 1062, located on both sides of the control gate 14 and within the first well region 101. The source region 1061 and drain region 1062 can be formed by implanting ions of the same conductivity type as the first well region 101 into the first well region 101 and then performing an annealing process. It is understood that the doping concentration of the source region 1061 and drain region 1062 is higher than the doping concentration of the first well region 101. In some examples, the doping element of the first well region 101 may include, for example, phosphorus, and the doping concentration may be 9.0E11. For example, one side of the first well region 101 where the first protrusion 104 and the second protrusion 105 are located ( Figure 1 The right side of the middle section can be the leak area 1062, while the other side ( Figure 1 The left side of the region can be source region 1061, but they can be structurally identical to each other.

[0097] According to some embodiments of this application, a method for fabricating a semi-floating gate transistor is also provided. Figure 3This is a schematic flowchart illustrating the fabrication method of a semi-floating gate transistor according to an embodiment of this application. Figures 4A to 4V This is a schematic cross-sectional view showing some stages in the formation process of the semi-floating gate transistor according to an embodiment of this application. Hereinafter, the composite material... Figure 3 , Figures 4A to 4V This document describes the preparation method of embodiments of this application.

[0098] The fabrication method includes: operation S11, forming a first well region 101 and a second well region 102 on a substrate 10, wherein the second well region 102 is below the first well region 101;

[0099] In operation S12, a trench 103 penetrating the first well region 101 is formed on the substrate 10, and a first gate dielectric layer 11 is formed on the surface of the trench 103.

[0100] In operation S13, a first floating gate portion 121 is formed in the trench 103 and on the surface of the first gate dielectric layer 11;

[0101] In operation S14, a first protrusion 104 and a second protrusion 105 are formed at a position near the first floating gate portion 121 in the first trap region 101, which are spaced apart from each other along the first direction X. The first protrusion 104 and the second protrusion 105 each extend into a fin shape along the second direction Y intersecting the first direction X. The first direction is perpendicular to the plane where the sidewall of the groove 103 is located.

[0102] In operation S15, a second floating gate portion 122 is formed on the first floating gate portion 121. The second floating gate portion 122 extends laterally along the first direction X to contact the first well region 101, such that the first protrusion 104 and the second protrusion 105 are embedded into the second floating gate portion 122.

[0103] In operation S16, a second gate dielectric layer 13 and a control gate 14 are sequentially formed on the second floating gate portion 122;

[0104] Operation S17 forms a source region 1061 and a drain region 1062 in the first well region 101 located on both sides of the control gate 14.

[0105] According to some embodiments of this application, in operation S11, a first well region 101 and a second well region 102 can be formed on the substrate 10 by ion implantation. Taking the first well region as an n-well and the second well region as a p-well as an example, if the substrate 10 is a p-type substrate, then the substrate 10 located below the first well region 101 can all serve as the second well region 102.

[0106] According to some embodiments of this application, in operation S12, for example, a trench 103 penetrating the first well region 101 can be formed on the substrate 10 in the following manner: Figure 4AAs shown, a first mask layer 20 can be formed on the substrate 10. Exemplarily, the first mask layer 20 may include a stacked film of a silicon oxide layer 21 and a silicon nitride layer 22, wherein the silicon nitride layer 22 is used to maintain pattern stability during trench formation, and the silicon oxide layer 21 is used to increase the bonding strength between the silicon nitride layer 22 and the substrate 10. Figure 4B As shown, the first mask layer 20 can be patterned based on a photolithography process. Specifically, a patterned photoresist layer can be formed on the surface of the first mask layer 20, exposing the corresponding region of the trench 103. The first mask layer 20 is then etched based on this photoresist layer to expose the substrate 10, resulting in the patterned first mask layer 20. The substrate 10 can be etched based on the patterned first mask layer 20 to form the trench 103. Specifically, the trench 103 can be formed using anisotropic dry etching techniques such as reactive plasma etching (RIE). Figure 4B In the example, the sidewalls of trench 103 are perpendicular to the surface of substrate 10, but are not limited thereto. The sidewalls of trench 103 may also be inclined relative to the surface of substrate 10 due to the etching process. For example, the width of trench 103 may gradually decrease from top to bottom.

[0107] like Figure 4C As shown, the first gate dielectric layer 11 can be formed on the surface of trench 103 by, for example, a thermal oxidation process. Taking a silicon substrate as an example, the first gate dielectric layer 11 is silicon oxide. In other examples, the first gate dielectric layer 11 can be formed by, for example, atomic layer deposition. The first gate dielectric layer can be at least one of silicon oxide, silicon nitride, hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Here, the first gate dielectric layer 11 (which is silicon oxide in this example) and the silicon oxide layer 21 in the first mask layer 20 are shown as continuous extensions.

[0108] According to some embodiments of this application, in operation S13, for example, a first floating gate portion 121 may be formed on the surface of the first gate dielectric layer 11 in the following manner.

[0109] like Figure 4D As shown, the first floating gate material 121a can be filled into the trench 103 on the surface where the first gate dielectric layer 11 is formed, and as... Figure 4E The first floating gate material 121a is etched back to expose the first gate dielectric layer 11 above the trench 103. For example, the first floating gate material 121a can be prepared by chemical vapor deposition; the etching process for the first floating gate material can be an anisotropic dry etching process such as RIE. After deposition, the deposited first floating gate material 121a can be planarized, such as by CMP, which can stop at the first mask layer 20 before etching back. The depth of the etching back can correspond to the height of the protrusion to be formed in subsequent processes.

[0110] like Figure 4F As shown, the exposed first gate dielectric layer 11 is removed; this exposes part of the sidewall surface of the trench 103. Furthermore, before removing the exposed first gate dielectric layer 11, the silicon nitride layer 22 can also be removed first, so that the exposed first gate dielectric layer 11 and silicon oxide layer 21 can be removed simultaneously in one etching step.

[0111] The trench 103, whose sidewall surface has been partially exposed as described above, is further filled with a first floating gate material to form a first floating gate portion 121. The top surface of the first floating gate portion 121 may be flush with the surface of the first well region 101. For example, the first floating gate material may be filled using chemical vapor deposition, and then, after filling with the first floating gate material, a planarization process such as CMP may be used to make the surface of the first floating gate portion 121 flush with the surface of the substrate 10 (first well region 101).

[0112] According to some embodiments of this application, in operation S14, for example, the first protrusion 104 and the second protrusion 105 can be formed in the following manner.

[0113] A second hard mask 32 is formed on the surface of the first well region 101 near the first floating gate portion 121, wherein the second hard mask 32 is a sidewall structure. For example, as Figure 4G As shown, a first hard mask material, such as silicon oxide, and a patterned photoresist layer can be sequentially formed on the surface of the first well region 101 near the first floating gate portion 121. The photoresist layer corresponds to the gap region between the first protrusion 104 and the second protrusion 105. Figure 4H As shown, the first hard mask 31 is obtained by etching the patterned photoresist layer to expose the substrate 10 and the first floating gate portion 121. Figure 4I As shown, a second hard mask material, such as silicon nitride, is conformally deposited on the exposed substrate 10, the first floating gate portion 121, and the first hard mask 31. Then, the second hard mask material is anisotropically etched to form a second hard mask 32 with a sidewall structure on both sides of the first hard mask 31. Figure 4J As shown, after the first hard mask 31 is removed by selective etching, a second hard mask 32 is obtained on the surface of the first well region 101.

[0114] like Figure 4K As shown, based on the second hard mask 32, the first well region 101 and the first floating gate portion 121 are etched, forming a first protrusion 104 and a second protrusion 105 on the first well region 101. For example, an anisotropic dry etching process such as RIE can be used. The etching depth can be controlled so that the top of the first gate dielectric layer 11 is exposed on the surface of the first well region 101. Thus, the first floating gate portion 121 can be seen through the first gate dielectric layer 11 on one side ( Figure 4K (left side) is electrically isolated from the first trap region 101 (on the other side) Figure 4K (The right side of the middle section) is also electrically isolated at this stage, and subsequently contacts each other through the second floating gate section. (For example...) Figure 4L As shown, the second hard mask 32 can be removed by selective etching.

[0115] According to some embodiments of this application, before forming the second floating gate portion 122 on the first floating gate portion 121, the method for preparing the SFGT may further include: forming an insulating portion 15 between the first protrusion portion 104 and the second protrusion portion 105.

[0116] For example, the insulating portion 15 can be formed in the following manner. Figure 4M As shown, an insulating material 15a is formed on the surfaces of the substrate 10 and the first floating gate portion 121. (As indicated...) Figure 4N As shown, a planarization process, such as CMP, is used to make the insulating material 15a flush with the surfaces of the first protrusion 104 and the second protrusion 105. Figure 4O and Figure 4P As shown, the insulating material 15a located in the spacer region is masked using photoresist 40, and the insulating material at other exposed locations is etched to obtain the insulating portion 15. The photoresist 40 can be reused to form, for example... Figure 4G The process of patterning the photoresist layer shown.

[0117] According to some embodiments of this application, in operation S15, for example, the second floating gate portion 122 can be formed on the first floating gate portion 121 in the following manner. Figure 4Q As shown, a second floating gate material 122a is deposited on the surfaces of the substrate 10 and the first floating gate portion 121. The second floating gate material and the first floating gate material can be the same. Figure 4R As shown, a patterned photoresist layer is formed on the surface of the second floating gate material 122a, and this patterned photoresist layer defines the pattern of the second floating gate portion 122. Figure 4S As shown, the second floating gate material 122a is etched based on a patterned photoresist layer to obtain the second floating gate portion 122.

[0118] According to some embodiments of this application, in operation S16, for example, a second gate dielectric layer 13 can be formed on the second floating gate portion 122 in the following manner. Figure 4T As shown, a second gate dielectric layer 13 can be formed on the surface of the second floating gate portion 122 by, for example, a thermal oxidation process. The second gate dielectric layer 13 is silicon oxide. In other examples, the second gate dielectric layer 13 can be formed by, for example, atomic layer deposition. The second gate dielectric layer can be at least one of silicon oxide, silicon nitride, hafnium oxide, zirconium oxide, and hafnium zirconium oxide.

[0119] For example, the control gate 14 can be formed on the second gate dielectric layer 13 in the following manner. Figure 4UAs shown, control gate material 14a is sequentially formed on the surface of the second gate dielectric layer 13. Figure 4V As shown, the control gate material 14a is etched using a photolithography process to obtain the control gate 14. Finally, sidewalls can be formed on both sides of the control gate 14.

[0120] According to some embodiments of this application, in operation S17, forming the source region and drain region may specifically include: implanting ions of the same conductivity type as the first well region 101 into the first well region 101 and performing an annealing process to form the source region 1061 and the drain region 1062, resulting in... Figure 1 or Figure 3 The SFGT shown.

[0121] According to another embodiment of this application, a memory device is also provided, which includes a plurality of semi-floating gate transistors as described above. The memory device may be Dynamic Random Access Memory (DRAM), SRAM, etc.

[0122] According to some embodiments of this application, the storage device is configured as follows:

[0123] In response to the first bias voltage V applied to the control gate 14 of the semi-floating gate transistor g1 and the first drain voltage V applied between the source region 1061 and the drain region 1062 (more specifically, the drain region). d1 When the parasitic field-effect transistor of the semi-floating gate transistor is turned on, the charge carriers flow into the floating gate layer 12 through the contact area where the first well region 101 and the floating gate layer 12 are in contact. Among them, the charge carriers flowing in through the first protrusion are more than the charge carriers flowing in through the second protrusion. This corresponds to the programming state of the memory device, or the charge injection state, or the write "1" state.

[0124] In response to the second bias voltage V applied to the control gate 14 g2 and a second drain voltage V, with the opposite polarity to the second bias voltage, applied between the source region 1061 and the drain region 1062 (more specifically, the drain region). d2 When the PN junction in the contact area is forward biased, charge carriers flow out of the floating gate layer 12 through the contact area. More charge carriers flow out through the second protrusion than through the first protrusion. This corresponds to the erase state of the storage device, or the charge erase state, or the write "0" state.

[0125] Thus, based on the semi-floating gate transistor provided in this application, when applied to memory devices, an unexpected effect is that by controlling a suitable bias voltage to regulate the different paths of charge carriers flowing into and out of the floating gate layer 12, the charge erasure speed and the lifespan of the memory device can be improved.

[0126] According to some embodiments of this application, the above-described storage device is further configured to:

[0127] In response to the third bias voltage V applied to the control gate 14 g3 and a third drain voltage V, which is opposite in polarity to the third bias voltage, applied to the source region 1061 and the drain region 1062 (more specifically, the drain region). d3 The PN junction in the contact area is reverse biased, which corresponds to the holding state of the storage device, or the holding state of the injected charge.

[0128] In response to the fourth bias voltage V applied to the control gate 14 g4 and a fourth drain voltage V, which is opposite in polarity to the fourth bias voltage, applied to the source region 1061 and the drain region 1062 (more specifically, the drain region). d4 At this time, the function of the semi-floating gate transistor is similar to that of a regular MOSFET. Depending on the charge storage state in the semi-floating gate, the magnitude of the current generated in the conductive channel at the bottom of the trench determines whether the storage device reads a "0" or "1" state. Generally speaking, the current in the "1" state is much greater than the current in the "0" state.

[0129] According to some embodiments of this application, for ease of understanding, the following example uses the first well region 101 of the semi-floating gate transistor provided in this application as an n-well, the second well region 102 as a p-well, and the floating gate layer 12 as a p-type doped layer to illustrate the regulation of the bias voltage and drain voltage of the control gate, as shown in the table below, which correspond to the different operating states of the memory device.

[0130] Table 1

[0131]

[0132] In summary, a carrier transmission window is formed at the contact point between the floating gate layer 12 and the first well region 101. At this transmission window, the first well region 101 has a first protrusion 104 and a second protrusion 105 spaced apart, both of which are embedded in the floating gate layer 12, forming a sidewall that contacts the second floating gate portion. An unexpected effect of this is that the contact area between the first well region 101 and the floating gate layer 12 can be significantly increased. During charge injection, the first protrusion 104 and the second protrusion 105 are embedded in the floating gate layer 12 in a raised manner. The recessed spacer region between them does not significantly disrupt the carrier injection mechanism, such as the parasitic field-effect transistor formed on the trench sidewall. Thus, charge injection can be achieved by utilizing the conduction of the parasitic field-effect transistor. At this time, the increased contact area of ​​the sidewalls of the first protrusion 104 and the second protrusion 105 can be used to increase the charge injection speed. During charge erasure, the PN junction between the floating gate layer 12 and the first well region 101 is forward biased by using a suitable bias voltage, allowing carriers to flow out of the floating gate layer 12. At this time, the increased contact area of ​​the sidewalls of the first protrusion 104 and the second protrusion 105 can be used to increase the charge erasure speed. Therefore, this application can significantly improve the erase and write speed of the SFGT.

[0133] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above descriptions are merely specific embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semi-floating gate transistor, characterized in that, include: A substrate having a first well region, a second well region below the first well region, and a trench penetrating the first well region; The floating gate layer includes a first floating gate portion and a second floating gate portion. The first floating gate portion is located in the trench, and the second floating gate portion is adjacent to the first floating gate portion and extends laterally along a first direction to contact the first well region. The first direction is perpendicular to the plane containing the sidewall of the trench. A control gate is located on the surface of the second floating gate portion; wherein the second floating gate portion has a groove structure extending along a second direction, and the first well region has a first protrusion and a second protrusion embedded in the groove structure, the first protrusion and the second protrusion being spaced apart from each other along the first direction and each extending in a fin shape along the second direction, wherein the second direction intersects the first direction; The semi-floating gate transistor further includes an insulating portion extending along the second direction, the insulating portion filling the space between the first protrusion and the second protrusion.

2. The semi-floating gate transistor according to claim 1, characterized in that, The groove structure has a bottom surface, and the ends of the insulating part, the first protrusion, and the second protrusion are respectively attached to the bottom surface.

3. The semi-floating gate transistor according to claim 1, characterized in that, In the third-party upward, The ratio of the height of the first protrusion and the height of the second protrusion to the depth of the groove is 0.3 to 0.

4. And / or, the ratio of the height of the first protrusion and the height of the second protrusion to the height of the second floating gate is 0.15 to 0.5; The third direction is perpendicular to the plane containing the first direction and the second direction.

4. The semi-floating gate transistor according to claim 1, characterized in that, In the first direction, the width of the first protrusion is w1, the width of the second protrusion is w2, and the width of the contact portion between the second floating gate portion and the first well region is w3, wherein w1 / w3 is 0.25~0.3 and w2 / w3 is 0.25~0.3; And / or, in the first direction, the width of the interval between the first protrusion and the second protrusion is w4, and the width of the contact portion located between the second floating gate portion and the first well region is w3, wherein w4 / w3 is 0.25~0.

3.

5. The semi-floating gate transistor according to claim 1, characterized in that, The first well region also has at least one third protrusion, which is spaced apart from each other along the first direction and each extends in a fin shape along the second direction, the third protrusion being disposed on the side of the second protrusion away from the groove; The second floating gate portion also has a protrusion structure extending along the second direction, wherein the number of the third protrusion portion is one, and the protrusion structure is embedded between the third protrusion portion and the second protrusion portion; or, the number of the third protrusion portion is two or more, and the protrusion structure is embedded between the third protrusion portion and the second protrusion portion and between adjacent third protrusion portions.

6. The semi-floating gate transistor according to claim 1, characterized in that, The trench is embedded within the second well region.

7. The semi-floating gate transistor according to claim 1, characterized in that, The semi-floating gate transistor further includes: A first gate dielectric layer is located between the first floating gate portion and the substrate; A second gate dielectric layer is located between the second floating gate portion and the control gate, and on the surface of the substrate; The source region and the drain region are located on both sides of the control gate and within the first well region.

8. A method for fabricating a semi-floating gate transistor, characterized in that, include: A first well region and a second well region are formed in the substrate, wherein the second well region is below the first well region; A trench is formed on the substrate that extends through the first well region, and a first gate dielectric layer is formed on the surface of the trench; A first floating gate portion is formed within the trench and on the surface of the first gate dielectric layer; In the first well region near the first floating gate portion, a first protrusion and a second protrusion are formed at intervals along a first direction. The first protrusion and the second protrusion each extend into a fin shape along a second direction intersecting the first direction. The first direction is perpendicular to the plane containing the sidewall of the groove. An insulating portion is formed between the first protrusion and the second protrusion; A second floating gate portion is formed on the first floating gate portion, and the second floating gate portion extends laterally along the first direction to contact the first well region, such that the first protrusion and the second protrusion are embedded in the second floating gate portion; A second gate dielectric layer and a control gate are sequentially formed on the second floating gate portion; A source region and a drain region are formed in the first well region located on both sides of the control gate.

9. The method for fabricating a semi-floating gate transistor according to claim 8, characterized in that, Forming the first floating gate portion on the surface of the first gate dielectric layer includes: The first floating gate material is filled into the trench on which the first gate dielectric layer is formed on the surface, and the first floating gate material is etched back to expose the first gate dielectric layer above the trench. Remove the exposed first gate dielectric layer; The first floating grid material is further filled into the trench to form the first floating grid portion, which is flush with the surface of the first well region; The formation of the first protrusion and the second protrusion includes: A second hard mask is formed on the surface of the first well region near the first floating gate portion, wherein the second hard mask is a sidewall structure; Based on the second hard mask, the first well region and the first floating gate portion are etched to form the first protrusion and the second protrusion on the first well region.

10. A storage device, characterized in that, The memory device includes a plurality of semi-floating gate transistors as described in any one of claims 1 to 7.

11. The storage device according to claim 10, characterized in that, The storage device is configured as follows: In response to a first bias voltage applied to the control gate of the semi-floating gate transistor and a first drain voltage applied between the source and drain regions, the parasitic field-effect transistor of the semi-floating gate transistor is turned on, and charge carriers flow into the floating gate layer through the contact region where the first well region and the floating gate layer are in contact, wherein more charge carriers flow in through the first protrusion than through the second protrusion. In response to a second bias voltage applied to the control gate and a second drain voltage of opposite polarity applied between the source and drain regions, the PN junction of the contact region is forward biased, and charge carriers flow out of the floating gate layer through the contact region, wherein more charge carriers flow out through the second protrusion than through the first protrusion.

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