半导体结构的制造方法和半导体结构
By forming a gate stack structure on a high dielectric constant dielectric layer and using it as a mask, a sigma trench is formed in the PMOS device region, which solves the problem of etching damage in the PMOS device region, improves device yield and reliability, and reduces process complexity and cost.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2026-03-26
- Publication Date
- 2026-07-17
AI Technical Summary
In existing technologies, the pseudo-gate structure in the PMOS device region is etched and damaged during the formation of sigma trenches, resulting in a difference in pseudo-gate height between the PMOS device region and the NMOS device region. This affects the uniformity of subsequent processes and device yield, and increases process complexity and cost.
By forming a gate stack structure on a high dielectric constant layer and using a patterned high dielectric constant layer as a mask, a sigma trench is formed in the PMOS device region, avoiding additional photomask processes, achieving selective etching, and simultaneously processing the gate stack structure of the NMOS and PMOS device regions.
It eliminates the dummy gate height difference between PMOS and NMOS device regions, improves device yield and reliability, simplifies the process flow, reduces cost and complexity, and ensures etching uniformity.
Smart Images
Figure CN121968691B_ABST