A semiconductor device and its fabrication method
By employing a combination of polishing barrier layer and etching barrier layer in semiconductor devices, the thickness of the dielectric layer is controlled, thus solving the micro-trenches problem caused by deep trench etching and improving the yield and reliability of the devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2026-04-01
- Publication Date
- 2026-07-17
Smart Images
Figure CN121969040B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and its fabrication method. Background Technology
[0002] Deep trench etching is a critical process in the manufacturing of advanced semiconductor devices such as BSI image sensors. Currently, this process typically employs a hard mask stacking structure. In a typical back-end BSI process flow, the "wide and deep" trenches formed by dielectric layer etching make it easy for plasma etching to create micro-trenches at the bottom of the deep trench sidewalls. These micro-trenches are located close to the trenches with solder pads, and during chemical mechanical polishing, the concentrated polishing stress can lead to fatal defects such as peeling and cracking of the patterned film, severely impacting device yield and reliability. Summary of the Invention
[0003] The purpose of this invention is to provide a semiconductor device and its fabrication method, which can effectively improve the formation of microtrench.
[0004] To address the above technical problems, this invention provides a method for fabricating a semiconductor device, comprising the following steps:
[0005] A semiconductor substrate having a first trench is provided, wherein a polishing barrier layer is disposed on the semiconductor substrate outside the first trench, and a pad is disposed in the first trench;
[0006] A first dielectric layer, an etch barrier layer, and a second dielectric layer are sequentially formed on the polishing barrier layer. The first dielectric layer, the etch barrier layer, and the second dielectric layer also fill the first trench. A second groove is formed in the second dielectric layer. The second groove is located above the first trench. The thickness of the first dielectric layer is equal to the distance between the polishing barrier layer and the pad in the thickness direction.
[0007] A patterned photoresist layer is formed, the patterned photoresist layer exposes the second dielectric layer outside the second groove, and the second dielectric layer and the etching stop layer are etched sequentially using the patterned photoresist layer as a mask, and the etching stops in the first dielectric layer to remove the photoresist layer;
[0008] The first dielectric layer is removed by grinding, exposing the grinding barrier layer and the etching barrier layer at the first trench.
[0009] In some embodiments, the thickness of the abrasion barrier layer is the same as the thickness of the etching barrier layer.
[0010] In some embodiments, the materials of the etching barrier layer and the polishing barrier layer are selected as silicon nitride, and the materials of the first dielectric layer and the second dielectric layer are selected as silicon oxide.
[0011] In some embodiments, the abrasion barrier layer located outside the first trench is flush with the etching barrier layer located in the first trench.
[0012] In some embodiments, sequentially etching the second dielectric layer and the etching stop layer further includes:
[0013] Using a patterned photoresist layer as a mask, the second dielectric layer is etched using a first reactive gas and a dry etching process, exposing the etching stop layer.
[0014] Using a patterned photoresist layer as a mask, the etching stop layer is etched using a second reactive gas and a dry etching process, and the etching stops in the first dielectric layer.
[0015] In some embodiments, the first reactant gas includes C4F8, O2, and Ar, and the second reactant gas includes C4F8, O2, N2, and Ar.
[0016] In some embodiments, when etching the second dielectric layer, an etching stop point is captured by endpoint detection to expose the etching stop layer.
[0017] In some embodiments, after the grinding process, the process further includes:
[0018] The polishing barrier layer and the etching barrier layer are removed by CMP process, wherein the thickness of the first dielectric layer is greater than 1.2 μm.
[0019] In some embodiments, after the grinding process, the process further includes:
[0020] The grinding barrier layer and the etching barrier layer are removed by a dry etching process, wherein the thickness of the first dielectric layer is 1.2 μm ≥ H1 > 0.8 μm.
[0021] On the other hand, the present invention also provides a semiconductor device, which is fabricated using the semiconductor device fabrication method described above. The semiconductor device includes a semiconductor substrate having a first trench, a polishing barrier layer disposed on the semiconductor substrate outside the first trench, a pad disposed in the first trench, a first dielectric layer filled in the first trench, an etch stop layer disposed on the surface of the first dielectric layer, and the etch stop layer being flush with and spaced apart from the polishing barrier layer.
[0022] Compared with the prior art, the present invention has the following unexpected technical effects:
[0023] This invention provides a semiconductor device and a method for fabricating the same. The method for fabricating the semiconductor device includes the following steps: providing a semiconductor substrate having a first trench, wherein a polishing barrier layer is disposed on the semiconductor substrate outside the first trench, and a pad is disposed in the first trench; sequentially forming a first dielectric layer, an etch barrier layer, and a second dielectric layer on the polishing barrier layer, wherein the first dielectric layer, the etch barrier layer, and the second dielectric layer also fill the first trench; forming a second groove in the second dielectric layer, wherein the second groove is located above the first trench; wherein the thickness of the first dielectric layer is equal to the spacing between the polishing barrier layer and the pad in the thickness direction; forming a patterned photoresist layer, wherein the patterned photoresist layer exposes the second dielectric layer outside the second groove; and using the patterned photoresist layer as a mask, sequentially etching the second dielectric layer and an etch stop layer, with the etching stopping in the first dielectric layer; removing the photoresist layer; polishing to remove the first dielectric layer and expose the polishing barrier layer and the etch barrier layer at the first trench. The present invention uses the thickness of the first dielectric layer to be equal to the spacing between the polishing barrier layer and the pad in the thickness direction, so that the etching barrier layer located at the first trench and the polishing barrier layer located outside the first trench are flush, thereby effectively buffering the formation of micro trenches. Attached Figure Description
[0024] Figure 1 This is a schematic diagram of a semiconductor device after a photoresist layer has been formed.
[0025] Figure 2 This is a schematic diagram of the structure of a semiconductor device after etching the oxide dielectric layer.
[0026] Figure 3 This is a schematic diagram of a semiconductor device with microgrooves.
[0027] Figure 4 This is a schematic diagram of the structure of a semiconductor device during grinding.
[0028] Figure 5 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.
[0029] Figure 6 This is a schematic diagram of the structure of a semiconductor substrate provided in an embodiment of the present invention.
[0030] Figure 7 This is a schematic diagram of a structure having a first dielectric layer, an etch barrier layer, and a second dielectric layer, provided in an embodiment of the present invention.
[0031] Figure 8 This is a schematic diagram of a structure with a second dielectric layer etched, provided as an embodiment of the present invention.
[0032] Figure 9 This is a schematic diagram of a structure with an etch stop layer and a first dielectric layer etched, according to an embodiment of the present invention.
[0033] Figure 10 This is a schematic diagram of the structure after the grinding process provided in an embodiment of the present invention.
[0034] Explanation of reference numerals in the attached figures:
[0035] Figures 1-4 In the middle: 10-Initial semiconductor structure; 11-Pad; 12-Silicon nitride layer; 13-Dielectric layer; 14-Initial photoresist layer; 20-Deep trench; 21-Micro trench;
[0036] Figures 6-10 In the middle: 100-semiconductor substrate; 101-first trench; 110-interface layer; 120-first high-dielectric material layer; 130-second high-dielectric material layer; 140-passivation layer; 150-precursor layer; 160-grinding barrier layer; 170-pad; 210-first dielectric layer; 220-etch stop layer; 230-second dielectric layer; 300-photoresist layer. Detailed Implementation
[0037] The following will provide a more detailed description of a semiconductor device and its fabrication method according to the present invention. The invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.
[0038] For clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not detailed in detail, as they would obscure the invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific objectives, such as changes from one embodiment to another according to limitations related to the system or business. Furthermore, it should be understood that such development work may be complex and time-consuming, but is merely routine work for those skilled in the art.
[0039] To make the objectives and features of the present invention more apparent and understandable, the specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, and are only used to conveniently and clearly assist in illustrating the objectives of the embodiments of the present invention.
[0040] like Figure 1As shown, the current semiconductor device includes an initial semiconductor structure 10, on the surface of which a silicon nitride layer 12 is disposed. A first trench is disposed in the initial semiconductor structure 10, the first trench penetrating the silicon nitride layer 12 and a portion of the depth of the initial semiconductor structure 10. A pad 11 is disposed at the bottom of the first trench, the pad 11 connecting to the top metal layer of the interconnect structure. A dielectric layer 13 is filled in the first trench, the dielectric layer 13 covering the pad 11 and also covering the surface of the silicon nitride layer 12, the thickness h1 of the dielectric layer on the silicon nitride layer 12 being, for example, 3.6 μm.
[0041] A second groove is provided in the dielectric layer 13, the second groove being located above the first trench. A patterned initial photoresist layer 14 is formed on the dielectric layer 13, the patterned initial photoresist layer 14 filling the second groove and exposing a portion of the dielectric layer 13 outside the second groove.
[0042] like Figures 2-3 As shown, using the patterned initial photoresist layer 14 as a mask, a dry etching process is first used to etch most of the thickness of the dielectric layer 13 to form deep trenches 20. For example, the 3.6 μm dielectric layer 13 is etched, leaving a dielectric layer 13 with a thickness h2 of 0.7 μm. During the etching process, micro-trenches 21 easily appear at the bottom of the sidewalls of the dielectric layer 13 in the area covered by the initial photoresist layer 14. It can be seen that the position of the micro-trenches 21 is close to the first trench. Then, the initial photoresist layer 14 is removed.
[0043] like Figure 4 As shown, a CMP process is performed to remove the dielectric layer 13 on the silicon nitride layer 12. In this step, since the micro trench a is close to the first trench, the grinding stress is concentrated at the micro trench a, which can lead to the peeling of the second groove pattern or cracking at the bottom of the second groove, which seriously affects the yield and reliability of the device.
[0044] Figure 5 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to this embodiment. Figure 5 As shown, this embodiment provides a method for fabricating a semiconductor device, including the following steps:
[0045] Step S1: Provide a semiconductor substrate with a first trench, wherein a polishing barrier layer is disposed on the semiconductor substrate outside the first trench, and a pad is disposed in the first trench;
[0046] Step S2: A first dielectric layer, an etch barrier layer, and a second dielectric layer are sequentially formed on the polishing barrier layer. The first dielectric layer, the etch barrier layer, and the second dielectric layer also fill the first trench. A second groove is formed in the second dielectric layer. The second groove is located above the first trench. The thickness of the first dielectric layer is equal to the distance between the polishing barrier layer and the pad in the thickness direction.
[0047] Step S3: Form a patterned photoresist layer, the patterned photoresist layer exposes the second dielectric layer outside the second groove, and using the patterned photoresist layer as a mask, etch the second dielectric layer and the etching stop layer in sequence, and stop the etching in the first dielectric layer to remove the photoresist layer;
[0048] Step S4: Grind away the first dielectric layer and expose the grinding barrier layer and the etching barrier layer at the first trench.
[0049] In this embodiment, the thickness of the first dielectric layer is equal to the spacing between the polishing barrier layer and the pad in the thickness direction, so that the etching barrier layer located at the first trench and the polishing barrier layer located outside the first trench are flush, thereby effectively buffering the formation of micro trenches.
[0050] The following combination Figures 6-10 This embodiment provides a detailed description of a method for fabricating a semiconductor device.
[0051] Figure 6 This is a schematic diagram of the semiconductor substrate provided in this embodiment. Figure 6 As shown, step S1 is first performed, providing a semiconductor substrate 100 with a first trench 101. A polishing barrier layer 160 is provided on the semiconductor substrate 100 outside the first trench 101, and a pad 170 is provided in the first trench 101.
[0052] In detail, firstly, a semiconductor substrate 100 is provided, comprising a bottom substrate, which includes a silicon substrate. A device layer is disposed on the silicon substrate, and a core functional device, such as a photodiode, is disposed in the device layer. An interconnect structure layer is disposed on the device layer to bring out the core functional device in the device layer. The top metal layer of the interconnect structure layer includes bonding pads, and an interface layer 110 is disposed on the top metal layer. The interface layer 110 covers the bonding pads in the top metal layer and serves as an ultra-thin interface layer, which can reduce the interface state density and improve the carrier mobility. The material of the interface layer 110 is silicon oxide.
[0053] Next, a high-dielectric material layer, a passivation layer 140, a precursor layer 150, and a polishing barrier layer 160 are sequentially formed on the interface layer 110. The high-dielectric material layer includes a first high-dielectric material layer 120 and a second high-dielectric material layer 130, with the first high-dielectric material layer 120 disposed on the interface layer 110 and the second high-dielectric material layer 130 located on the first high-dielectric material layer 120. Therefore, the semiconductor substrate 100 includes a bottom substrate, an interface layer 110, a high-dielectric material layer, a passivation layer 140, and a precursor layer 150.
[0054] The first high-dielectric material layer 120 is selected from Al₂O₃ with a dielectric constant (e.g., K = 9). This layer serves as a thermodynamically stabilizing layer and a metal barrier layer, suppressing leakage current and preventing metal diffusion. The second high-dielectric material layer 130 is selected from Ta₂O₅ with a high dielectric constant (e.g., K = 25). This layer is used to increase capacitance density. The passivation layer 140 uses ALD (atomic layer deposition) silicon dioxide to prevent metal diffusion. The precursor layer 150, made of TEOS (tetraethyl orthosilicate), is used to achieve high-quality trench filling. The polishing barrier layer 160 is made of silicon nitride. This layer serves as a stop layer in CMP, its core function being to "stop on SIN" during the chemical mechanical polishing (CMP) step. Because the hardness and flatness of silicon nitride differ from those of silicon oxide, the polishing rate (selectivity ratio) for silicon nitride and silicon oxide in the CMP process differs significantly. The polishing barrier layer 160 provides a global and uniform "braking point" for the CMP process, preventing excessive polishing by CMP from damaging the underlying device structure.
[0055] Next, a first trench 101 is formed, which penetrates the polishing barrier layer 160, the precursor layer 150, the passivation layer 140, the high dielectric material layer and the interface layer 110, and stops in the interconnect structure layer without exposing the solder pads.
[0056] Next, a pad 170 is formed in the first trench 101. The pad 170 is electrically connected to the solder pad and is used for connection to an external circuit. The pad 170 is made of aluminum. The pad 170 is embedded in an insulating material within the first trench 101, with the insulating material exposing the upper surface of the pad 170.
[0057] At this time, the distance between the pad 170 and the polishing barrier layer 160 is, for example, H1, which can be greater than 1.2 μm, or less than or equal to 1.2 μm and greater than 0.8 μm.
[0058] Figure 7This is a schematic diagram of a structure having a first dielectric layer, an etch barrier layer, and a second dielectric layer, as provided in this embodiment. Figure 7 As shown, step S2 is then performed, in which a first dielectric layer 210, an etch barrier layer, and a second dielectric layer 230 are sequentially formed on the polishing barrier layer 160. The first dielectric layer 210, the etch barrier layer, and the second dielectric layer 230 also fill the first trench 101. A second groove is formed in the second dielectric layer 230, and the second groove is located above the first trench 101. The thickness of the first dielectric layer 210 is equal to the distance between the polishing barrier layer 160 and the pad 170 in the thickness direction.
[0059] In detail, firstly, a first dielectric layer 210, an etching barrier layer, and a second dielectric layer 230 are sequentially formed on the polishing barrier layer 160 through a deposition process. The thickness of the first dielectric layer 210 is H1, the thickness of the second dielectric layer 230 is H2, and the total thickness of the first dielectric layer 210 and the second dielectric layer 230 is the target thickness (for example, the total thickness of the dielectric layer in the prior art is 3.6 μm). When the target thickness is fixed, the thickness of the second dielectric layer 230 varies with the thickness of the first dielectric layer 210.
[0060] The thickness of the polishing barrier layer 160 is the same as the thickness of the etching barrier layer. The etching barrier layer is made of silicon nitride, and the first dielectric layer 210 and the second dielectric layer 230 are made of silicon oxide.
[0061] In this embodiment, the polishing barrier layer 160 located outside the first trench 101 is flush with the etch barrier layer located at the first trench 101. This allows the etch barrier layer at the first trench 101 and the polishing barrier layer 160 located outside the first trench 101 to serve the same masking function in subsequent CMP processes. The etch barrier layer outside the first trench 101 is used in the etching steps, particularly the main etching (ME) step, where the process utilizes a high selectivity ratio for silicon oxide and silicon nitride. This means that the etchant etches silicon oxide much faster than it etches silicon nitride. When etching reaches the etch barrier layer, the EPD (Endpoint Detection) system detects a signal change and precisely stops the etching, ensuring the consistency and controllability of the etching depth.
[0062] Next, a second groove is formed in the second dielectric layer 230, the second groove being located above the first trench 101. The second groove is used to mark the position of the pad 170.
[0063] Figure 8 This is a schematic diagram of the structure of the second dielectric layer etched in this embodiment. Figure 9This is a schematic diagram of the structure with the etch stop layer and the first dielectric layer etched, provided for this embodiment. (See diagram below.) Figures 8-9 As shown, please also refer to Figure 7 Next, step S3 is executed to form a patterned photoresist layer 300. The patterned photoresist layer 300 exposes the second dielectric layer 230 outside the second groove. Using the patterned photoresist layer 300 as a mask, the second dielectric layer 230 and the etching stop layer 220 are etched sequentially, and the etching stops in the first dielectric layer 210 to remove the photoresist layer 300.
[0064] For more details, please continue reading. Figure 7 First, a patterned photoresist layer 300 is formed on the second dielectric layer 230. The patterned photoresist layer 300 fills the second groove and covers the second dielectric layer 230 around the second groove.
[0065] like Figure 8 As shown, next, using the patterned photoresist layer 300 as a mask, the second dielectric layer 230 is etched by a dry etching process (i.e., the main etching step), and the etching stop position is captured by EPD (end point detection) to expose the etching stop layer 220.
[0066] The reaction gases used in this step include C4F8, O2, and Ar. Due to the high etching selectivity of the material of the second dielectric layer 230 (silicon oxide) and the material of the etching stop layer 220 (silicon nitride), the etching in this step stops on the etching stop layer 220, which can effectively reduce the occurrence of microtrenches.
[0067] like Figure 9 As shown, next, using the patterned photoresist layer 300 as a mask, the etching stop layer 220 is etched by a dry etching process (i.e., over-etching step), and the etching stops in the first dielectric layer 210. At this time, the thickness H3 of the first dielectric layer 210 is the same as the remaining thickness of the dielectric layer after one etching in the prior art, for example, both are 700 angstroms.
[0068] The reaction gases used in this step include C4F8, O2, N2, and Ar. The N2 in this step can be used to protect the ions from bombarding the sidewalls of the bottom material, thus increasing the interaction between N2 and fluorocarbon groups (such as CF2). x The reaction produces more stable carbon-nitrogen polymers (such as CN). x F x The enhanced sidewall passivation layer 140 reduces lateral etching caused by bottom ion bombardment, thereby increasing carbon-nitrogen polymer deposition; simultaneously, the addition of N2 dilutes the fluorine-based reactive gas, reducing fluorine free radicals (F... + This reduces the activity of fluorine free radicals, thereby weakening the aggressive etching of the bottom material and effectively suppressing the concentration of fluorine free radicals.
[0069] Next, the remaining photoresist layer 300 is removed.
[0070] Figure 10 This is a schematic diagram of the structure after the grinding process provided in this embodiment. Figure 10 As shown, step S4 is then performed, whereby the first dielectric layer 210 is removed by grinding, exposing the grinding barrier layer 160 and the etching barrier layer at the first trench 101. Specifically, the remaining first dielectric layer 210 is removed by CMP process, and grinding stops on the grinding barrier layer, exposing the etching stop layer 220 located at the first trench 101.
[0071] In this step, the etching stop layer 220 at the first trench 101 serves as a stop layer (or barrier layer) for CMP, effectively preventing the deepening of the second groove in the first trench 101 and improving the uniformity of CMP. Simultaneously, since the etching stop layer 220 has better mechanical strength, stress resistance, and chemical stability than the dielectric layer (i.e., silicon oxide), it can effectively prevent crack propagation in a multilayer stacked structure (i.e., a stack of the polishing barrier layer, the first dielectric layer 210, the etching stop layer 220, and the second dielectric layer 230).
[0072] Following the grinding process, the following is also included:
[0073] If the thickness of the first dielectric layer 210 (i.e., the distance between the polishing barrier layer and the pad 170 in the thickness direction) H1 is greater than 1.2 μm, the polishing barrier layer 160 and the etching barrier layer are removed by CMP process; if 1.2 μm ≥ H1 > 0.8 μm, the polishing barrier layer 160 and the etching barrier layer are removed by dry etching process.
[0074] This embodiment also provides a semiconductor device, such as a BSI image sensor. The semiconductor device includes a semiconductor substrate 100 having a first trench 101, a polishing barrier layer 160 disposed on the semiconductor substrate 100 outside the first trench 101, a pad 170 disposed in the first trench 101, a first dielectric layer 210 filled in the first trench 101, and an etch stop layer 220 disposed on the surface of the first dielectric layer 210, the etch stop layer 220 being flush with and spaced apart from the polishing barrier layer.
[0075] In summary, the present invention provides a semiconductor device and a method for fabricating the same. The method for fabricating the semiconductor device includes the following steps: providing a semiconductor substrate having a first trench, wherein a polishing barrier layer is disposed on the semiconductor substrate outside the first trench, and a pad is disposed in the first trench; sequentially forming a first dielectric layer, an etch barrier layer, and a second dielectric layer on the polishing barrier layer, wherein the first dielectric layer, the etch barrier layer, and the second dielectric layer also fill the first trench, and forming a second groove in the second dielectric layer, wherein the second groove is located above the first trench, wherein the thickness of the first dielectric layer is equal to the spacing between the polishing barrier layer and the pad in the thickness direction; forming a patterned photoresist layer, wherein the patterned photoresist layer exposes the second dielectric layer outside the second groove, and using the patterned photoresist layer as a mask, sequentially etching the second dielectric layer and an etch stop layer, and etching stops in the first dielectric layer, and removing the photoresist layer; polishing to remove the first dielectric layer and expose the polishing barrier layer and the etch barrier layer at the first trench. The present invention uses the thickness of the first dielectric layer to be equal to the spacing between the polishing barrier layer and the pad in the thickness direction, so that the etching barrier layer located at the first trench and the polishing barrier layer located outside the first trench are flush, thereby effectively buffering the formation of micro trenches.
[0076] Furthermore, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are used only to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.
[0077] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the protection scope of the present invention.
Claims
1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A semiconductor substrate having a first trench is provided, wherein a polishing barrier layer is disposed on the semiconductor substrate outside the first trench, and a pad is disposed in the first trench; A first dielectric layer, an etch barrier layer, and a second dielectric layer are sequentially formed on the polishing barrier layer. The first dielectric layer, the etch barrier layer, and the second dielectric layer also fill the first trench. A second groove is formed in the second dielectric layer. The second groove is located above the first trench. The thickness of the first dielectric layer is equal to the distance between the polishing barrier layer and the pad in the thickness direction. A patterned photoresist layer is formed, the patterned photoresist layer exposes the second dielectric layer outside the second groove, and the second dielectric layer and the etching barrier layer are etched sequentially using the patterned photoresist layer as a mask, and the etching stops in the first dielectric layer to remove the photoresist layer. The first dielectric layer is removed by grinding, exposing the grinding barrier layer and the etching barrier layer at the first trench.
2. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The thickness of the abrasive barrier layer is the same as the thickness of the etching barrier layer.
3. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The materials of the etching barrier layer and the polishing barrier layer are selected as silicon nitride, and the materials of the first dielectric layer and the second dielectric layer are selected as silicon oxide.
4. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The abrasion barrier layer located outside the first trench is flush with the etching barrier layer located in the first trench.
5. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The sequential etching of the second dielectric layer and the etching barrier layer further includes: Using a patterned photoresist layer as a mask, the second dielectric layer is etched using a first reactive gas and a dry etching process, thereby exposing the etching barrier layer. Using a patterned photoresist layer as a mask, the etching barrier layer is etched using a second reactive gas and a dry etching process, and the etching stops in the first dielectric layer.
6. The method for fabricating a semiconductor device as described in claim 5, characterized in that, The first reactant gas includes C4F8, O2 and Ar, and the second reactant gas includes C4F8, O2, N2 and Ar.
7. The method for fabricating a semiconductor device as described in claim 5, characterized in that, When etching the second dielectric layer, the etching stop position is captured by endpoint detection to expose the etching barrier layer.
8. The method for fabricating a semiconductor device as described in claim 1, characterized in that, Following the grinding process, it also includes: The polishing barrier layer and the etching barrier layer are removed by CMP process, wherein the thickness of the first dielectric layer is greater than 1.2 μm.
9. The method for fabricating a semiconductor device as described in claim 1, characterized in that, Following the grinding process, it also includes: The grinding barrier layer and the etching barrier layer are removed by a dry etching process, wherein the thickness of the first dielectric layer is 1.2 μm ≥ H1 > 0.8 μm.
10. A semiconductor device, fabricated using the method for fabricating a semiconductor device as described in any one of claims 1 to 7, characterized in that, The semiconductor device includes a semiconductor substrate having a first trench, a polishing barrier layer disposed on the semiconductor substrate outside the first trench, a pad disposed in the first trench, a first dielectric layer filled in the first trench, an etch barrier layer disposed on the surface of the first dielectric layer, and the etch barrier layer and the polishing barrier layer being flush and spaced apart.