半导体结构、半导体结构的形成方法、存储器及电子设备
By setting mutually attached isolation structures in the semiconductor structure and using selective etching and protective layer filling technology, the critical size loss and electrical performance problems caused by increased etching depth are solved, achieving higher integration and electrical performance stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- RUILI INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2026-04-02
- Publication Date
- 2026-07-17
AI Technical Summary
In semiconductor manufacturing, as the etching depth increases, the size of the etching opening decreases, resulting in a tapered etching morphology boundary, which causes critical dimension loss and device electrical performance issues.
By setting a first isolation structure and a second isolation structure that are attached to each other in the substrate, the formation of etching defect structures is avoided. Selective etching and protective layer filling techniques are used to ensure the verticality of the etching morphology.
It avoids critical dimension loss caused by etching defects, improves the integration and electrical performance of semiconductor structures, and reduces the risk of electrical interconnection of devices.
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Figure CN121969131B_ABST
Abstract
Citation Information
Patent Citations
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