A semiconductor device manufacturing method and a semiconductor device

By generating an N-type injection region and contact holes within the wafer marking area to form a PN junction diode, and combining it with multiple metal layers and vias to form an antenna structure, the problem of electrostatic charge accumulation in the wafer marking area is solved, achieving rapid charge discharge and structural protection, and reducing production costs.

CN121969158BActive Publication Date: 2026-05-29SOUTH CHINA UNIV OF TECH +1
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
SOUTH CHINA UNIV OF TECH
Filing Date
2026-04-01
Publication Date
2026-05-29

AI Technical Summary

Technical Problem

During semiconductor wafer manufacturing, electrostatic charges can easily accumulate in the wafer marking area, leading to destructive electric arcs. Existing technologies cannot effectively protect against this, affecting wafer manufacturing yield and increasing production costs.

Method used

An N-type injection region and contact holes are generated within the wafer marking area to form a PN junction diode. This is combined with multiple metal layers and vias to form an antenna structure. The PN junction diode enables safe grounding and provides a low-resistance discharge path for the charge.

Benefits of technology

It can quickly dissipate static charge, prevent the generation of destructive electric arcs, protect the structural integrity of the wafer marking area and surrounding chip functional areas, reduce production difficulty and cost, and improve charge conduction efficiency.

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Abstract

The application provides a semiconductor device preparation method and a semiconductor device, and relates to the technical field of semiconductor manufacturing. The method comprises the following steps: generating an N-type injection region on a P-type substrate in a wafer marking area, forming a contact hole on the surface of the N-type injection region, and forming a PN junction diode by the N-type injection region and the P-type substrate; generating a first metal layer on the surface of the N-type injection region; sequentially forming metal layers of a multilayer metal mesh structure on the first metal layer according to the number of chip metal layers, and electrically interconnecting adjacent metal layers through a via; generating a passivation layer on the surface of the outermost metal layer to obtain a semiconductor device; wherein the metal layer, the contact hole and the N-type injection region jointly form an antenna structure and are safely grounded through the PN junction diode. By using the semiconductor device preparation method and the semiconductor device, the problem that electric charges are easy to accumulate and generate destructive electric arcs in the wafer marking area process is solved, the low-resistance discharge of the electric charges is realized, and the electric arc damage is effectively prevented.
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