A ring amplifier circuit employing duplicate bias and bias enhancement techniques

Abstract

This invention discloses a ring amplifier circuit employing duplicate biasing and bias enhancement techniques, including a first amplification stage, a second amplification stage, and a third amplification stage, as well as a duplicate biasing loop and an output stage bias enhancement circuit. In the duplicate biasing loop, the circuit structure of the duplicate branch is the same as that of the second amplification stage, and the circuit parameters of the duplicate branch are proportional to 1 / N of those of the second amplification stage. The output stage bias enhancement circuit includes a second amplification stage bias resistor connected in series between the PMOS and NMOS transistors of the second amplification stage A2, and a cross-connection method from the output of the second amplification stage to the input of the third amplification stage. The cross-connection method connects the high output node voltage of the second amplification stage to the input of the NMOS transistor of the third amplification stage, while simultaneously connecting the low output node voltage of the second amplification stage to the input of the PMOS transistor of the third amplification stage. This invention, through the design of the duplicate biasing loop and the output stage bias enhancement techniques, achieves a comprehensive balance between stable performance under different process, voltage, and temperature conditions and the requirements for high-speed and high-precision performance.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit design technology, and relates to operational amplifier technology for applications such as high-speed, high-precision data converters (e.g., ADCs). In particular, it relates to a ring amplifier circuit and its operating method that employs duplicate bias and bias enhancement techniques. It is a three-stage ring amplifier circuit technology that combines high speed, high energy efficiency, and strong PVT (process, voltage, temperature) robustness. Background Technology

[0002] Operational amplifiers (Op-Amps) are the most core and ubiquitous functional modules in analog and mixed-signal integrated circuits, and their performance directly determines the accuracy, speed, and power consumption of the entire system. In the residual amplification stage of high-speed, high-precision data converters (especially pipelined ADCs), the requirements for operational amplifiers are high, demanding an extreme balance between high gain, wide bandwidth, fast settling, low power consumption, and strong robustness.

[0003] Traditional operational amplifier architectures, such as telescopic and folded-cascode amplifiers, offer high DC gain and good power supply noise rejection ratios, making them a classic choice for achieving high precision. However, as semiconductor process nodes continue to shrink, the intrinsic gain of transistors decreases, making it difficult for these single-stage architectures to maintain sufficient gain at low supply voltages. To address this issue, multi-stage cascaded designs are typically employed, but this introduces complex frequency compensation problems, limiting the amplifier's bandwidth and speed. More importantly, the inherently limited output swing of the cascode structure makes it inefficient in low-voltage designs, hindering the full utilization of the power rails.

[0004] To overcome the speed and power consumption bottlenecks of traditional architectures, the ring amplifier was developed. Essentially, a ring amplifier is an open-loop amplifier composed of a multi-stage (typically three or five-stage) inverter chain, achieving amplification through capacitive feedback during closed-loop operation. Its advantages lie in high speed, high energy efficiency, and a large output swing: as a dynamic circuit, the inverter can provide a large transient current during signal switching, thus the ring amplifier naturally possesses a very high slew rate; simultaneously, its open-loop and dynamic operation characteristics result in extremely low static power consumption, with power efficiency far exceeding that of traditional amplifiers; furthermore, the ring amplifier is not limited by a cascode structure, and its output can approach the power rail, making it ideal for low-voltage designs.

[0005] Despite its significant advantages, existing ring amplifier technology still faces serious challenges: ring amplifiers directly cascade inverters, and their bias points depend entirely on the feedback network and the threshold voltage of the transistors. Lacking a clear definition, they are extremely sensitive to fluctuations in process, voltage, and temperature (PVT), resulting in poor performance consistency, unstable output common-mode voltage, and difficulty in application in commercial products.

[0006] In summary, both traditional high-gain operational amplifiers and existing ring amplifiers have significant shortcomings in simultaneously achieving the key objectives of robust biasing across process, voltage, and temperature (PVT) levels, nanosecond-level rapid setup, high power efficiency, and common-mode output voltage feedback circuit design. Therefore, there is an urgent need in this field for a novel amplifier architecture that can overcome these bottlenecks and provide a solution with superior overall performance. Summary of the Invention

[0007] This invention aims to solve the technical problem of existing ring amplifiers struggling to balance process, voltage, temperature robustness, speed, and power consumption. It provides a ring amplifier circuit employing duplicate bias and bias enhancement techniques, which is a novel three-stage ring amplifier circuit. Through innovative duplicate bias loop and output stage bias enhancement technology, this circuit achieves a comprehensive balance between stable performance under different process, voltage, and temperature conditions and high-speed, high-precision performance requirements.

[0008] The technical solution of the present invention is as follows:

[0009] A ring amplifier circuit employing duplicate bias and bias enhancement techniques includes: a first amplification stage, a second amplification stage, a third amplification stage, a self-zeroing capacitor Caz, a feedback capacitor Cf, a related level shifting capacitor Ccls, and a related level shifting switch; as well as a duplicate bias loop for providing a stable bias voltage to the second amplification stage and an output stage bias enhancement circuit for improving the transient response speed of the third amplification stage.

[0010] Besides the inverter-based single-stage amplifier (first amplification stage, second amplification stage, and third amplification stage); the self-zeroing capacitor Caz for eliminating the offset voltage of the first amplification stage; the feedback capacitor Cf for realizing closed-loop switched capacitor amplification; and the relevant level shifting capacitor and relevant level shifting switch for improving the equivalent open-loop gain, the core of this invention lies in the inclusion of a replica bias loop and an output stage bias enhancement circuit. The replica bias loop provides a process-, voltage-, and temperature-stable bias voltage for the second amplification stage; the replica bias loop includes a replica branch and two auxiliary amplifiers (a first auxiliary amplifier and a second auxiliary amplifier). The second amplification stage adopts an amplification structure based on a dynamic inverter, mainly including a PMOS transistor, an NMOS transistor, two second amplification stage bias capacitors (Cbias), and a second amplification stage bias resistor (Rdz). The specific connection is as follows: the input terminal of the second amplification stage is AC-coupled to the gate of the PMOS transistor and the gate of the NMOS transistor through two second amplification stage bias capacitors (Cbias), respectively; the source of the PMOS transistor is connected to the power supply voltage, and its gate is connected to the first bias voltage (Vb1) terminal through a switch controlled by a self-return-to-zero clock signal (Φaz); the source of the NMOS transistor is connected to ground, and its gate is connected to the second bias voltage (Vb2) terminal through a switch controlled by a self-return-to-zero clock signal (Φaz). Between the drain of the PMOS transistor and the drain of the NMOS transistor, a switch controlled by a ring amplifier amplification phase clock signal (Φa) and a second amplification stage bias resistor (Rdz) are connected in series; the drain of the PMOS transistor and the drain of the NMOS transistor serve as the high output node voltage and low output node voltage of the second amplification stage, respectively. The replica branch has the same circuit structure as the second amplification stage, but its circuit parameters are proportional to 1 / N of the second amplification stage. Specifically, it includes NMOS and PMOS transistors with sizes proportional to 1 / N of the second amplification stage's NMOS and PMOS transistors, and a replica branch bias resistor with a resistance value N times that of the second amplification stage's bias resistor. In the two auxiliary amplifiers, the negative input terminal of the first auxiliary amplifier receives the first reference common-mode voltage (VCM1), and its positive input terminal is connected to the drain of the PMOS transistor in the replica branch. The negative input terminal of the second auxiliary amplifier receives the second reference common-mode voltage (VCM2), and its positive input terminal is connected to the drain of the NMOS transistor in the replica branch. The outputs of the first and second auxiliary amplifiers control the gates of the PMOS and NMOS transistors in the replica branch, forming a negative feedback loop that forces the DC voltages of the two output nodes of the replica branch to stabilize at the first reference common-mode voltage VCM1 and the second reference common-mode voltage VCM2, respectively. In the replica branch, the gate voltages of the PMOS and NMOS transistors are applied to the corresponding transistors of the second amplification stage in the main signal path, thereby providing the second amplification stage with a precise bias point that is independent of process, voltage, and temperature.

[0011] The output stage bias enhancement circuit is used to improve the transient response speed of the third amplification stage. The core of this circuit is the bias resistor Rdz of the second amplification stage and the cross-connection between the output of the second amplification stage and the input of the third amplification stage. The third amplification stage can employ existing technology using a single-stage amplifier based on an inverter. During the amplification stage, the output node at the upper end of the bias resistor Rdz (i.e., the high output node voltage of the second amplification stage) and the output node at the lower end of the bias resistor Rdz (i.e., the low output node voltage of the second amplification stage) drive the gates of the input NMOS and PMOS transistors of the third amplification stage through a special cross-connection method. Specifically, the high output node voltage of the second amplification stage is connected to the input of the NMOS transistor of the third amplification stage, while the low output node voltage of the second amplification stage is connected to the input of the PMOS transistor of the third amplification stage. During the initial transient of the amplification stage, the current flowing through the second amplification stage will generate a significant voltage drop across the bias resistor Rdz of the second amplification stage. This voltage drop is effectively superimposed on the gate-source voltage of the input transistor of the third amplification stage through the aforementioned cross-connection, thereby greatly increasing the overdrive voltage of the third amplification stage, enabling it to provide a larger drive current instantaneously and significantly accelerating the initial slew rate of the ring amplifier.

[0012] In a specific implementation of the present invention, the first amplification stage adopts a bootstrap input switch to achieve highly linear input sampling; the third amplification stage adopts a floating inverter amplifier (FIA) structure to achieve inherent common-mode rejection without a global common-mode feedback loop.

[0013] The operation method of the ring amplifier circuit employing the above-mentioned duplicate bias and bias enhancement techniques specifically includes the following steps:

[0014] Step 1: Self-reset stage

[0015] When the self-zero clock signal Φaz is high, the circuit enters the self-zero phase:

[0016] 11) Close the switch controlled by the self-reset clock signal Φaz, connect the differential input terminal of the first amplifier stage A1 to the differential output terminal of the first amplifier stage, and at the same time reset the input terminal of the ring amplifier, so as to sample the input offset voltage of the first amplifier stage A1 and store it on the self-reset capacitor Caz.

[0017] 12) Activate the two auxiliary amplifiers in the replica bias loop; wherein, the negative input terminal of the first auxiliary amplifier receives the first reference common-mode voltage VCM1, and the positive input terminal is connected to the drain of the PMOS transistor in the replica branch; the negative input terminal of the second auxiliary amplifier is connected to the drain of the NMOS transistor in the replica branch, and the positive input terminal receives the second reference common-mode voltage VCM2.

[0018] 13) Utilize the negative feedback of the two auxiliary amplifiers to adjust the gate voltages of the PMOS transistor and NMOS transistor in the replica branch until the drain voltages of the PMOS transistor and NMOS transistor in the replica branch are stabilized at the first reference common-mode voltage VCM1 and the second reference common-mode voltage VCM2, respectively.

[0019] 14) The gate bias voltage of the PMOS transistor output from the first auxiliary amplifier and the gate bias voltage of the NMOS transistor output from the second auxiliary amplifier are applied to the gates of the PMOS transistor and the NMOS transistor of the second amplification stage A2, respectively, thereby establishing a bias current Irep = (VCM1-VCM2) / (N*Rdz) for the second amplification stage A2, where N is the proportionality coefficient and Rdz is the resistance value of the bias resistor of the second amplification stage.

[0020] Step 2: Scale-up stage

[0021] When the ring amplifier amplifies the phase clock signal Φa to a high level, the circuit enters closed-loop amplification mode:

[0022] 21) Disconnect the switch controlled by the self-zero clock signal Φaz, and close the switch controlled by the amplified phase clock signal Φa of the ring amplifier; the first amplification stage A1 is dynamically activated by the first amplification stage enable control signal Φen;

[0023] 22) The analog input signal from the capacitor digital-to-analog converter (CDAC) is coupled to the first amplification stage A1 through the self-returning capacitor Caz, and then amplified sequentially through the first amplification stage A1, the second amplification stage A2, and the third amplification stage A3. The second amplification stage A2 operates based on the bias voltage established in step 14), and its differential output current flows through the internal second amplification stage bias resistor Rdz, generating an amplified differential voltage at the output of the second amplification stage A2.

[0024] 23) Accelerating setup using bias enhancement technology: At the initial moment of the amplification stage, the large current output by the second amplification stage A2 generates a voltage drop across the bias resistor Rdz; through a cross-connection structure, the high output node voltage Vo2p1 of the positive terminal of the second amplification stage A2 with a higher potential is connected to the gate of the NMOS input transistor at the positive terminal of the third amplification stage A3, and the low output node voltage Vo2p2 of the positive terminal of the second amplification stage with a lower potential is connected to the gate of the PMOS input transistor at the positive terminal of the third amplification stage A3 (the same operation is performed at the negative terminal), thereby increasing the overdrive voltage of the NMOS and PMOS transistors input to the third amplification stage A3 and improving the transient output current.

[0025] Compared with existing conventional operational amplifiers and conventional ring amplifiers, the advantages of this invention include:

[0026] I. Robustness to process, voltage, and temperature: The innovative replica bias loop generates a stable bias point for the core amplification stage that is independent of process, voltage, and temperature through precise negative feedback, ensuring the stability of the amplifier's performance under different process angles, voltages, and temperatures.

[0027] 2. High dynamic amplification speed: The output stage bias enhancement technology is proposed, which uses the voltage drop of the bias resistor in the intermediate stage to dynamically increase the overdrive voltage of the output stage, significantly shortening the amplifier settling time and making it very suitable for high-speed applications.

[0028] 3. High energy efficiency and simplicity: The output stage can adopt a floating inverter amplifier structure, which avoids the global common-mode feedback loop used to stabilize the common mode in traditional designs. This not only saves power consumption and chip area, but also eliminates the speed bottleneck and noise that may be introduced by the common-mode feedback loop.

[0029] IV. Comprehensive Performance Optimization: This invention organically combines multiple advanced technologies and simultaneously solves several core issues such as bias stability, speed, power consumption, and common-mode rejection, providing an amplifier solution with excellent overall performance. Attached Figure Description

[0030] Figure 1 The diagram shows the overall architecture of the ring amplifier circuit employing duplicate bias and bias enhancement techniques in an embodiment of the present invention, and the timing waveforms of the present invention in a typical pipelined analog-to-digital converter (ADC) application.

[0031] The meanings of the markings in the diagram are as follows:

[0032] CDAC: Capacitor-to-Digital Converter

[0033] Caz: Self-returning zero capacitor

[0034] Cf: Feedback capacitor

[0035] CL: Load capacitance

[0036] Ccls: Relevant level shift capacitance

[0037] VCM: Input Common Mode Voltage

[0038] A1: First Amplification Stage

[0039] A2: Second Amplification Stage

[0040] A3: Third amplification stage;

[0041] Φa: The ring amplifier amplifies the phase clock signal;

[0042] Φaz: Self-reset clock signal;

[0043] Φest: Preamplified clock signal for the third amplification stage;

[0044] Φls: Level shift clock signal for the third amplification stage;

[0045] Φen: Enable control signal for the first amplification stage.

[0046] Figure 2 This is a detailed circuit diagram of the first amplification stage A1 of the ring amplifier in an example of the present invention;

[0047] The meanings of the markings in the diagram are as follows:

[0048] Vip1: Differential input voltage at the positive terminal of the first amplifier stage;

[0049] Vin1: Differential input voltage at the negative terminal of the first amplifier stage;

[0050] Vop1: Differential output voltage at the positive terminal of the first amplifier stage;

[0051] Von1: Differential output voltage at the negative terminal of the first amplification stage.

[0052] Figure 3 The detailed circuit structure diagrams of the second amplification stage A2 and the third amplification stage A3 of the ring amplifier circuit in this embodiment of the invention are shown below.

[0053] The meanings of the markings in the diagram are as follows:

[0054] VCM1: First reference common-mode voltage;

[0055] VCM2: Second reference common-mode voltage;

[0056] N*Rdz: Bias resistor for the replica branch;

[0057] Rdz: Bias resistor for the second amplification stage;

[0058] Cbias: Bias capacitor for the second amplification stage;

[0059] Irep: Second amplification stage replica bias current;

[0060] Vb1: First bias voltage;

[0061] Vb2: Second bias voltage;

[0062] Vo2p1: High output node voltage at the positive terminal of the second amplifier stage;

[0063] Vo2n1: High output node voltage at the negative terminal of the second amplifier stage;

[0064] Vo2p2: Low output node voltage at the positive terminal of the second amplifier stage;

[0065] Vo2n2: Low output node voltage at the negative terminal of the second amplifier stage;

[0066] Vop3: Differential output voltage at the positive terminal of the third amplification stage.

[0067] Von3: Differential output voltage at the negative terminal of the third amplification stage. Detailed Implementation

[0068] The present invention will be further described below with reference to the accompanying drawings and embodiments, but the scope of the invention is not limited in any way.

[0069] This invention provides a ring amplifier circuit and its operating method employing duplicate biasing and bias enhancement techniques. The circuit is a three-stage ring amplifier circuit, comprising a first amplification stage A1, a second amplification stage A2, and a third amplification stage A3 cascaded sequentially. The core of this circuit lies in the integration of a duplicate biasing loop and an output stage bias enhancement circuit.

[0070] The three-stage ring amplifier circuit provided by this invention includes a replica bias loop that provides a process-, voltage-, and temperature-stable bias voltage for the second amplification stage A2. This replica bias loop consists of a replica branch and two auxiliary amplifiers (a first auxiliary amplifier and a second auxiliary amplifier, respectively). The replica branch has the same circuit structure as the second amplification stage A2, but its circuit parameters are in a 1 / N ratio. That is, the replica branch includes NMOS and PMOS transistors with sizes in a 1 / N ratio to the NMOS and PMOS transistors of the second amplification stage A2, and a replica branch bias resistor N*Rdz with a resistance value N times that of the second amplification stage bias resistor. Of the two auxiliary amplifiers, the negative input terminal of the first auxiliary amplifier receives a first reference common-mode voltage (VCM1), and its positive input terminal is connected to the drain of the PMOS transistor in the replica branch, outputting a first bias voltage Vb1; the negative input terminal of the second auxiliary amplifier receives a second reference common-mode voltage (VCM2), and its positive input terminal is connected to the drain of the NMOS transistor in the replica branch, outputting a second bias voltage Vb2. The outputs of the first and second auxiliary amplifiers control the gates of the PMOS and NMOS transistors in the replica branch, respectively, forming negative feedback. This forces the DC voltages at the upper and lower output nodes of the replica branch bias resistor to stabilize at the first reference common-mode voltage VCM1 and the second reference common-mode voltage VCM2, respectively. At this time, the gate voltages of the PMOS and NMOS transistors in the replica branch are applied to the PMOS and NMOS transistors of the second amplification stage A2, respectively, thus providing the second amplification stage A2 with a precise bias point independent of process, voltage, and temperature.

[0071] The three-stage ring amplifier circuit provided by this invention also includes an output stage bias enhancement circuit for improving the transient response speed of the third amplification stage A3. The core of this output stage bias enhancement circuit is a second amplification stage bias resistor Rdz connected in series between the PMOS and NMOS transistors of the second amplification stage A2. During the amplification stage, the two differential output nodes of the second amplification stage A2 drive the gate of the input transistor of the third amplification stage A3 through a special cross-connection method. Specifically, the output node with a larger voltage at the upper end of the second amplification stage bias resistor Rdz is connected to the NMOS transistor input of the third amplification stage A3, while the output node with a smaller voltage at the lower end of the second amplification stage bias resistor Rdz is connected to the PMOS transistor input of the third amplification stage A3. During the initial transient period of the amplification stage, the differential current flowing through the second amplification stage A2 generates a significant voltage drop across the second amplification stage bias resistor Rdz. This voltage drop is superimposed on the gate-source voltage of the input transistor of the third amplification stage A3 through the aforementioned cross-connection, thereby effectively increasing the overdrive voltage of A3. This allows the third amplification stage to provide a larger drive current instantaneously, significantly accelerating the initial slew rate of the amplifier.

[0072] like Figure 1 As shown, the ring amplifier in this embodiment is composed of a first amplification stage A1, a second amplification stage A2, and a third amplification stage A3 cascaded together, and is controlled by a series of non-overlapping clock signals (including the ring amplifier amplification phase clock signal Φa, the self-reset clock signal Φaz, the third amplification stage pre-amplification clock signal Φest, and the third amplification stage level shift clock signal Φls). The input voltage of the ring amplifier's pre-stage (such as a capacitor digital-to-analog converter CDAC) is coupled through the self-reset capacitor Caz, and a closed-loop amplification structure is formed through the feedback capacitor Cf. The overall operation of the ring amplifier is divided into two main stages: the self-reset stage controlled by the self-reset clock signal Φaz and the amplification stage controlled by the ring amplifier amplification phase clock signal Φa.

[0073] Self-reset phase (self-reset clock signal Φaz is high, ring amplifier amplifies phase clock signal Φa to low):

[0074] During this clock phase, the amplifier prepares for subsequent precise amplification. (Refer to...) Figure 2 When the switch controlled by the self-reset clock signal Φaz is closed, the differential input voltage at the positive terminal of the first amplifier stage and the differential output voltage at the negative terminal of the first amplifier stage are shorted together, and the differential input voltage at the negative terminal of the first amplifier stage is shorted together with the differential output voltage at the negative terminal of the first amplifier stage. The offset voltage of the amplifier is sampled to eliminate the offset voltage in the first amplifier stage A1 caused by device mismatch.

[0075] at the same time, Figure 3The replica bias loop shown begins operation. The core of this loop is the circuit labeled "Replica Bias Loop." Two operational amplifiers, labeled "First Auxiliary Amplifier" and "Second Auxiliary Amplifier," are activated. The negative input of the first auxiliary amplifier is connected to the first reference common-mode voltage VCM1, and its positive input is connected to the drain voltage of the PMOS transistor in the replica branch. The output voltage of the first auxiliary amplifier is the first bias voltage (Vb1). The negative input of the second auxiliary amplifier is connected to the second reference common-mode voltage VCM2, and its positive input is connected to the drain voltage of the NMOS transistor in the replica branch. The output of the second auxiliary amplifier is the second bias voltage (Vb2). Through negative feedback, the output voltages of the first and second auxiliary amplifiers respectively adjust the gate voltages of the PMOS and NMOS transistors in the replica branch until their gate voltages are precisely clamped to the first and second reference common-mode voltages VCM1 and VCM2, respectively. At this point, the gate voltages of the PMOS and NMOS transistors in the replica branch are sufficient to generate a process-, voltage-, and temperature-insensitive replica bias current Irep = (VCM1-VCM2) / (N*Rdz). The gate voltages of the PMOS and NMOS transistors in the replica branch (i.e., the first bias voltage Vb1 and the second bias voltage Vb2) are applied to the gates of the PMOS and NMOS transistors in the second amplification stage A2, respectively, thereby setting a precise and robust operating point for the second amplification stage A2 in the upcoming amplification phase.

[0076] Amplification stage (the ring amplifier amplifies the phase clock signal Φa at a high level, and the self-reset clock signal Φaz at a low level):

[0077] During this clock phase, the ring amplifier performs signal amplification. The ring amplifier amplifies the phase clock signal Φa to a high level, and the amplifier is configured in closed-loop amplification mode. The input signal from the right plate of the capacitor-to-analog converter is coupled into the input through the self-returning capacitor Caz. The three-stage circuit of the first amplification stage A1, the second amplification stage A2, and the third amplification stage A3 amplify the signal sequentially.

[0078] The detailed structure of the first amplification stage A1 is as follows: Figure 2 As shown, it employs a differential amplifier structure with dynamic enable. The first amplifier stage enable control signal Φen (generated by the OR logic of the self-reset clock signal Φaz and the ring amplifier amplified phase clock signal Φa) controls two switches that dynamically enable the first amplifier stage current bias. When neither the amplification stage nor the self-reset stage is in progress, the power supply to the first amplifier stage A1 is cut off, thereby reducing power consumption when the first amplifier stage A1 is not operating. The detailed structure of the second amplifier stage A2 is shown below. Figure 3As shown in the diagram, the second amplifier stage A2 receives the differential output voltage Vop1 at the positive terminal and the differential output voltage Von1 at the negative terminal of the first amplifier stage, and amplifies it according to the stable bias established during the self-reset phase. The output current of the second amplifier stage A2 flows through the bias resistor Rdz of the second amplifier stage, thereby generating the output voltage at the positive terminal of the second amplifier stage between the high output node voltage Vo2p1 at the positive terminal and the low output node voltage Vo2p2 at the positive terminal of the second amplifier stage, and simultaneously generating the output voltage at the negative terminal of the second amplifier stage between the high output node voltage Vo2n1 at the negative terminal and the low output node voltage Vo2n2 at the negative terminal of the second amplifier stage.

[0079] The output stage bias enhancement technique is the key inventive point of this invention. For example... Figure 3 As shown in the dashed box labeled "Output Stage Bias Enhancement," a special cross-connection is used between the output of the second amplifier stage A2 and the input of the third amplifier stage A3. At the instant the amplification phase begins, the differential input voltage of the first amplifier stage causes a large differential output current in the second amplifier stage A2. When this current flows through the bias resistor Rdz of the second amplifier stage, it creates a significant instantaneous voltage drop across the resistor. Taking the positive terminal of the second amplifier stage as an example, the voltage at the high output node Vo2p1 at the positive terminal of the second amplifier stage will be higher than the voltage at the low output node Vo2p2. Because a special cross-connection is used between the output of the second amplifier stage A2 and the input of the third amplifier stage A3, the higher voltage of the second amplifier stage's positive terminal high output node voltage Vo2p1 drives the NMOS input transistor of the third amplifier stage A3, while the lower voltage of the second amplifier stage's positive terminal low output node voltage Vo2p2 drives the PMOS input transistor of the third amplifier stage A3. Therefore, the gate-source voltage of the NMOS transistor in the third amplifier stage A3 becomes higher, thus turning it on more strongly; at the same time, the absolute value of the gate-source voltage of the PMOS input transistor in the third amplifier stage A3 also becomes higher, similarly turning it on more strongly. This is equivalent to instantaneously and greatly increasing the overdrive voltage of the input transistor in the third amplifier stage A3, enabling the third amplifier stage to output a larger current, thereby achieving a faster initial slewing rate and significantly accelerating the voltage build-up process of the ring amplifier.

[0080] like Figure 3As shown, the third amplification stage A3 employs a floating inverter amplifier (FIA) structure. A floating inverter amplifier is a discrete-time amplifier whose basic structure consists of a pair of differential inverters and several power supply capacitors. During the reset phase of the floating inverter amplifier, the power supply capacitors are pre-charged to the power supply voltage and ground voltage, respectively. Once the amplification phase begins, the differential inverter pair is connected to the power supply capacitors, and the differential inverters are powered by the power supply capacitors. The floating inverter amplifier structure itself has an inherent common-mode stabilization mechanism, and its output common-mode voltage is stabilized near the middle of the power supply voltage. Therefore, using a floating inverter amplifier in the third amplification stage eliminates the need for a complex global common-mode feedback circuit, which is required by traditional amplifiers. This not only simplifies the design, saves power consumption and chip area, but also avoids the speed bottleneck and additional noise that common-mode feedback loops may introduce.

[0081] In summary, this invention ensures stable operation of the amplifier under various process, voltage, and temperature conditions through a duplicate bias loop, overcomes the speed bottleneck of traditional designs through bias enhancement technology, and achieves high energy efficiency by utilizing a floating inverter amplifier structure, thus forming a high-speed ring amplifier with superior overall performance.

[0082] It should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the scope of the claims.

Claims

1. A ring amplifier circuit employing duplicate bias and bias enhancement techniques, characterized in that, It includes a first amplification stage, a second amplification stage, and a third amplification stage cascaded in sequence; the first amplification stage, the second amplification stage, and the third amplification stage are all single-stage amplifiers based on inverters, and adopt an amplification structure based on dynamic inverters; The ring amplifier circuit further includes a replica bias loop and an output stage bias enhancement circuit; wherein: The replica bias loop provides a stable bias voltage for the second amplification stage and includes a replica branch, a first auxiliary amplifier, and a second auxiliary amplifier. The circuit structure of the replica branch is the same as that of the second amplification stage, and the circuit parameters of the replica branch are proportional to 1 / N of those of the second amplification stage. The negative input of the first auxiliary amplifier receives a first reference common-mode voltage VCM1, and the positive input of the first auxiliary amplifier is connected to the drain of the PMOS transistor in the replica branch. The negative input of the second auxiliary amplifier receives a second reference common-mode voltage VCM2, and the positive input of the second auxiliary amplifier is connected to the drain of the NMOS transistor in the replica branch. The outputs of the first and second auxiliary amplifiers control the gates of the PMOS and NMOS transistors in the replica branch, respectively, forming a negative feedback loop that forces the DC voltages of the two output nodes of the replica branch to stabilize at the first reference common-mode voltage VCM1 and the second reference common-mode voltage VCM2, respectively. The gate voltages of the PMOS and NMOS transistors in the replica branch are applied to the corresponding transistors of the second amplification stage in the main signal path, respectively, to provide a process-, voltage-, and temperature-stable bias voltage for the second amplification stage. The output stage bias enhancement circuit includes a second amplification stage bias resistor connected in series between the PMOS and NMOS transistors of the second amplification stage, and a cross-connection method from the output of the second amplification stage to the input of the third amplification stage, used to improve the transient response speed of the third amplification stage. During the amplification stage, the high output node voltage and the low output node voltage of the second amplification stage drive the gates of the input NMOS and PMOS transistors of the third amplification stage through the cross-connection method. Specifically, the high output node voltage of the second amplification stage is connected to the input of the NMOS transistor of the third amplification stage, while the low output node voltage of the second amplification stage is connected to the input of the PMOS transistor of the third amplification stage. During the initial transient period of the amplification stage, the current flowing through the second amplification stage generates a significant voltage drop across the second amplification stage bias resistor, which is effectively superimposed on the gate-source voltage of the input transistor of the third amplification stage through the cross-connection, thereby increasing the overdrive voltage of the third amplification stage.

2. The ring amplifier circuit employing duplicate bias and bias enhancement techniques as described in claim 1, characterized in that, The ring amplifier circuit further includes: a self-zeroing capacitor for eliminating the offset voltage of the first amplification stage; a feedback capacitor for realizing closed-loop switched capacitor amplification; a related level shifting capacitor and a related level shifting switch for improving the equivalent open-loop gain.

3. The ring amplifier circuit employing duplicate bias and bias enhancement techniques as described in claim 1, characterized in that, The first amplification stage uses a bootstrap input switch; the third amplification stage uses a floating inverter amplifier structure.

4. The ring amplifier circuit employing duplicate bias and bias enhancement techniques as described in claim 1, characterized in that, The second amplification stage includes a PMOS transistor, an NMOS transistor, two second amplification stage bias capacitors, and a second amplification stage bias resistor; the input terminal of the second amplification stage is AC coupled to the gate of the PMOS transistor and the gate of the NMOS transistor through the two second amplification stage bias capacitors, respectively. The source of the PMOS transistor is connected to the power supply voltage, and its gate is connected to the first bias voltage terminal via a switch controlled by a self-reset clock signal. The source of the NMOS transistor is connected to ground, and its gate is connected to the second bias voltage terminal via a switch controlled by a self-reset clock signal. Between the drains of the PMOS transistor and the NMOS transistor, a switch controlled by a ring amplifier amplification phase clock signal and a second amplification stage bias resistor are connected in series. The drains of the PMOS transistor and the NMOS transistor serve as the high output node voltage and low output node voltage of the second amplification stage, respectively.

5. The ring amplifier circuit employing duplicate bias and bias enhancement techniques as described in claim 4, characterized in that, The circuit parameters of the replica branch are proportional to the second amplification stage by 1 / N. Specifically, it includes NMOS and PMOS transistors whose sizes are proportional to the NMOS and PMOS transistors of the second amplification stage by 1 / N, and a replica branch bias resistor whose resistance is N times that of the second amplification stage bias resistor.

6. The ring amplifier circuit employing duplicate bias and bias enhancement techniques as described in claim 4, characterized in that, The operation method of the ring amplifier circuit includes the following steps: When the self-zero clock signal is high, the circuit enters the self-zero phase, including: 11) Close the switch controlled by the self-reset clock signal to connect the differential input terminal of the first amplifier stage to the differential output terminal of the first amplifier stage. At the same time, the input terminal of the ring amplifier is reset, thereby sampling the input offset voltage of the first amplifier stage and storing it on the self-reset capacitor. 12) Activate the two auxiliary amplifiers in the replica bias loop; wherein, the negative input terminal of the first auxiliary amplifier receives the first reference common-mode voltage VCM1, and the positive input terminal is connected to the drain of the PMOS transistor in the replica branch; the negative input terminal of the second auxiliary amplifier is connected to the drain of the NMOS transistor in the replica branch, and the positive input terminal receives the second reference common-mode voltage VCM2. 13) Utilize the negative feedback of the two auxiliary amplifiers to adjust the gate voltages of the PMOS transistor and NMOS transistor in the replica branch until the drain voltages of the PMOS transistor and NMOS transistor in the replica branch are stabilized at the first reference common-mode voltage VCM1 and the second reference common-mode voltage VCM2, respectively. 14) The gate bias voltage of the PMOS transistor output by the first auxiliary amplifier and the gate bias voltage of the NMOS transistor output by the second auxiliary amplifier are applied to the gates of the PMOS transistor and the NMOS transistor of the second amplification stage A2, respectively, thereby establishing a bias current for the second amplification stage A2. When the ring amplifier amplifies the phase clock signal to a high level, the circuit enters closed-loop amplification mode, including: 21) Disconnect the switch controlled by the self-zero clock signal and close the switch controlled by the amplified phase clock signal of the ring amplifier; the first amplification stage is dynamically activated by the first amplification stage enable control signal; 22) The analog input signal from the capacitor digital-to-analog converter is coupled to the first amplification stage through a self-returning capacitor, and then amplified sequentially through the first amplification stage, the second amplification stage, and the third amplification stage; wherein, the second amplification stage operates based on the bias voltage, and its differential output current flows through the internal bias resistor of the second amplification stage, generating an amplified differential voltage at the output of the second amplification stage. 23) Accelerating setup using bias enhancement technology: At the initial moment of the amplification stage, the large current output of the second amplification stage generates a voltage drop across the bias resistor; through a cross-connection structure, the high output node voltage of the positive terminal of the second amplification stage with a higher potential is connected to the gate of the positive terminal NMOS input transistor of the third amplification stage, and the low output node voltage of the positive terminal of the second amplification stage with a lower potential is connected to the gate of the PMOS input transistor of the third amplification stage. The negative terminal performs the same operation, thereby increasing the overdrive voltage of the input NMOS and PMOS transistors of the third amplification stage and improving the transient output current.

7. The ring amplifier circuit employing duplicate bias and bias enhancement techniques as described in claim 6, characterized in that, In step 14), the bias current Irep established for the second amplification stage is expressed as: Irep = (VCM1-VCM2) / (N*Rdz), Wherein, VCM1 is the first reference common-mode voltage; VCM2 is the second reference common-mode voltage; N is the proportional coefficient; and Rdz is the resistance value of the bias resistor for the second amplification stage.

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