Imaging device and control method thereof

Abstract

This disclosure provides an imaging apparatus and its control method. The imaging apparatus includes at least one pixel array; the pixel array includes at least two subarrays, each subarray including at least two pixel rows; the imaging apparatus is configured to: in an exposure mode, acquire imaging data; in a transfer mode, transfer and output the imaging data; wherein, the pixel array transferring and outputting the imaging data includes: in response to a first control signal, transferring one piece of data to be filtered from each of the at least two subarrays, the data to be filtered being imaging data within a pixel row of a subarray; in response to a second control signal, filtering out target data from the data to be filtered transferred from the at least two subarrays; and in response to a third control signal, transferring the target data to a next-level pixel array, or transferring the target data transferred from a previous-level pixel array to a next-level pixel array, or outputting the target data.

Description

Technical Field

[0001] This disclosure relates to the field of imaging technology, and in particular to an imaging device and its control method. Background Technology

[0002] With the development of single-photon avalanche diode (SPAD) device manufacturing technology and integrated circuits, SPAD-based photon counting imaging (PCI) technology has been applied. In a SPAD-based PCI image sensor, each pixel unit has an independent SPAD, quenching circuit, and counting circuit, which replicates and expands the pixel units into an array of photosensitive areas. Simultaneously, readout circuits, control circuits, and other components are connected outside the photosensitive area array, collectively forming a PCI image sensor capable of capturing optical images of a target.

[0003] After exposure, the count value of the counting circuit in the PCI image sensor can provide feedback on the light intensity information of the optical target. The count value of a single pixel reflects the light intensity of a single point target, while the count value counted by the two-dimensional pixel array can depict a digital image of the target's field of view.

[0004] SPAD PCI image sensors can read the count value of each pixel in the pixel array from the pixel array and transmit it to the downstream signal array module. Existing SPAD PCI image sensors read the count value of each pixel in the pixel array based on a cascaded readout circuit. However, the excessive length of the cascaded structure will lead to excessive delay in reading the pixel count value, and the failure of any node in the cascaded structure will prevent the pixel count values ​​of multiple rows before the failed node from being transferred through that failed node. In other words, the failure risk of the cascaded structure is high. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide an imaging device and a control method thereof.

[0006] To achieve the above objectives, the technical solution disclosed herein is implemented as follows: In a first aspect, embodiments of this disclosure provide an imaging apparatus, the imaging apparatus including at least one pixel array; the pixel array including at least two subarrays, the subarrays including at least two pixel rows; the imaging apparatus is configured to: in an exposure mode, the pixel array acquires imaging data; in a transfer mode, the pixel array transfers and outputs the imaging data; wherein, the pixel array transferring and outputting the imaging data includes: in response to a first control signal, transferring one piece of data to be filtered from each of the at least two subarrays, the data to be filtered being imaging data within a pixel row of the subarray; in response to a second control signal, filtering target data from the data to be filtered transferred from the at least two subarrays; and in response to a third control signal, transferring the target data to a next-level pixel array, or transferring the target data transferred from a previous-level pixel array to a next-level pixel array, or outputting the target data.

[0007] In some embodiments, the imaging device includes a primary selector corresponding to the number of subarrays, the control terminal of the primary selector is connected to the first control signal, the input terminal of the primary selector is connected to the signal output terminal of each pixel row in the corresponding subarray, and the output terminal of the primary selector outputs the data to be filtered in the subarray.

[0008] In some embodiments, the imaging device further includes a secondary selector corresponding to the number of pixel arrays. The control terminal of the secondary selector is connected to the second control signal, the input terminal of the secondary selector is connected to the output terminal of the primary selector corresponding to each subarray in the pixel array, and the output terminal of the secondary selector outputs the target data in the corresponding pixel array.

[0009] In some embodiments, the imaging device further includes a cascade selector corresponding to the number of pixel arrays. The control terminal of the cascade selector is connected to the third control signal. The input terminal of the cascade selector is connected to the output terminal of the secondary selector corresponding to the pixel array and the output terminal of the cascade selector corresponding to the previous pixel array. The output terminal of the cascade selector is connected to the input terminal of the cascade selector corresponding to the next pixel array or directly outputs the target data.

[0010] In some embodiments, at least two subarrays within the same pixel array have the same number of pixel rows, and the first-level selectors corresponding to the subarrays with the same number of pixel rows within the same pixel array simultaneously respond to the same first control signal.

[0011] In some embodiments, the number of pixel rows in each subarray within the same pixel array is the same and equal to the number of subarrays within the pixel array.

[0012] In some embodiments, at least two subarrays within the same pixel array have different numbers of pixel rows, and the first-level selectors corresponding to the subarrays with different numbers of pixel rows within the same pixel array simultaneously respond to different first control signals.

[0013] In some embodiments, the number of pixel rows in each subarray within the same pixel array varies regularly, and the first control signal connected to the first-level selector corresponding to each subarray within the same pixel array also varies regularly.

[0014] In some embodiments, the imaging device further includes a shift register module, and the imaging device is further configured such that a reset signal is connected to an input terminal of the cascade selector corresponding to the pixel array furthest from the shift register module.

[0015] Secondly, embodiments of this disclosure provide a control method for an imaging device, applied to an imaging device including at least one pixel array, the pixel array including at least two sub-arrays, and the sub-arrays including at least two pixel rows; the control method includes: in an exposure mode, controlling the pixel array to acquire imaging data; in a transfer mode, controlling at least two of the sub-arrays to transfer out one piece of data to be filtered, the data to be filtered being imaging data within one pixel row of the sub-array; filtering out target data from the data to be filtered transferred out from the at least two sub-arrays; transferring the target data to a next-level pixel array, or transferring the target data transferred out from a previous-level pixel array to a next-level pixel array, or outputting the target data.

[0016] This disclosure provides an imaging apparatus and its control method. The imaging apparatus includes at least one pixel array; the pixel array includes at least two subarrays, each subarray including at least two pixel rows; the imaging apparatus is configured to: in an exposure mode, the pixel array acquires imaging data; in a transfer mode, the pixel array transfers and outputs the imaging data; wherein, the pixel array transferring and outputting the imaging data includes: in response to a first control signal, transferring one piece of data to be filtered from each of the at least two subarrays, the data to be filtered being imaging data within a pixel row of the subarray; in response to a second control signal, filtering target data from the data to be filtered transferred from the at least two subarrays; and in response to a third control signal, transferring the target data to a next-level pixel array, or transferring the target data transferred from a previous-level pixel array to a next-level pixel array, or outputting the target data. This embodiment of the disclosure, by reasonably setting pixel grouping and selector cascading methods, changes the traditional SPAD array method of selecting a pixel row by row selection signal and then transmitting the imaging data in that pixel row down row by row until output. Instead, it uses a method of multiple "multiple selections" in multiple subarrays of the SPAD array to filter the target data in the target pixel row. This transforms the traditional cascading circuit structure between rows into a cascading circuit structure between groups, thereby significantly reducing the number of cascading nodes. This effectively alleviates the problem of excessive latency caused by an excessive number of cascading selectors due to an excessive number of cascading nodes, and also effectively reduces the risk of cascading node failure. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the traditional readout circuit architecture of an imaging device in related technologies. Figure 2 This is a simplified schematic diagram of the traditional readout circuit architecture of imaging devices in related technologies; Figure 3 for Figure 2 A magnified view of a portion of the mid-pixel array; Figure 4 A schematic diagram of a pixel array in an imaging device provided in an embodiment of this disclosure; Figure 5 This is a schematic diagram of a grouped cascaded circuit for a pixel array provided in an embodiment of the present disclosure; Figure 6 A schematic diagram illustrating the steps of a control method for an imaging apparatus provided in an embodiment of this disclosure. Detailed Implementation

[0018] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0019] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0020] Figure 1 This is a schematic diagram of a conventional readout circuit architecture for an imaging device in related technologies. The imaging device typically includes a SPAD array 11 and control circuitry. For example... Figure 1 As shown, the SPAD array 11 includes multiple pixels 14 arranged in a matrix. The control circuit includes a row selection circuit 12 and a shift register circuit 13. The row selection circuit 12 enables the row selection signal of the target pixel row to select the target data within the target pixel row for transfer and transmission. The shift register circuit 13 temporarily stores the target data transmitted through multiple levels of pixel rows and transfers it to the subsequent circuit. Here, the pixel 14 may include a photodiode (PD), an amplifier, and a transistor. It should be noted that the specific structure of the pixel 14 is not limited to... Figure 1 The structure shown.

[0021] Figure 2 This is a simplified schematic diagram of the traditional readout circuit architecture of imaging devices in related technologies. Figure 3 for Figure 2 A magnified view of a portion of the pixel array. (e.g.) Figure 2 As shown, the image sensor includes a pixel array and a readout circuit. The pixel array includes multiple pixel rows ROW1, ... ROW1. n-1 ROW n ROW n+1 Or, in other words, the pixel array includes multiple pixel columns COL1, ... COL n-1 COL n COL n+1 The readout circuit includes a row selection module 21 and a shift register module 22. The row selection module 21 controls a row of pixel units 23 to perform an imaging data (count value) transfer step by controlling the row selection signal corresponding to the pixel row. For example, when a ROW transfer is required... n When the count value is within the range, row selection module 21 enables ROW. n The corresponding row selection signal.

[0022] In a pixel array, adjacent pixel units 23 in the same column are cascaded to achieve count value transfer; this cascading relationship can be implemented using a selector. Specifically, as shown... Figure 3 As shown, the output of each pixel unit 23 in the pixel array is connected to the input of a selector 24. In each column, the output of the selector 24 corresponding to the previous pixel unit 23 is connected to the input of the selector 24 corresponding to the next pixel unit 23. When ROW n Once selected, it will be located in [ROW] n COL n The count value in the pixel at position [ROW] will be transferred to the pixel at position [ROW]. n-1 COL n In the pixels at position ]; then ROW n-1 When selected, the count value is taken from [ROW] n-1 COL n Transfer the pixel at position [ROW] to the pixel at position [ROW] n-2 COL n In the pixels at position [ROW1, COL]. Continue in this manner until the pixel is moved to [ROW1, COL]. n The pixel at position ] is ultimately sampled by the downstream shift register module 22. Here, the shift register module 22 may include a shift register Shift Reg. For ROW n For each pixel, its imaging data (count values) needs to be transferred and read out through N cascaded selectors. The cascade relationship involves N nodes. An excessively long cascade structure leads to excessive delays in reading out pixel count values, and the failure of any single node prevents the transfer of pixel count values ​​from multiple rows preceding that node. In other words, the readout circuit of the cascade structure has a high failure risk. In a specific example, assuming the probability of each cascaded node failing is p, then the probability of all nodes functioning correctly is (1-p). N .

[0023] During the transfer, ROW n The count value is transferred to ROW n-1 The delay is D mux This refers to the transmission delay of the cascaded selector. ROW... n The count value eventually needs to go through n transfers to be transferred out of the pixel array, so ROW n The delay for transferring the count value out of the pixel array is n×D mux +D sel , where D sel The row selection signal enable delay.

[0024] Similarly, the readout delay for transferring an N-line image is given by the following formula (1): (1) Taking a 1080P resolution image as an example, N = 1080, assuming D mux For 0.5 ns, D sel If the readout delay is 5ns, then the readout delay is approximately 300µs. In actual image sensors, D... mux and D sel The latency may be even greater, and as the application requirements for image resolution develop, the value of N will increase by 3 to 5 times, further increasing the image readout latency.

[0025] Frame rate is one of the important performance indicators of an image sensor. Frame rate can generally be expressed as 1 / (T) E +T readout +T output ). Among them, T E It's the exposure time, T readout It is the readout time, also known as the readout delay, T. output This is the output time. Readout time T readout Excessive speed will severely reduce the frame rate of the image sensor, affecting the user's visual experience.

[0026] In view of this, embodiments of the present disclosure provide an imaging device and a control method thereof.

[0027] Figure 4 This is a schematic diagram of a pixel array in an imaging apparatus provided in an embodiment of this disclosure. (Refer to...) Figure 4 The imaging apparatus includes at least one pixel array 10; the pixel array 10 includes at least two subarrays 20, each subarray 20 including at least two pixel rows; the imaging apparatus is configured to: in an exposure mode, the pixel array 10 acquires imaging data; in a transfer mode, the pixel array 10 transfers and outputs the imaging data; wherein the pixel array 10 transfers and outputs the imaging data includes: in response to a first control signal, transferring one piece of data to be filtered from each of the at least two subarrays 20, the data to be filtered being imaging data within a pixel row of the subarray 20; in response to a second control signal, filtering out target data from the data to be filtered transferred from the at least two subarrays 20; in response to a third control signal, transferring the target data to the next level pixel array 10, or transferring the target data transferred from the previous level pixel array 10 to the next level pixel array 10, or outputting the target data.

[0028] This embodiment of the disclosure, by reasonably setting pixel grouping and selector cascading methods, changes the traditional SPAD array method of selecting a pixel row by row selection signal and then transmitting the imaging data in that pixel row down row by row until output. Instead, it uses a method of multiple "multiple selections" in multiple subarrays of the SPAD array to filter the target data in the target pixel row. This transforms the traditional cascading circuit structure between rows into a cascading circuit structure between groups, thereby significantly reducing the number of cascading nodes. This effectively alleviates the problem of excessive latency caused by an excessive number of cascading selectors due to an excessive number of cascading nodes, and also effectively reduces the risk of cascading node failure.

[0029] The present invention will be illustrated in detail below with reference to specific embodiments.

[0030] In some embodiments, reference Figure 4 Pixel array 10 can be a 16×16 SPAD pixel array, comprising four subarrays 20, each subarray 20 comprising four pixel rows. Each subarray 20 includes ROW0 to ROW3, ​​ROW4 to ROW7, ROW8 to ROW11, and ROW12 to ROW15, respectively, and each pixel row includes 16 pixel units. It should be noted that... Figure 4 The number of pixel units, the number of subarrays, and the grouping of the pixel array 10 are not intended to limit this disclosure.

[0031] In a specific example, refer to Figure 4 The imaging device is configured to: in response to a first control signal, transfer one piece of data to be screened from each of the four subarrays 20 (exemplarily, imaging data within ROW0, ROW4, ROW8, and ROW12); in response to a second control signal, screen target data (exemplarily, imaging data within ROW8) from the four pieces of data to be screened, i.e., screen target data from the pixel array 10 through two-stage screening. Then, in response to a third control signal, transfer the target data to the next-level pixel array 10, or directly output the target data, or transfer the target data transferred from the previous-level pixel array 10 to the next-level pixel array 10.

[0032] It is understandable that when the SPAD array of the imaging device contains only one of the aforementioned pixel arrays 10, the imaging device can directly output target data in response to the third control signal.

[0033] When the entire SPAD array of the imaging device comprises multiple pixel arrays 10, and the current pixel array 10 is the last pixel array 10 in the entire SPAD array (the pixel array closest to the shift register module), the imaging device can directly output target data in response to the third control signal, or output target data transferred from the previous pixel array 10. Specifically, when the current pixel array 10 is the last pixel array 10 in the entire SPAD array and is the target pixel array 10, the imaging device can directly output the target data in the target pixel array 10 in response to the third control signal. Alternatively, when the current pixel array 10 is the last pixel array 10 in the entire SPAD array and is located after the target pixel array 10, the imaging device can output the target data transferred from the previous pixel array 10 in response to the third control signal.

[0034] When the entire SPAD array of the imaging device comprises multiple pixel arrays 10, and the current pixel array 10 is located before the last pixel array 10 in the entire SPAD array, the target data in the current pixel array 10 can be transferred to the next pixel array 10 in response to the third control signal, or the target data transferred from the previous pixel array 10 can be transferred to the next pixel array 10. Specifically, when the current pixel array 10 is located before the last pixel array 10 in the entire SPAD array and is the target pixel array 10, the target data in the current pixel array 10 can be transferred to the next pixel array 10 in response to the third control signal. Alternatively, when the current pixel array 10 is located before the last pixel array 10 in the entire SPAD array and is located after the target pixel array 10, the target data transferred from the previous pixel array 10 can be transferred to the next pixel array 10 in response to the third control signal.

[0035] In this embodiment, the imaging device filters target data from multiple subarrays of a pixel array through a two-stage screening process, and transmits the target data between multiple pixel arrays in a cascaded manner until output. That is, the two-stage screening in this disclosure reduces the number of cascaded nodes for reading out imaging data to the same number of pixel arrays, significantly reducing the number of cascaded nodes and thus lowering the image readout latency and the risk of cascaded node failure.

[0036] In some embodiments, Figure 5 This is a schematic diagram of a grouped cascaded circuit for a pixel array provided in an embodiment of this disclosure. (Reference) Figure 5Each pixel array 10 of the imaging device includes a primary selector 51 corresponding to the number of sub-arrays. The control terminal of the primary selector 51 is connected to the first control signal sel[1:0]. The input terminal of the primary selector 51 is connected to the signal output terminal of each pixel row in the corresponding sub-array 20. The output terminal of the primary selector 51 outputs the data to be filtered in the sub-array 20.

[0037] In some embodiments, reference Figure 4 and Figure 5 Taking an example where each subarray 20 includes 4 pixel rows and each first-level selector 51 includes 4 input terminals, the first control signal can be a 2-bit control signal. Under the control of the first control signal, the first-level selector 51 outputs the data to be filtered (i.e., the imaging data in the pixel rows to be filtered) within the corresponding subarray 20. It can be understood that among the 4 data to be filtered in the 4 subarrays 20 contained in each pixel array 10, one of the data to be filtered is target data, and the rest are invalid data. Furthermore, only the target data in the target pixel array 10 of at least one pixel array can be transferred to the next level pixel array 10, while the target data in other pixel arrays 10 are invalid data. For example, each first-level selector 51 outputs the data to be filtered in ROW3, ​​ROW7, ROW11, and ROW15 respectively in response to the first control signal sel[1:0]. It should be noted that the number of bits of the first control signal can be set according to the number of pixel rows in each subarray 20. The more pixel rows in each subarray 20, the larger the number of bits of the first control signal.

[0038] In some embodiments, such as Figure 4 As shown, each primary selector 51 is used to receive imaging data within multiple pixel rows in the corresponding subarray 20 (or imaging data within a single pixel unit in each pixel row of the subarray 20). Specifically, the primary selectors 51 corresponding to ROW0 to ROW3 are used to receive imaging data within ROW0, ROW1, ROW2, and ROW3, ​​collectively referred to as ROW[3:0]; similarly, the primary selectors 51 corresponding to ROW4 to ROW7 are used to receive ROW[7:4], the primary selectors 51 corresponding to ROW8 to ROW11 are used to receive ROW[11:8], and the primary selectors 51 corresponding to ROW12 to ROW15 are used to receive ROW[15:12].

[0039] In some embodiments, reference Figure 5The imaging device also includes a secondary selector 52 corresponding to the number of pixel arrays 10. The control terminal of the secondary selector 52 is connected to the second control signal sel[3:2]. The input terminal of the secondary selector 52 is connected to the output terminal of the primary selector 51 corresponding to each subarray 20 in the pixel array 10. The output terminal of the secondary selector 52 outputs the target data in the corresponding pixel array 10.

[0040] In some embodiments, taking the pixel array 10 including four sub-arrays 20 and the secondary selector 52 including four input terminals as an example. The second control signal can be a 2-bit control signal, and the secondary selector 52 can output target data from multiple data to be filtered under the control of the second control signal. For example, each primary selector 51 responds to the first control signal sel[1:0] and outputs the imaging data in ROW3, ​​ROW7, ROW11 and ROW15 respectively, and the secondary selector 52 responds to the second control signal sel[3:2] and outputs the target data from the four data to be filtered (exemplarily, specifically the imaging data in ROW11). It should be noted that the number of bits of the second control signal can be set according to the number of sub-arrays 20 in the pixel array 10. The more sub-arrays 20 in the pixel array 10, the larger the number of bits of the second control signal.

[0041] In some embodiments, the imaging device further includes a cascade selector 53 corresponding to the number of pixel arrays 10. The control terminal of the cascade selector 53 is connected to a third control signal Ctrl. One input terminal of the cascade selector 53 is connected to the output terminal of the secondary selector 52 corresponding to the pixel array 10. The other input terminal of the cascade selector 53 is connected to the output terminal of the cascade selector 53 corresponding to the previous pixel array 10. The output terminal of the cascade selector 53 is connected to the input terminal of the cascade selector 53 corresponding to the next pixel array 10 or directly outputs the target data.

[0042] In some embodiments, the input terminal 0 of the cascade selector 53 is connected to the output terminal of the cascade selector 53 corresponding to the previous level pixel array 10, the input terminal 1 of the cascade selector 53 is connected to the output terminal of the secondary selector 52 corresponding to the pixel array 10, and the output terminal of the cascade selector 53 is connected to the input terminal of the cascade selector 53 corresponding to the next level pixel array 10 or directly outputs the target data.

[0043] When the SPAD array of the imaging device contains only one pixel array 10, the cascade selector 53 corresponding to the pixel array 10 can directly output the target data in the pixel array 10 in response to the third control signal.

[0044] When the entire SPAD array of the imaging device comprises multiple pixel arrays 10 as described above, and the current pixel array 10 is the last pixel array 10 in the entire SPAD array and is also the target pixel array 10, the cascade selector 53 corresponding to the current pixel array 10 can directly output the target data in the current pixel array 10 in response to the third control signal. Alternatively, when the current pixel array 10 is the last pixel array 10 in the entire SPAD array and is located after the target pixel array 10, the cascade selector 53 corresponding to the current pixel array 10 can output the target data transferred from the previous pixel array 10 in response to the third control signal. Alternatively, when the current pixel array 10 is the last pixel array 10 in the SPAD array and is located after the target pixel array 10, the cascade selector 53 corresponding to the current pixel array 10 can transfer the target data transferred from the previous pixel array 10 to the input terminal 0 of the cascade selector 53 corresponding to the next pixel array 10 in response to the third control signal. Alternatively, when the current pixel array 10 is located before the last pixel array 10 in the entire SPAD array and the current pixel array 10 is the target pixel array 10, the cascade selector corresponding to the current pixel array 10 can transfer the target data in the current pixel array 10 to the input terminal 0 of the cascade selector 53 corresponding to the next level pixel array 10 in response to the third control signal.

[0045] In some embodiments, at least two subarrays 20 within the same pixel array 10 have the same number of pixel rows, and the first-level selectors 51 corresponding to the subarrays 20 with the same number of pixel rows within the same pixel array 10 simultaneously respond to the same first control signal. This allows at least some subarrays 20 to share the same first control signal for data filtering, thereby reducing the number of first control signals and simplifying signal routing.

[0046] In some embodiments, the number of pixel rows in each subarray 20 within the pixel array 10 can be set to the same value. For example, a 16×16 pixel array 10 can be divided into two 8×16 subarrays 20. Thus, each subarray has 8 pixel rows, allowing them to share a single 3-bit binary first control signal to filter data from these 8 pixel rows. This improves the synchronous efficiency of filtering data from multiple subarrays 20 and reduces signal asynchronous delay. For example, the first-level selectors corresponding to ROW0 to ROW7 and ROW8 to ROW15 simultaneously respond to the same first control signal and output the imaging data received from their respective input terminals (exemplarily, input terminals 3 of each first-level selector) as the data to be filtered. Here, for example, the first-level selector is an 8-to-1 selector with 8 input terminals. In this case, the first control signals 000, 001, 010, 011, 100, 101, 110, and 111 correspond to the 8 different input terminals of the first-level selector.

[0047] In some embodiments, the number of pixel rows in each subarray 20 within the same pixel array 10 is the same and equal to the number of subarrays 20 within the pixel array 10.

[0048] In some embodiments, such as Figure 4 As shown, the pixel array 10 includes four sub-arrays 20, and each sub-array 20 also has four pixel rows. In this embodiment, the primary selector 51 corresponding to each sub-array 20 is a 4-to-1 selector Mux4, and when the four data to be filtered output by the four primary selectors 51 are filtered by the secondary selector 52, the secondary selector 52 can also be a 4-to-1 selector Mux4. Thus, both the first control signal and the second control signal can be 2-bit digital signals to control the primary selector 51 and the secondary selector 52 respectively. In this way, the primary selector 51 and the secondary selector 52 have the same structure, which facilitates circuit design and integration. Furthermore, the first control signal and the second control signal have the same number of bits, making it simpler to generate digital control signals with the same number of bits.

[0049] In some embodiments, at least two subarrays 20 within the same pixel array 10 have different numbers of pixel rows, and the first-level selectors 51 corresponding to the subarrays 20 with different numbers of pixel rows within the same pixel array 10 respond simultaneously to different first control signals.

[0050] In a specific example, pixel array 10 includes four subarrays 20, each comprising pixel rows as follows: ROW0 to ROW2, ROW3 to ROW5, ROW6 to ROW10, and ROW11 to ROW15. That is, two subarrays 20 each contain three pixel rows, and two subarrays 20 each contain five pixel rows. In this case, the primary selectors corresponding to ROW0 to ROW2 and ROW3 to ROW5 each output the data to be filtered in response to the same first control signal, and the primary selectors corresponding to ROW6 to ROW10 and ROW11 to ROW15 each output the data to be filtered in response to the same first control signal. Here, the first control signal responding to the primary selectors corresponding to ROW0 to ROW2 and ROW3 to ROW5 and the first control signal responding to the primary selectors corresponding to ROW6 to ROW10 and ROW11 to ROW15 can be the same or different.

[0051] In another specific example, pixel array 10 includes four subarrays 20, each comprising pixel rows as follows: ROW0 to ROW1, ROW2 to ROW5, ROW6 to ROW9, and ROW10 to ROW15, i.e., each subarray comprises 2, 4, 4, and 6 pixel rows respectively. In this case, the primary selectors corresponding to ROW0 to ROW1 output the data to be filtered in response to the first control signal; the primary selectors corresponding to ROW2 to ROW5 and ROW6 to ROW9 each output the data to be filtered in response to the same first control signal; and the primary selectors corresponding to ROW10 to ROW15 output the data to be filtered in response to the first control signal. Here, the first control signal responding to the primary selectors corresponding to ROW0 to ROW1, the first control signal responding to the primary selectors corresponding to ROW2 to ROW5 and ROW6 to ROW9, and the first control signal responding to the primary selectors corresponding to ROW10 to ROW15 can be the same or different.

[0052] In some embodiments, at least two subarrays 20 within the same pixel array 10 have different numbers of pixel rows, and the first-level selectors corresponding to the subarrays 20 with different numbers of pixel rows within the same pixel array 10 respond simultaneously to different first control signals or the same first control signal, which can improve the flexibility of pixel array grouping in the imaging device.

[0053] In some embodiments, the number of pixel rows in each subarray within the same pixel array varies regularly, and the first control signal connected to the first-level selector corresponding to each subarray within the same pixel array also varies regularly.

[0054] In some embodiments, the pixel rows in each subarray 20 within the same pixel array 10 can be distributed according to an arithmetic sequence. For example, the pixel array 10 includes three subarrays 20, each including pixel rows as follows: ROW0 to ROW2, ROW3 to ROW7, and ROW8 to ROW14, i.e., the three subarrays 20 respectively include 3, 5, and 7 pixel rows, with the number of pixel rows forming an arithmetic sequence with a common difference of 2. In this case, the first control signal corresponding to each subarray 20 can also change in an arithmetic sequence with a common difference of 2. For example, the first-level selector corresponding to ROW0 to ROW2 responds to the first control signal bit data being 000 and outputs the imaging data within the data to be selected in ROW0; the first-level selector corresponding to ROW3 to ROW7 responds to the first control signal bit data being 010 and outputs the imaging data within the data to be selected in ROW5; and the first-level selector corresponding to ROW8 to ROW14 responds to the first control signal bit data being 100 and outputs the imaging data within the data to be selected in ROW12. It should be noted that the number of pixel rows in each subarray within different pixel arrays may be different. This embodiment of the present disclosure does not limit the pattern of the number of pixel rows in each subarray within the same pixel array.

[0055] In some embodiments, reference Figure 4 and Figure 5 The pixel array 10 includes four sub-arrays 20, and each sub-array 20 has four pixel rows. The first-level selector 51 corresponding to each sub-array 20 can respond to the same first control signal sel[1:0] and output the imaging data received by the input terminal with the same number (e.g., input terminal 3) as the data to be filtered. The second-level selector 52 corresponding to the pixel array 10 can respond to the second control signal sel[3:2] and filter and output the target data from the four data to be filtered. The cascade selector 53 corresponding to the pixel array 10 can respond to the third control signal Ctrl and transfer the target data to the next level pixel array, or transfer the target data transferred from the previous level pixel array to the next level pixel array, or output the target data.

[0056] The following will analyze the transfer of image data within N rows of pixels using the imaging device of this disclosure, with reference to specific embodiments.

[0057] Regarding readout time, assuming the imaging device comprises N pixel rows, which are divided into several pixel arrays, each pixel array comprising M pixel rows, i.e., N pixel rows are divided into N / M pixel arrays. Therefore, the number of cascade nodes (cascade selectors) can be reduced from N to N / M. The readout delay for completing an N-row image is given by the following formula (2): (2) For an imaging device with N pixel rows, compared to equation (1), the imaging device provided in this disclosure reduces the readout delay of completing an N-row image by D. mux ×[(M-1) / M]×N 2 / 2. In a specific example, for a 1080p resolution image, N=1080, assuming D mux =0.2ns, D sel =3ns, M=16, then the transition time is reduced by 119988ns-10771ns=109217ns, which is a reduction of 91.02% (where N / 16=67.5 is rounded down to 68).

[0058] Regarding the risk of cascade node failure, the probability of each cascade node failing is p, and the probability of all nodes functioning normally in related technologies is (1-p). N In this disclosure, the number of cascaded nodes is reduced to N / M, so the normal probability of all cascaded nodes becomes (1-p). (N / M)+2 The 2 in the exponent represents the probability that the first-level and second-level selectors within the pixel array are functioning correctly. In a specific example, for an imaging device with N pixel rows, assuming N=1080 and M=16, the probability of cascade node failure is p=0.001%. Figure 2 The probability that the structure shown is normal is 98.926%. Figure 5 The probability of the structure shown being normal is 99.933%, an increase of 1.007%.

[0059] Regarding the storage space occupied by the control signals, for an imaging device with N pixel rows, assume N=1080 and M=16. Figure 2 The readout circuit architecture of the related technology shown requires one 1-bit control signal for each cascaded node, meaning it requires 1080 bits of storage space to store these 1080 1-bit control signals. However, in this disclosure... Figure 5 The required storage space in the structure shown is the sum of the number of bits required for the control signals of the first-level selector, the second-level selector, and the cascaded selector, respectively, which is the sum of the number of bits for the first control signal, the second control signal, and the third control signal, i.e., 2 + 2 + 1 = 5 bits. Therefore, the storage space occupied by the control signals is reduced by 1080 - 1080 / 16 × 5 = 742 bits, a reduction of 68.7%. This reduction in the number of bits required for the control signals not only lowers the hardware requirements but also makes it easier to optimize the wiring layout at the physical level, further optimizing D. sel The delay.

[0060] In some embodiments, since the sum of the number of primary selectors and secondary selectors corresponding to the pixel array that filters out the target data is much smaller than the number of cascaded nodes reduced by group cascading, the transmission delay of the primary selectors and secondary selectors can be basically ignored.

[0061] In some embodiments, the imaging device further includes a shift register module, and the imaging device is further configured such that an input terminal of the cascade selector corresponding to the pixel array farthest from the shift register module is connected to a reset signal.

[0062] In some embodiments, the input terminal 0 of the cascaded selector 53 corresponding to the pixel array 10 farthest from the shift register module is connected to a reset signal, and the input terminal 1 is connected to the output terminal of the corresponding secondary selector 52.

[0063] Figure 6 This diagram illustrates the steps of a control method for an imaging apparatus provided in an embodiment of the present disclosure. The control method is applied to an imaging apparatus, which includes at least one pixel array, wherein the pixel array includes at least two sub-arrays, and each sub-array includes at least two pixel rows. (Reference) Figure 6 The control method includes the following steps: S100: In exposure mode, controls the pixel array to acquire imaging data.

[0064] S200: In transfer mode, control at least two subarrays to transfer out one piece of data to be filtered, the data to be filtered being the imaging data within one pixel row in the subarray; filter out target data from the data to be filtered transferred out from at least two subarrays; transfer the target data to the next level pixel array, or transfer the target data transferred out from the previous level pixel array to the next level pixel array, or output the target data.

[0065] This embodiment of the disclosure, by reasonably setting pixel grouping and selector cascading methods, changes the traditional SPAD array method of selecting a pixel row by row selection signal and then transmitting the imaging data in that pixel row down row by row until output. Instead, it uses a method of multiple "multiple selections" in multiple subarrays of the SPAD array to filter the target data in the target pixel row. This transforms the traditional cascading circuit structure between rows into a cascading circuit structure between groups, thereby significantly reducing the number of cascading nodes. This effectively alleviates the problem of excessive latency caused by an excessive number of cascading selectors due to an excessive number of cascading nodes, and also effectively reduces the risk of cascading node failure.

[0066] Here, the control method embodiment of the imaging device has at least all the beneficial effects brought about by the technical solutions of the above-described imaging device embodiments. Details not mentioned in the control method embodiment of the imaging device can be referred to the technical solutions of the above-described imaging device embodiments, and will not be repeated here.

[0067] This disclosure provides an imaging apparatus and its control method. The imaging apparatus includes at least one pixel array; the pixel array includes at least two subarrays, each subarray including at least two pixel rows; the imaging apparatus is configured to: in an exposure mode, acquire imaging data; in a transfer mode, transfer and output the imaging data; wherein, the pixel array transferring and outputting the imaging data includes: in response to a first control signal, transferring one piece of data to be filtered from each of the at least two subarrays, the data to be filtered being imaging data within a pixel row of a subarray; in response to a second control signal, filtering out target data from the data to be filtered transferred from the at least two subarrays; and in response to a third control signal, transferring the target data to a next-level pixel array, or transferring the target data transferred from a previous-level pixel array to a next-level pixel array, or outputting the target data. This embodiment of the disclosure, by reasonably setting pixel grouping and selector cascading methods, changes the traditional SPAD array method of selecting a pixel row by row selection signal and then transmitting the imaging data in that pixel row down row by row until output. Instead, it uses a method of multiple "multiple selections" in multiple subarrays of the SPAD array to filter the target data in the target pixel row. This transforms the traditional cascading circuit structure between rows into a cascading circuit structure between groups, thereby significantly reducing the number of cascading nodes. This effectively alleviates the problem of excessive latency caused by an excessive number of cascading selectors due to an excessive number of cascading nodes, and also effectively reduces the risk of cascading node failure.

[0068] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0069] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. An image forming apparatus characterized by comprising: The imaging device includes at least one SPAD pixel array; the SPAD pixel array includes at least two sub-arrays, and the sub-arrays include at least two pixel rows; The imaging device is configured such that, in exposure mode, the SPAD pixel array acquires imaging data; In transfer mode, the SPAD pixel array transfers and outputs the imaging data; wherein, the transfer and output of the imaging data by the SPAD pixel array includes: In response to a first control signal, one piece of data to be filtered is transferred from each of at least two of the subarrays, the data to be filtered being imaging data within a pixel row of the subarray; In response to a second control signal, target data is selected from the data to be filtered transferred from at least two of the subarrays; In response to a third control signal, the target data is transferred to the next level SPAD pixel array, or the target data transferred from the previous level SPAD pixel array is transferred to the next level SPAD pixel array, or the target data is output.

2. The imaging device of claim 1, wherein, The imaging device includes a primary selector corresponding to the number of subarrays. The control terminal of the primary selector is connected to the first control signal, the input terminal of the primary selector is connected to the signal output terminal of each pixel row in the corresponding subarray, and the output terminal of the primary selector outputs the data to be filtered in the subarray.

3. The imaging apparatus according to claim 2, characterized by The imaging device further includes a secondary selector corresponding to the number of SPAD pixel arrays. The control terminal of the secondary selector is connected to the second control signal, the input terminal of the secondary selector is connected to the output terminal of the primary selector corresponding to each subarray in the SPAD pixel array, and the output terminal of the secondary selector outputs the target data in the corresponding SPAD pixel array.

4. The imaging apparatus according to claim 3, characterized by The imaging device further includes a cascade selector corresponding to the number of SPAD pixel arrays. The control terminal of the cascade selector is connected to the third control signal. The input terminal of the cascade selector is connected to the output terminal of the secondary selector corresponding to the SPAD pixel array and the output terminal of the cascade selector corresponding to the previous level SPAD pixel array. The output terminal of the cascade selector is connected to the input terminal of the cascade selector corresponding to the next level SPAD pixel array or directly outputs the target data.

5. The imaging apparatus of claim 2, wherein Within the same SPAD pixel array, at least two of the subarrays have the same number of pixel rows, and the first-level selectors corresponding to the subarrays with the same number of pixel rows within the same SPAD pixel array simultaneously respond to the same first control signal.

6. The imaging apparatus of claim 2, wherein The number of pixel rows in each subarray within the same SPAD pixel array is the same and equal to the number of subarrays within the SPAD pixel array.

7. The imaging apparatus of claim 2, wherein Within the same SPAD pixel array, at least two subarrays have different numbers of pixel rows, and the first-level selectors corresponding to the subarrays with different numbers of pixel rows within the same SPAD pixel array simultaneously respond to different first control signals.

8. The imaging apparatus of claim 2, wherein The number of pixel rows in each subarray within the same SPAD pixel array varies regularly, and the first control signal connected to the first-level selector corresponding to each subarray within the same SPAD pixel array also varies regularly.

9. The imaging apparatus according to claim 4, wherein The imaging device further includes a shift register module, and the imaging device is further configured such that a reset signal is connected to one input terminal of the cascade selector corresponding to the SPAD pixel array farthest from the shift register module.

10. A control method of an image forming apparatus, applied to an image forming apparatus, characterized by, The imaging device includes at least one SPAD pixel array, the SPAD pixel array including at least two subarrays, the subarrays including at least two pixel rows; the control method includes: In exposure mode, the SPAD pixel array is controlled to acquire imaging data; In the transfer mode, at least two of the subarrays are controlled to transfer out one piece of data to be filtered, wherein the data to be filtered is the imaging data within a pixel row in the subarray; target data is filtered out from the data to be filtered transferred out from the at least two subarrays; the target data is transferred to the next level SPAD pixel array, or the target data transferred out from the previous level SPAD pixel array is transferred to the next level SPAD pixel array, or the target data is output.

Images