Wafer level acoustic functional test method and support substrate

Abstract

This application provides a wafer-level acoustic function testing method and a support substrate, relating to the field of wafer-level testing technology. First, an acoustic sensor wafer with a protective structure on its surface is provided, and the acoustic sensor wafer is thinned. Next, a support substrate is provided, and the acoustic sensor wafer and the support substrate are bonded together using an adhesive material to form a bonded wafer. The support substrate has through-hole windows and a first slot structure; the positions of the through-hole windows correspond to the positions of the functional areas of the wafer, and the first slot structure corresponds to the positions of the dicing tracks on the wafer. Then, the bonded wafer is placed on a dicing workpiece, and the surface protective structure is removed. The substrate of the acoustic sensor wafer is then cut along the dicing tracks until the adhesive material or support substrate is exposed. Finally, the bonded wafer is removed from the dicing workpiece, and wafer-level acoustic function testing is performed. This application's solution has the advantages of balancing acoustic fidelity, wafer-level operational robustness, and inter-chip acoustic isolation.

Description

Technical Field

[0001] This application relates to the field of wafer-level testing technology, and more specifically, to a wafer-level acoustic function testing method and a supporting substrate. Background Technology

[0002] With the increasing prevalence of acoustic sensors in consumer electronics, automotive electronics, medical devices, and the Internet of Things (IoT), the semiconductor industry widely adopts wafer-level manufacturing and packaging technologies to meet the demands for miniaturization, high performance, and low cost. Under this technological approach, wafer-level functional testing of sensors becomes a crucial step in ensuring product quality and reducing subsequent packaging costs.

[0003] Wafer-level acoustic functional testing refers to evaluating core performance parameters such as sensitivity, frequency response, and linearity of a chip by applying specific acoustic signals (such as sound waves of a specific frequency and sound pressure) to the wafer before it has been cut and separated (i.e., while it is still in the wafer state) and simultaneously detecting the electrical signals converted and output by each sensor chip.

[0004] In existing technologies, acoustic sensor wafers face a dual precision bottleneck during wafer-level acoustic functional testing due to the coupling of longitudinal and lateral acoustic wave propagation. On the one hand, if the silicon substrate thickness is too large, longitudinal acoustic waves undergo significant attenuation, reflection, and mode conversion during penetration, leading to distortion of the acoustic response received by the functional area and severely affecting sensitivity, signal-to-noise ratio, and calibration accuracy. On the other hand, when wafers are thinned to <150μm to improve longitudinal acoustic coupling efficiency, mechanical strength decreases sharply, making them prone to warping, slippage, and even cracking during transmission, handling, bonding, and probe pressing processes, resulting in a sharp drop in yield. Furthermore, during parallel testing of multiple chips, the silicon substrates between adjacent chips form lateral acoustic pathways, causing crosstalk. This results in the acoustic parameters of a single chip (such as resonant frequency and phase response) being interfered with by the radiated sound field from neighboring chips, leading to unreliable test results and mapping failure.

[0005] Therefore, there is an urgent need for a wafer-level testing method that takes into account the acoustic fidelity of ultra-thin substrates, wafer-level operational robustness, and inter-chip acoustic isolation. Summary of the Invention

[0006] The purpose of this application is to provide a wafer-level acoustic function testing method and a supporting substrate to solve the problems in the prior art where wafer-level acoustic function testing cannot simultaneously achieve acoustic fidelity, wafer-level operational robustness, and inter-chip acoustic isolation.

[0007] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0008] On one hand, embodiments of this application provide a wafer-level acoustic function testing method, the method comprising:

[0009] An acoustic sensor wafer with a protective structure on its surface is provided, and the acoustic sensor wafer is thinned; wherein, the acoustic sensor wafer is provided with a cleavage and multiple acoustic sensor chips formed on a substrate, and each of the sensor chips includes a functional area;

[0010] A support substrate is provided, and the acoustic sensor wafer is bonded to the support substrate using an adhesive material to form a bonded wafer; wherein, the support substrate is provided with a through-hole window and a first slot structure, and in the bonded wafer, the position of the through-hole window corresponds to the position of the functional area, and the position of the first slot structure corresponds to the position of the dicing channel;

[0011] The bonded wafer is placed on the dicing workpiece, and the protective structure on the surface is removed;

[0012] Cut the substrate of the acoustic sensor wafer along the cutting path until the adhesive material or supporting substrate is exposed;

[0013] The bonded wafer is removed from the dicing workpiece and subjected to wafer-level acoustic performance testing.

[0014] Optionally, after performing wafer-level acoustic functional testing, the method further includes:

[0015] The bonding wafer is placed in reverse on the dicing workpiece so that the supporting substrate faces upward;

[0016] Remove the supporting substrate.

[0017] Optionally, the step of providing an acoustic sensor wafer with a protective structure on its surface includes:

[0018] Provide acoustic sensor wafers;

[0019] BG tape is attached to the surface of the acoustic sensor wafer.

[0020] Optionally, the step of thinning the acoustic sensor wafer includes:

[0021] The acoustic sensor wafer is thinned to 50~150μm using a grinding process.

[0022] Optionally, the supporting substrate is further provided with a second slotted structure, which is located on the side of the through-hole window and is connected to the first slotted structure.

[0023] Optionally, each of the through-hole windows is provided with the first slot structure on all four sides.

[0024] Optionally, the width of the second slotted structure is smaller than the width of the first slotted structure.

[0025] Optionally, the thickness of the adhesive material is greater than the thickness of the first slotted structure.

[0026] Optionally, the diameter of the supporting substrate is the same as the diameter of the acoustic sensor wafer, and the thickness of the supporting substrate is 100~2000μm.

[0027] On the other hand, this application embodiment also provides a support substrate, which is provided with through-hole windows and a first slot structure. The support substrate is used to bond with the acoustic sensor wafer by an adhesive material when performing the above-described wafer-level acoustic function testing method.

[0028] Compared with the prior art, the embodiments of this application have the following beneficial effects:

[0029] This application provides a wafer-level acoustic function testing method and a supporting substrate. First, an acoustic sensor wafer with a protective structure on its surface is provided, and the acoustic sensor wafer is thinned. The acoustic sensor wafer has dicing channels and multiple acoustic sensor chips formed on the substrate, each sensor chip including a functional area. Next, a supporting substrate is provided, and the acoustic sensor wafer and the supporting substrate are bonded together using an adhesive material to form a bonded wafer. The supporting substrate has through-hole windows and a first slot structure. In the bonded wafer, the positions of the through-hole windows correspond to the positions of the functional areas, and the first slot structure corresponds to the positions of the dicing channels. Then, the bonded wafer is placed on a cutting workpiece, and the protective structure on its surface is removed. The substrate of the acoustic sensor wafer is then cut along the dicing channels until the adhesive material or supporting substrate is exposed. Finally, the bonded wafer is removed from the cutting workpiece, and wafer-level acoustic function testing is performed.

[0030] Firstly, this application significantly reduces the propagation loss and phase distortion of longitudinal acoustic waves in the substrate by thinning the wafer; through-hole windows precisely aligned with the functional area on the supporting substrate achieve full hollowing directly below the functional area, eliminating the substrate's obstruction and reflection of the acoustic pressure field, and ensuring the integrity and directionality of the acoustic excitation / reception path. Secondly, after thinning, the ultra-thin wafer is directly bonded to the supporting substrate, which bears all the mechanical load; the temporary adhesive material not only provides initial fixing force, but also accommodates excess colloid and buffers cutting stress through the first slotted structure (corresponding to the dicing track), and guides the solution to penetrate along the slot to the center of the dicing track during subsequent debonding, achieving stress-free, low-temperature, and highly controllable separation, avoiding warping and chip displacement. Thirdly, the substrate between chips is completely removed along the dicing path, so that adjacent functional areas are physically separated by air gaps, completely cutting off the propagation path of transverse acoustic waves in the silicon body; while the adhesive material remains fixed in the original position after dicing, ensuring zero drift of chip spatial coordinates in the entire process of dicing, testing and debonding, providing a structural basis for precise contact and parallel testing of wafer-level probe cards.

[0031] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 An example flowchart of a wafer-level acoustic function testing method provided in an embodiment of this application.

[0034] Figure 2 This is a cross-sectional schematic diagram of the substrate provided in an embodiment of this application.

[0035] Figure 3 This is a cross-sectional view of the application provided in an embodiment of this application after BG tape has been applied.

[0036] Figure 4 This is a schematic cross-sectional view of the wafer after thinning, provided in an embodiment of this application.

[0037] Figure 5 This is a cross-sectional schematic diagram of the support substrate provided in an embodiment of this application.

[0038] Figure 6 This is a top view of the support substrate provided in an embodiment of this application.

[0039] Figure 7 This is a 3D schematic diagram of the support substrate provided in an embodiment of this application.

[0040] Figure 8 This is a cross-sectional schematic diagram of the bonding wafer provided in an embodiment of this application.

[0041] Figure 9 This is a cross-sectional view of the area after removing the BG tape, as provided in an embodiment of this application.

[0042] Figure 10 This is a schematic cross-sectional view of the substrate after it has been cut, as provided in an embodiment of this application.

[0043] Figure 11 This is a cross-sectional view of the acoustic sensor wafer after it has been peeled from the workpiece, as provided in the embodiments of this application.

[0044] Figure 12 This is a cross-sectional schematic diagram corresponding to wafer-level acoustic function testing provided in an embodiment of this application.

[0045] Figure 13 This is a cross-sectional schematic diagram of a test wafer flipped and placed on a cutting workpiece, provided as an embodiment of this application.

[0046] Figure 14 This is a cross-sectional schematic diagram of the independent chip array provided in the embodiments of this application.

[0047] In the picture:

[0048] 00-Substrate; 01-Electrode; 02-Functional area; 03-BG tape; 04-Supporting substrate; 05-Through hole opening; 06-Second slotted structure; 07-First slotted structure; 08-Adhesive material; 09-Cut film; 10-Cut iron ring; 11-Cut track; 12-Probe card; 13-Probe. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0050] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0051] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0052] It should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0053] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0054] As described in the background section, the implementation of wafer-level acoustic functional testing currently faces two interrelated technical challenges:

[0055] The first challenge is the trade-off between wafer thickness and testing accuracy versus process feasibility: acoustic waves attenuate as they propagate through solid media. During testing, the excitation acoustic waves need to penetrate the wafer substrate to reach the sensor elements (i.e., the "functional area" or "diaphragm") located on the front side of the wafer. If the wafer thickness is large (e.g., exceeding 200 μm), the acoustic waves attenuate significantly during penetration, resulting in a weaker acoustic signal reaching the functional area, a decreased signal-to-noise ratio in the testing system, and ultimately inaccurate test results that fail to accurately reflect chip performance. To address the acoustic wave attenuation problem, the most direct approach is to mechanically grind and thin the back of the wafer to shorten the acoustic wave propagation path. However, when the wafer thickness is reduced to below 150 μm, while the accuracy of acoustic testing is improved, the mechanical strength of the wafer itself decreases drastically. Such ultra-thin wafers are highly susceptible to bending, warping, or even cracking (i.e., "cracking") during subsequent transport, handling, and loading / unloading on the testing platform, leading to the scrapping of the entire wafer and severely restricting production yield and process stability.

[0056] The second challenge is lateral acoustic crosstalk during testing. On a wafer, hundreds or even thousands of sensor chips are densely arranged in an array. When a probe card simultaneously or sequentially acoustically excites multiple chips, the generated sound waves not only propagate longitudinally to the functional area of ​​the target chip but also laterally along the wafer substrate, leaking into adjacent chip areas. This crosstalk interferes with the test signals of neighboring chips, causing the test results to include noise from other chips, thus distorting the performance evaluation of individual chips. This lateral crosstalk problem becomes particularly prominent in designs with high-density integration and small chip spacing, severely affecting the consistency and reliability of testing.

[0057] In view of this, in order to solve the above problems, this application provides a wafer-level acoustic function testing method. As one implementation method, please refer to [link / reference needed]. Figure 1 The method includes:

[0058] S102, an acoustic sensor wafer with a protective structure on its surface is provided, and the acoustic sensor wafer is thinned; wherein, the acoustic sensor wafer is provided with a dicing channel and multiple acoustic sensor chips formed on a substrate, each sensor chip including a functional area.

[0059] S104, a support substrate is provided, and an acoustic sensor wafer is bonded to the support substrate by an adhesive material to form a bonded wafer; wherein, the support substrate is provided with a through-hole window and a first slot structure, and in the bonded wafer, the position of the through-hole window corresponds to the position of the functional area, and the position of the first slot structure corresponds to the position of the dicing channel.

[0060] S106, Place the bonded wafer on the dicing workpiece and remove the protective structure on the surface.

[0061] S108 cuts the substrate of the entire acoustic sensor wafer along the dicing path until the adhesive material or support substrate is exposed.

[0062] S110 removes the bonded wafer from the dicing workpiece and performs wafer-level acoustic functional testing.

[0063] Firstly, this application significantly reduces the propagation loss and phase distortion of longitudinal acoustic waves in the substrate by thinning the wafer; through-hole windows precisely aligned with the functional area on the supporting substrate achieve full hollowing directly below the functional area, eliminating the substrate's obstruction and reflection of the acoustic pressure field, and ensuring the integrity and directionality of the acoustic excitation / reception path. Secondly, after thinning, the ultra-thin wafer is directly bonded to the supporting substrate, which bears all the mechanical load; the temporary adhesive material not only provides initial fixing force, but also accommodates excess colloid and buffers cutting stress through the first slotted structure (corresponding to the dicing track), and guides the solution to penetrate along the slot to the center of the dicing track during subsequent debonding, achieving stress-free, low-temperature, and highly controllable separation, avoiding warping and chip displacement. Thirdly, the substrate between chips is completely removed along the dicing line, physically isolating adjacent functional areas by air gaps and completely cutting off the propagation path of transverse acoustic waves within the silicon. Meanwhile, the adhesive material remains in place after dicing, ensuring zero drift in chip spatial coordinates throughout the entire dicing, testing, and debonding process, providing a structural basis for precise contact and parallel testing of wafer-level probe cards. Therefore, the wafer-level acoustic functional testing method provided in this application balances the acoustic fidelity of ultra-thin substrates, wafer-level operational robustness, and inter-chip acoustic isolation.

[0064] Step S102 includes:

[0065] S1021 provides acoustic sensor wafers.

[0066] S1022 is based on surface mount BG tape on acoustic sensor wafers.

[0067] First, provide an acoustic sensor wafer with completed front-end processing. For example... Figure 2 As shown, multiple acoustic sensor chips (chip 1 and chip 2 are exemplary in the figure) are formed on the substrate 00 (e.g., silicon substrate) of the wafer through semiconductor processes such as photolithography, etching, and thin film deposition. Each acoustic sensor chip includes a functional area 02 (i.e., an acoustically sensitive area, such as a MEMS diaphragm) and an electrode 01, etc., and the functional area 02 and the electrode 01 are both located on the front side of the chip, with reserved cutting channels 11 between the chips.

[0068] Next, a layer of BG tape 03 (BackGrinding Tape) is applied to the front side of the wafer (i.e., the side with functional area 02), as shown below. Figure 3 As shown. This tape should be selected for its moderate tack, ease of subsequent peeling, and lack of residue to fully protect the delicate sensor structure.

[0069] Next, back-side thinning is performed. The wafer, with protective tape applied, is loaded onto a grinding machine, and its back side is mechanically ground. For example, during thinning, depending on design requirements, the acoustic sensor wafer is thinned to 50-500 μm using a grinding process. Preferably, the acoustic sensor wafer is thinned to 50-150 μm, for example, to 100 μm. The thinned acoustic sensor wafer is as follows... Figure 4 As shown, after thinning, the longitudinal acoustic attenuation of the wafer in acoustic testing will be significantly reduced.

[0070] After wafer thinning, a dedicated support substrate 04 is prepared and bonded to the acoustic sensor wafer using an adhesive material 08. The support substrate 04 is circular, with a diameter identical to the acoustic sensor wafer to be processed (e.g., 8-inch or 12-inch), and its thickness is 100–2000 μm, for example, 500 μm. A specific structure is pre-fabricated on this support substrate 04 using laser processing or deep etching. (See also...) Figures 5-7 This particular structure includes:

[0071] Via 05: Its position is precisely aligned with the functional area 02 of each chip on the wafer. Its size is slightly larger than the functional area 02 itself, generally more than 10μm larger on each side than the functional area 02. For example, each side of the via 05 is 20μm larger than the functional area 02 to ensure that acoustic waves can pass through without obstruction.

[0072] Furthermore, this application does not specifically limit the shape of the through-hole window 05; the shape of the through-hole window 05 can be set according to the shape of the functional area 02. For example, when the functional area 02 is set to square, the shape of the through-hole window 05 is also set to square; when the functional area 02 is set to circular, the shape of the through-hole window 05 is also set to circular.

[0073] The first slot structure 07 is precisely aligned with the dicing path 11 on the wafer. The opening is typically set to approximately 10µm to 300µm, for example, a slot width of 80µm; the slot depth is approximately 10µm to 500µm, for example, a depth of 30µm. Understandably, the first slot structure 07 defines the path for subsequent dicing.

[0074] The first slotted structure 07 has the following functions:

[0075] First, it provides a physical path and space for completely cutting off the wafer substrate 00.

[0076] In subsequent dicing processes, the substrate 00 between the chips needs to be completely cut through along the dicing path 11 to eliminate lateral acoustic crosstalk. Therefore, by setting a first slotting structure 07, when the dicing blade cuts down, it first cuts through the substrate 00 and then falls into this first slotting structure 07 to continue cutting the filler (adhesive material 08) within the groove, without hitting the supporting substrate 04 body. This structure prevents the blade tip from directly impacting the hard surface of the supporting substrate 04, thus avoiding blade chipping, wear, and potential scratches on the substrate that generate silicon dust and contaminate the chip.

[0077] Second: Control the cutting depth to protect the blade and substrate.

[0078] Since the trench has a defined depth (e.g., 30 μm), as long as the thickness of the temporary bonding material is slightly greater than this depth (e.g., 40 μm), the blade's range of motion within the trench is a safe "soft material" zone. This achieves precise control over cutting the silicon substrate without damaging the supporting substrate 04, ensuring cutting quality and equipment safety.

[0079] Third: to provide a penetration channel for the subsequent removal of adhesive material 08.

[0080] During debonding (removal of the support substrate 04), the chemical solution for dissolving the bonding material can quickly penetrate into each dicing channel 11 through the first slotted structure 07 that runs through the entire wafer, ensuring that the bonding material can be dissolved uniformly and thoroughly.

[0081] Furthermore, in one implementation, the supporting substrate 04 is further provided with a second slotted structure 06, which is located on the side of the through-hole window 05 and connects to the first slotted structure 07. In one implementation, the first slotted structure 07 is provided around each through-hole window 05. The surrounding area described in this application, as... Figure 6 As shown, for each through-hole opening 05, a first slotting structure 07 is provided in at least four directions: top, bottom, left, and right. For example, when the through-hole opening 05 is set as square, a first slotting structure 07 is provided on all four sides of each through-hole opening 05. The number of slots is unlimited and is designed according to the product size. The slot opening and depth are not limited, generally with an opening of 10um~1000μm and a slot depth of approximately 10um~500μm.

[0082] Furthermore, this application does not limit the shape or size of the second slotted structure 06 and the first slotted structure 07, and these can be adjusted according to the product design space. In one possible implementation, the width of the second slotted structure 06 is smaller than the width of the first slotted structure 07. For example, the slot width of the first slotted structure 07 is set to 80 μm, the slot width of the second slotted structure 06 is set to 30 μm, and the depth of both the first slotted structure 07 and the second slotted structure 06 is 30 μm.

[0083] The second slotted structure 06 has the following functions:

[0084] First: Control the distribution and thickness of temporary adhesive material 08 (as an "overflow channel").

[0085] When liquid temporary bonding material is coated on the support substrate 04 and then pressed, if the material has nowhere to go, it will be over-compressed, leading to uneven bonding layer thickness, colloid overflow contaminating functional area 02, and even affecting the alignment accuracy between the wafer and the substrate. By placing the second slotted structure 06 around the through-hole window 05, it acts as an overflow channel and stores the adhesive material 08. During the pressing process, the excess bonding material squeezed out flows into these surrounding second slotted structures 06, thereby precisely controlling the final thickness and uniformity of the bonding layer directly below the chip and ensuring bonding quality.

[0086] Second: It greatly improves the removal efficiency of bonded materials (as a rapid penetration channel).

[0087] The bonding material adheres a large area of ​​the chip's back surface to the support substrate 04. During removal, if the chemical solution can only slowly penetrate inwards from the wafer edge, the efficiency is extremely low, and the bonding material in the central area may not be completely removed. By setting a second trench structure 06 interconnected with the first trench structure 07, a trench network is formed covering the entire support substrate 04. When immersed in the chemical solution, the solution can quickly penetrate into the bonding interface from all sides, not only from the outside but also through these internal trenches surrounding each chip. This makes the dissolution / peeling process fast, uniform, and thorough, improving the efficiency and success rate of the bonding process.

[0088] Next, adhesive coating and bonding are performed. A layer of adhesive material 08 is spin-coated onto the grooved side of the support substrate 04. This adhesive material 08 is generally a temporary bonding material, such as a photosensitive temporary bonding material, which can be removed later. The adhesive material 08 is coated on the surface of the grooved structure.

[0089] During the adhesive coating process, the coating process is controlled so that the thickness of the bonding material is greater than the depth of the first slotted structure 07. For example, the thickness of the bonding material is 40 μm, and the depth of the first slotted structure 07 is 30 μm. Then, the thinned sensor wafer (thinned on the back and protected by BG tape on the front) and the coated support substrate 04 are precisely aligned in a bonding machine, ensuring that the functional area 02 of each chip falls completely within the corresponding through-hole window 05 of the support substrate 04. After alignment, vacuum bonding is performed under specific temperature and pressure conditions to solidify the bonding material and form a firmly bonded wafer, such as... Figure 8 As shown. Excess bonding material is squeezed into the first and second slots.

[0090] After the bonding wafer is formed, loading and removal of the protective layer follow. For details, please refer to [link to relevant documentation]. Figure 9 The support substrate 04 is attached to an expanded dicing film 09, which is taut on a metal dicing ring 10. At this point, the BG tape 03 is on top and the support substrate 04 is on the bottom. Then, the BG tape is smoothly peeled off, exposing the functional area 02, electrode 01, and other structures on the front side of the wafer.

[0091] Then, using a diamond cutting blade, the bonded wafer is cut along the path indicated by the first slot structure 07 on the support substrate 04 (i.e., the original wafer dicing location). Please refer to [link to relevant documentation]. Figure 10 The cutting depth needs to be precisely controlled, completely cutting through the substrate 00 of the acoustic sensor wafer to thoroughly separate adjacent chips at the silicon level, thus blocking the lateral acoustic wave path. Simultaneously, the cutting depth must only penetrate the bonding material filling the first slot, without cutting into the body material of the supporting substrate 04. That is, cutting should stop when the bonding material 08 is exposed or just as the supporting substrate 04 is exposed. Since the thickness of the bonding material is greater than the depth of the first slot structure 07, a safe buffer zone is provided for the cutting blade.

[0092] After completing the cutting, please refer to Figure 11 The entire structure is removed from the dicing membrane 09. At this point, the substrates 00 between the individual acoustic sensor chips have been separated, but are still fixed in their original positions on the supporting substrate 04 by bonding materials, forming a test wafer. This test wafer is then mounted on the wafer prober 13 stage using a dedicated acoustic test probe card 12, which integrates the acoustic emitter and electrical probes 13. Figure 12 As shown, probe card 12 contacts electrode 01 on the chip, and its acoustic transmitter emits a standard acoustic test signal into the functional area 02 of the chip through the through-hole window 05 of the supporting substrate 04. The electrical signal generated by the chip is collected by probe 13 and transmitted to the testing machine, thereby completing the performance evaluation and good / bad judgment of each chip and generating a test mapping diagram. Since the substrate 00 between adjacent chips has been cut off, lateral crosstalk is greatly suppressed; at the same time, the wafer has been thinned, and the longitudinal acoustic wave attenuation is small, so the test results are more accurate and reliable.

[0093] As one implementation method, after completing wafer-level acoustic functional testing, the method also includes:

[0094] S112, the bonding wafer is reversed and placed on the dicing workpiece so that the supporting substrate faces upward.

[0095] S114, Remove the supporting substrate.

[0096] That is, debonding is performed after the test is completed. For example... Figure 13As shown, the test wafer is flipped so that its front side is attached to a new, highly adhesive diced film 09 and an iron ring, with the support substrate 04 on top. The entire structure is then immersed in a specific solvent, which rapidly penetrates through the network formed by the first and second slots, dissolving the temporary bonding material. Once the bonding material fails, the support substrate 04 can be easily removed. Of course, when removing the bonding material, appropriate methods can be selected based on the properties of the adhesive material 08, such as using laser irradiation to reduce adhesion strength, UV irradiation to reduce adhesion strength, or chemical soaking to dissolve the adhesive material 08. This application does not limit the scope of these methods.

[0097] After debonding, the functional areas 02 of multiple chips remain facing downwards. Therefore, in one implementation, a film-applying and peeling method can be used to place the functional areas 02 of the chips face upwards on the adhesive film and cutting ring 10, followed by cleaning and drying. The final result is an array of individual chips facing upwards and neatly arranged on the final cutting film 09, as shown below. Figure 14 As shown, the product is then inspected and put into storage, completing the entire processing procedure.

[0098] In summary, the wafer-level acoustic function testing method provided in this application reduces the wafer silicon substrate to below 150 μm before continuing the wafer-level acoustic function testing, and then attaches it to a support substrate 04 using a temporary bonding material, thereby solving the problems of longitudinal acoustic wave testing accuracy and easy cracking during the transport of ultra-thin wafers.

[0099] Next, the acoustic wafer, temporarily bonded to the support substrate 04, is diced along the dicing path 11, removing the silicon substrate between the chips. Because of the adhesion of the temporary bonding material, each chip remains in its original position after dicing without displacement. Therefore, the acoustic wafer with the support substrate 04 can be used for wafer-level testing using a pinboard. Since the silicon substrate between adjacent chips is removed, the influence of lateral acoustic waves during acoustic testing is eliminated.

[0100] The through-hole window structure 05 of the support substrate 04 facilitates the hollowing out of the functional area 02 below the chip, which is helpful for the acoustic function testing of longitudinal acoustic waves. Furthermore, the second slot structure 06 of the support substrate 04 has two functions: firstly, it helps control the amount (thickness) of the adhesive material 08, allowing excess material to flow out along the slot; secondly, during the subsequent removal of the adhesive material 08, it facilitates the penetration of the reaction solution into the center of the dicing channel 11, improving removal efficiency and effectiveness. The design of the first slot structure 07 is beneficial for the process window and quality control of the cutting depth during wafer dicing: when the adhesive material 08 is very thin, such as within 5µm, the groove design ensures that the dicing blade only cuts into the interior of the adhesive material 08 without touching the support substrate 04. If the blade touches the support substrate 04, it will damage the blade, damage the support substrate 04, and result in poor chip dicing quality, leading to product scrap.

[0101] Furthermore, during debonding, the preferred method for using the adhesive material 08 is immersion in a chemical solution, which offers the following advantages: First, the immersion temperature does not exceed 100°C, making it suitable for temperature-sensitive sensor wafers; second, the separation process is stress-free, also wafer-friendly; and third, the combination of the first and second trench structures enables rapid removal of the adhesive material 08.

[0102] Based on the above implementation, this application embodiment also provides a support substrate 04, which is provided with a through-hole window 05 and a first slot structure 07. The support substrate 04 is used to bond with the acoustic sensor wafer by an adhesive material 08 in the above-mentioned wafer-level acoustic function testing method.

[0103] The shape of the through-hole window 05 is not limited to square; a circular window can be used for the circular functional area 02. The width of the first slot structure 07 can be adjusted according to the type of cutting blade used, for example, varying within the range of 50-150 μm. The number of second slot structures 06 is not limited to one on each of the four sides of each window; more or fewer guide slots can be set at key locations based on the shape of the functional area 02 and material flow simulation.

[0104] Temporary bonding materials are not limited to photosensitive materials; they can also be thermoplastic materials, UV-degradable materials, etc. In addition, temporary bonding materials are not limited to wet adhesives; they can be dry film materials with adhesive properties on both sides, as long as they can form a reliable temporary bond with the support substrate 04 and the wafer, and can be removed by physical (such as laser ablation) or chemical methods in the future.

[0105] In summary, this application provides a wafer-level acoustic function testing method and a supporting substrate. First, an acoustic sensor wafer with a protective structure on its surface is provided, and the acoustic sensor wafer is thinned. The acoustic sensor wafer has dicing channels and multiple acoustic sensor chips formed on the substrate, each sensor chip including a functional area. Next, a supporting substrate is provided, and the acoustic sensor wafer and the supporting substrate are bonded together using an adhesive material to form a bonded wafer. The supporting substrate has through-hole openings and a first slot structure. In the bonded wafer, the positions of the through-hole openings correspond to the positions of the functional areas, and the first slot structure corresponds to the positions of the dicing channels. Then, the bonded wafer is placed on a cutting workpiece, and the protective structure on its surface is removed. The substrate of the acoustic sensor wafer is then cut along the dicing channels until the adhesive material or supporting substrate is exposed. Finally, the bonded wafer is removed from the cutting workpiece, and wafer-level acoustic function testing is performed. Firstly, this application significantly reduces the propagation loss and phase distortion of longitudinal acoustic waves in the substrate by thinning the wafer; through-hole windows precisely aligned with the functional area on the supporting substrate achieve full hollowing directly below the functional area, eliminating the substrate's obstruction and reflection of the acoustic pressure field, and ensuring the integrity and directionality of the acoustic excitation / reception path. Secondly, after thinning, the ultra-thin wafer is directly bonded to the supporting substrate, which bears all the mechanical load; the temporary adhesive material not only provides initial fixing force, but also accommodates excess colloid and buffers cutting stress through the first slotted structure (corresponding to the dicing track), and guides the solution to penetrate along the slot to the center of the dicing track during subsequent debonding, achieving stress-free, low-temperature, and highly controllable separation, avoiding warping and chip displacement. Thirdly, the substrate between chips is completely removed along the dicing path, so that adjacent functional areas are physically separated by air gaps, completely cutting off the propagation path of transverse acoustic waves in the silicon body; while the adhesive material remains fixed in the original position after dicing, ensuring zero drift of chip spatial coordinates in the entire process of dicing, testing and debonding, providing a structural basis for precise contact and parallel testing of wafer-level probe cards.

[0106] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0107] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A wafer-level acoustic functional test method, characterized in that, The method includes: An acoustic sensor wafer with a protective structure on its surface is provided, and the acoustic sensor wafer is thinned; wherein, the acoustic sensor wafer is provided with a cleavage and multiple acoustic sensor chips formed on a substrate, and each of the sensor chips includes a functional area; A support substrate is provided, and the acoustic sensor wafer is bonded to the support substrate using an adhesive material to form a bonded wafer; wherein, the support substrate is provided with a through-hole window and a first slot structure, and in the bonded wafer, the position of the through-hole window corresponds to the position of the functional area, and the position of the first slot structure corresponds to the position of the dicing channel; the support substrate is also provided with a second slot structure, the second slot structure being located on the side of the through-hole window and communicating with the first slot structure; The bonded wafer is placed on the dicing workpiece, and the protective structure on the surface is removed; Cut the substrate of the acoustic sensor wafer along the cutting path until the adhesive material or supporting substrate is exposed; The bonded wafer is removed from the dicing workpiece and subjected to wafer-level acoustic performance testing.

2. The wafer-level acoustic functional test method of claim 1, wherein, Following the step of performing wafer-level acoustic functional testing, the method further includes: The bonding wafer is placed in reverse on the dicing workpiece so that the supporting substrate faces upward; Remove the supporting substrate.

3. The wafer-level acoustic functional test method of claim 1, wherein, The steps of providing an acoustic sensor wafer with a protective structure on its surface include: Provide acoustic sensor wafers; BG tape is attached to the surface of the acoustic sensor wafer.

4. The wafer-level acoustic function testing method as described in claim 1, characterized in that, The step of thinning the acoustic sensor wafer includes: The acoustic sensor wafer is thinned to 50~150μm using a grinding process.

5. The wafer-level acoustic function testing method as described in claim 1, characterized in that, Each of the through-hole windows is provided with the first slotted structure on all four sides.

6. The wafer-level acoustic function testing method as described in claim 1, characterized in that, The width of the second slotted structure is smaller than the width of the first slotted structure.

7. The wafer-level acoustic function testing method as described in claim 1, characterized in that, The thickness of the adhesive material is greater than the thickness of the first slotted structure.

8. The wafer-level acoustic function testing method as described in claim 1, characterized in that, The diameter of the supporting substrate is the same as the diameter of the acoustic sensor wafer, and the thickness of the supporting substrate is 100~2000μm.

9. A support substrate, characterized in that, The supporting substrate is provided with a through-hole window and a first slot structure. The supporting substrate is used to bond with the acoustic sensor wafer by an adhesive material when performing the wafer-level acoustic function testing method as described in any one of claims 1 to 8.

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