A bidirectional thyristor with a composite trench terminal structure and its fabrication method

Abstract

This invention relates to the field of semiconductor device technology, and discloses a bidirectional thyristor with a composite trench termination structure and its fabrication method. The bidirectional thyristor includes: an N-type silicon substrate; two P-type base regions for forming a planar PN junction within the device together with the N-type silicon substrate; an N+ type emitter region located on the side of the P-type base regions away from the N-type silicon substrate; several composite trench termination structures disposed in the termination isolation region of the N-type silicon substrate; the composite trench termination structure includes a mesa deep trench and auxiliary trenches located on the side of the mesa deep trench; wherein, the mesa deep trench is used to achieve physical isolation between the active region and adjacent devices through the trench structure, and the auxiliary trench is used to attract and redistribute electric field lines during breakdown voltage to reduce the peak electric field at the sidewall of the mesa deep trench; and an oxide thin film. This invention can directly and efficiently suppress the peak electric field at the corner of the mesa deep trench with minimal process and area costs.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically, to a bidirectional thyristor with a composite trench termination structure and its fabrication method. Background Technology

[0002] In the field of semiconductor devices, bidirectional thyristors are widely used in various power electronic systems such as dimming, speed control, and temperature control because they enable bidirectional control of AC circuits. To ensure the electrical isolation performance and reliability of the device, a termination isolation structure is usually used at the chip edge to define the active region.

[0003] In thyristor products, the mesa deep trench structure is a common solution for achieving terminal isolation; a typical dual-mesa bidirectional thyristor uses this structural design. For example... Figure 3 As shown, deep trenches formed by etching processes can effectively isolate different functional areas, but they also introduce new technical challenges, especially the inherent physical limitations in terms of device withstand voltage performance.

[0004] In existing mesa-type silicon controlled rectifier (SCR) devices, the mesa trenches formed by etching to isolate the active region inevitably intersect with the planar PN junction within the device. Because the sidewalls of the etched trenches have a small radius of curvature, this intersection leads to extremely dense electric field lines when the device is subjected to reverse voltage, generating a local peak electric field intensity much higher than in other areas. This electric field concentration caused by curvature means that avalanche breakdown often occurs first at the intersection of the mesa trench and the PN junction, with the actual breakdown voltage being far lower than the theoretical withstand voltage of silicon itself and also lower than the withstand voltage level achievable by the planar junction within the device.

[0005] To improve the withstand voltage capability of mesa thyristors, the industry typically employs methods such as optimizing the morphology of the mesa trench itself or introducing lateral termination structures like field-limiting rings. However, each of these methods has its limitations. For example, while optimizing the sidewall tilt angle and doping profile distribution of the deep mesa trench can directly improve the electric field distribution at the corners to some extent, this method requires extremely high precision in manufacturing process control, resulting in a very narrow process window and limited actual optimization space, making it difficult to achieve significant performance improvements. Furthermore, while lateral termination structures like field-limiting rings are technically mature, they inevitably require a large chip area, leading to a significant increase in manufacturing costs and contradicting the current trend of miniaturization and high integration in power devices. Finally, a composite termination structure combining trench structures and field-limiting rings is overly complex in design and manufacturing, significantly increasing process steps and manufacturing difficulty, and is not a simple solution specifically addressing the peak electric field problem at the corners of deep mesa trenches. Therefore, current technology still lacks a solution that can directly and efficiently suppress the peak electric field at the corners of deep mesa trenches with minimal process and area costs.

[0006] No effective solutions have yet been proposed to address the problems in the relevant technologies. Summary of the Invention

[0007] To address the problems in related technologies, this invention proposes a bidirectional thyristor with a composite trench terminal structure and its preparation method, in order to overcome the aforementioned technical problems existing in the prior art.

[0008] Therefore, the specific technical solution adopted by the present invention is as follows: According to one aspect of the present invention, a bidirectional thyristor with a composite trench termination structure is provided. The bidirectional thyristor with a composite trench termination structure includes: an N-type silicon substrate; termination isolation regions are provided on both sides of the front and back sides of the N-type silicon substrate; two P-type base regions are respectively disposed on the front and back sides of the N-type silicon substrate; the P-type base regions are used to form a planar PN junction in the device together with the N-type silicon substrate; an N+ type emitter region is formed on the side of the P-type base region away from the N-type silicon substrate; a plurality of composite trench termination structures are disposed on the termination isolation regions of the N-type silicon substrate; the composite trench termination structure includes a mesa deep trench and an auxiliary trench located on the side of the mesa deep trench; wherein the mesa deep trench is used to achieve physical isolation between the active region and adjacent devices through the trench structure, and the auxiliary trench is used to attract and redistribute electric field lines during breakdown voltage to reduce the peak electric field at the sidewall of the mesa deep trench; and an oxide film covering the side of the P-type base region away from the N-type silicon substrate.

[0009] Furthermore, the bidirectional thyristor with a composite trench terminal structure also includes: a SIPOS thin film disposed inside the mesa deep trench and the auxiliary trench, and on one side of the oxide layer thin film; wherein, the surface of the SIPOS thin film located inside the mesa deep trench and the auxiliary trench is sequentially covered with a glass film and an LTO thin film, and the surface of the SIPOS thin film located on the oxide layer thin film is covered with an LTO thin film; a cathode electrode and a gate electrode located on the front side of the N-type silicon substrate, and an anode electrode located on the back side of the N-type silicon substrate; wherein, the cathode electrode and the gate electrode are used to lead out the cathode and realize gate control, respectively, and the anode electrode is used to lead out the anode.

[0010] Furthermore, the auxiliary trench and the deep trench on the platform are arranged adjacent to each other in the terminal isolation area, and the deep trench on the platform has a first trench depth, while the auxiliary trench has a second trench depth; the second trench depth is less than the first trench depth, and the second trench depth is within the range of one-third to two-fifths of the first trench depth.

[0011] Furthermore, both the mesa deep trench and the auxiliary trench are trench structures formed by wet chemical etching. The trench structure includes sidewalls with an inclined angle and a bottom trench with a radius of curvature. The auxiliary trench, through the semiconductor interface formed by the bottom trench with a radius of curvature, shifts the electric field lines that were originally concentrated at the intersection of the sidewall of the mesa deep trench and the planar PN junction in the device during breakdown voltage to the auxiliary trench, thereby suppressing the local peak electric field at the intersection.

[0012] Furthermore, the deep trench of the mesa has a trench depth of 84-90μm, and the auxiliary trench has a trench depth of 31-33μm, which is used to help improve the forward breakdown voltage and reverse breakdown voltage of the device.

[0013] Furthermore, the oxide film serves as an electrical insulating and passivation layer to reduce the surface state density, thereby stabilizing the electrical characteristics of the device and suppressing metal or ion contamination during fabrication; the SIPOS film serves as an electric field conditioning layer to optimize the electric field distribution on the terminal surface; the glass film serves as an insulating dielectric layer distributed within the mesa deep trenches and auxiliary trenches to block ion migration and, after high-temperature treatment, to smooth the device surface for step coverage; and the LTO film serves as the outermost protective film to cover and isolate, forming a complete surface passivation and protective layer.

[0014] According to another aspect of the present invention, a method for fabricating a bidirectional thyristor with a composite trench termination structure is also provided. The method includes: providing an N-type silicon substrate; implanting and diffusing P-type impurity ions on the front and back sides of the N-type silicon substrate, and during the diffusion process, forming a P-type base region and an oxide film on the surface of the front and back sides; photolithographically creating a first window on the front and back sides of the N-type silicon substrate, removing the oxide film within the first window using an etching solution, and then cleaning the substrate; implanting N-type impurity ions into the first window, and diffusing and diffusing to form an N+ type emitter region and an oxide film on the surface; photolithographically creating a second window in the termination isolation region, removing the oxide film within the second window, and then performing wet etching using an etching solution to form an auxiliary trench; and photolithographically creating a second window in the termination isolation region. A third window is created using photolithography. After removing the oxide film within the third window, wet etching is performed using an etchant to form mesa deep trenches, thus obtaining a composite trench terminal structure including mesa deep trenches and auxiliary trenches. SIPOS films are deposited on the front and back sides of the N-type silicon substrate, allowing the SIPOS films to enter and cover the mesa deep trenches and auxiliary trenches. A glass paste is prepared and filled into the mesa deep trenches and auxiliary trenches, and then sintered to form a glass film. LTO films are deposited on the front and back sides of the N-type silicon substrate to form an outer protective film. Lead windows for the cathode and gate electrodes are formed on the front side of the N-type silicon substrate, and lead windows for the anode electrode are formed on the back side. Subsequently, the corresponding films within the lead windows are removed. A metal layer is deposited and the cathode, gate, and anode electrodes are formed through metal reverse etching.

[0015] Furthermore, the P-type impurity ion implantation uses aluminum ions as implantation ions, and the aluminum ions are implanted at an implantation angle perpendicular to the silicon wafer surface within a predetermined implantation energy range and a predetermined implantation dose range. Subsequently, a P-type base region is formed through diffusion and push-junction, so that the junction depth of the P-type base region is in the range of 54-58 μm and an oxide thin film is generated at the same time.

[0016] Furthermore, the N-type impurity ion implantation uses phosphorus ions as implantation ions, and the phosphorus ions are implanted within a predetermined implantation energy range and a predetermined implantation dose range and diffused to form an N+ type emitter region, so that the junction depth of the N+ type emitter region is in the range of 10-15 μm and an oxide thin film is generated at the same time.

[0017] Furthermore, the preparation sequence for forming the auxiliary trench and the mesa deep trench is as follows: the auxiliary trench is formed first, followed by the mesa deep trench. The depth of the auxiliary trench is in the range of 31-33 μm, and the depth of the mesa deep trench is in the range of 84-90 μm, so that the two form a deep and shallow trench structure. This preparation sequence is used to reduce the impact of photoresist accumulation in the deep trench during photolithography after the mesa deep trench has been formed on development and resist removal, and to avoid the two trenches from being etched at the same time, resulting in the trench depths becoming similar and thus failing to form a deep and shallow trench structure.

[0018] The beneficial effects of this invention are as follows: (1) The present invention proposes a composite terminal structure of deep and shallow trenches. By introducing an auxiliary trench with a suitable position and depth, the peak electric field at the sidewall of the deep trench on the mesa can be directly and efficiently attracted and dispersed. Thus, with the cost of only adding one photolithography and etching process, the breakdown voltage and reliability are significantly improved without significantly increasing the chip area.

[0019] (2) This invention proposes a bidirectional thyristor with a composite trench terminal structure. By adding a shallow auxiliary trench on the side of the mesa deep trench and optimizing the depth of the auxiliary trench, the peak electric field of the mesa deep trench sidewall can be effectively attracted and reduced, thereby improving the forward and reverse breakdown voltage of the device. Simulation results show that the auxiliary trench successfully reduced the peak electric field of the mesa deep trench sidewall from 234 kV / cm to 217 kV / cm and increased the average electric field strength to 1.7 kV / cm.

[0020] (3) The composite trench terminal structure proposed in this invention significantly increases the forward and reverse breakdown voltage from 985V / 928V of the traditional structure to 1310V / 1295V, an increase of more than 33%, which significantly improves the withstand voltage level and electrical performance reliability of the thyristor device. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the cross-sectional structure of a bidirectional thyristor with a composite trench terminal structure according to an embodiment of the present invention; Figure 2 yes Figure 1 A magnified view of a section at point A in the middle; Figure 3 This is a schematic diagram of the cross-sectional structure of a typical double-mesa bidirectional thyristor in a traditional structure; Figure 4 This is a graph showing the trend of forward breakdown voltage of a bidirectional thyristor with a composite trench terminal structure as a function of an auxiliary trench, according to an embodiment of the present invention. Figure 5 This is a graph showing the reverse breakdown voltage of a bidirectional thyristor with a composite trench terminal structure according to an embodiment of the present invention, as a function of the auxiliary trench. Figure 6This is a comparison diagram of the electric field distribution of a bidirectional thyristor with a composite trench terminal structure according to an embodiment of the present invention, and that of a conventional structure. Figure 7 This is a comparison diagram of the forward and reverse breakdown voltages of a bidirectional thyristor with a composite trench terminal structure according to an embodiment of the present invention. Figure 8 This is a schematic flowchart of a method for fabricating a bidirectional thyristor with a composite trench terminal structure according to an embodiment of the present invention.

[0023] In the picture: 1. N-type silicon substrate; 2. P-type base region; 3. N+ type emitter region; 4. Mesa deep trench; 5. Auxiliary trench; 6. Oxide thin film; 7. SIPOS thin film; 8. Glass film; 9. LTO thin film; 10. Cathode electrode; 11. Gate electrode; 12. Anode electrode. Detailed Implementation

[0024] To further illustrate the various embodiments, the present invention provides accompanying drawings, which are part of the disclosure of the present invention. These drawings are mainly used to illustrate the embodiments and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these drawings, those skilled in the art should be able to understand other possible implementation methods and the advantages of the present invention. The components in the drawings are not drawn to scale, and similar component symbols are generally used to represent similar components.

[0025] According to an embodiment of the present invention, a bidirectional thyristor with a composite trench terminal structure and a method for preparing the same are provided.

[0026] The present invention will now be further described in conjunction with the accompanying drawings and specific embodiments, such as... Figure 1 and Figure 2 As shown, according to an embodiment of the present invention, a bidirectional thyristor with a composite trench termination structure is provided. The bidirectional thyristor with the composite trench termination structure includes: an N-type silicon substrate 1; termination isolation regions are provided on both sides of the front and back sides of the N-type silicon substrate 1; two P-type base regions 2 are respectively disposed on the front and back sides of the N-type silicon substrate 1; the P-type base regions 2 are used to form a planar PN junction within the device together with the N-type silicon substrate 1; and an N+ type emitter region 3 is formed on the P-type base regions 2 away from the N-type silicon substrate 1. One side of substrate 1; several composite trench termination structures are disposed in the termination isolation region of N-type silicon substrate 1; the composite trench termination structures include mesa deep trenches 4 and auxiliary trenches 5 located on the side of mesa deep trenches 4; wherein, mesa deep trenches 4 are used to achieve physical isolation between the active region and adjacent devices through the trench structure, and auxiliary trenches 5 are used to attract and redistribute electric field lines during breakdown voltage to reduce the peak electric field at the sidewall of mesa deep trenches 4; oxide film 6 covers the side of P-type base region 2 away from N-type silicon substrate 1.

[0027] In one embodiment, the bidirectional thyristor with a composite trench terminal structure further includes: a SIPOS film 7 disposed inside the mesa deep trench 4 and the auxiliary trench 5, and on one side of the oxide film 6; wherein the surface of the SIPOS film 7 located inside the mesa deep trench 4 and the auxiliary trench 5 is sequentially covered with a glass film 8 and an LTO film 9, and the surface of the SIPOS film 7 located on the oxide film 6 is covered with an LTO film 9; a cathode electrode 10 and a gate electrode 11 located on the front side of the N-type silicon substrate 1, and an anode electrode 12 located on the back side of the N-type silicon substrate 1; wherein the cathode electrode 10 and the gate electrode 11 are used to lead out the cathode and realize gate control, respectively, and the anode electrode 12 is used to lead out the anode.

[0028] In one embodiment, the auxiliary trench 5 and the tabletop deep trench 4 are arranged adjacent to each other in the terminal isolation area, and the tabletop deep trench 4 has a first trench depth, while the auxiliary trench 5 has a second trench depth; the second trench depth is less than the first trench depth, and the second trench depth is within the range of one-third to two-fifths of the first trench depth.

[0029] In one embodiment, both the mesa deep trench 4 and the auxiliary trench 5 are trench structures formed by wet chemical etching. The trench structure includes sidewalls with an inclined angle and a bottom trench with a radius of curvature. The auxiliary trench 5, through the semiconductor interface formed by the bottom trench with a radius of curvature, shifts the electric field lines that were originally concentrated at the intersection of the sidewall of the mesa deep trench 4 and the planar PN junction in the device during breakdown voltage to the auxiliary trench 5, so as to suppress the local peak electric field at the intersection.

[0030] Specifically, the resistivity of the N-type silicon substrate 1 is 40-50 Ω·cm.

[0031] In one embodiment, the trench depth of the deep trench 4 is 84-90 μm, and the trench depth of the auxiliary trench 5 is 31-33 μm, which is used to help improve the forward breakdown voltage and reverse breakdown voltage of the device.

[0032] In one embodiment, the oxide film 6 serves as an electrical insulating layer and passivation layer, used to reduce the surface state density to stabilize the electrical characteristics of the device and to suppress metal or ion contamination during fabrication; the SIPOS film 7 serves as an electric field conditioning layer, used to optimize the electric field distribution on the terminal surface; the glass film 8 serves as an insulating dielectric layer distributed within the mesa deep trench 4 and auxiliary trench 5, used to block ion migration and to smooth the device surface after high-temperature treatment to facilitate step coverage; the LTO film 9 serves as the outermost protective film, used to cover and isolate to form a complete surface passivation and protective layer.

[0033] It should be noted that this invention proposes a bidirectional thyristor with a composite trench terminal structure, the structure of which is as follows: Figure 1 and Figure 2 As shown, by adding a shallower auxiliary trench to the side of the deep mesa trench and optimizing the depth of the auxiliary trench using Silvaco TCAD software, the peak electric field on the sidewall of the deep mesa trench can be effectively attracted and reduced, thereby improving the forward and reverse breakdown voltages of the device. Figure 4 and Figure 5 As shown, the forward and reverse breakdown voltages of the bidirectional thyristor device clearly exhibit maximum values ​​with increasing auxiliary trench depth. Simulation results indicate that the optimal auxiliary trench depth is approximately 32 μm, which is between 1 / 3 and 2 / 5 of the depth of the mesa trench. This provides a precise and reliable design window for process implementation. Figure 6 In the electric field distribution diagram shown, the auxiliary trench successfully reduced the peak electric field on the sidewall of the deep trench on the platform from 234 kV / cm to 217 kV / cm, and increased the average electric field strength to 1.7 kV / cm. Furthermore, as shown... Figure 7 As shown, the structure of this invention significantly increases the forward and reverse breakdown voltages from 985V / 928V in the conventional structure to 1310V / 1295V, an increase of more than 33%, which significantly improves the withstand voltage level and electrical performance reliability of the device.

[0034] It should also be noted that in this invention, the composite trench terminal structure consists of a mesa deep trench 4 and an auxiliary trench 5. The auxiliary trench 5 is located on the side of the mesa deep trench 4, and the two are arranged adjacent to each other in the terminal isolation area of ​​the chip. The depth of the mesa deep trench 4 is 84-90 μm, and the depth of the auxiliary trench 5 is 31-33 μm. The depth of the auxiliary trench 5 is significantly shallower than that of the mesa deep trench 4, and simulation optimization results indicate that its optimal depth is about 32 μm, which is between 1 / 3 and 2 / 5 of the depth of the mesa deep trench 4. Since the mesa deep trench 4 and the auxiliary trench 5 are formed by wet chemical etching, both of them have a certain tilt angle on the sidewalls and have a groove with a radius of curvature at the bottom. The interior of both the mesa deep trench 4 and the auxiliary trench 5 is filled with a SIPOS film 7, and the surface is successively covered with a glass film 8 and an LTO film 9, forming a complete surface passivation and protection system.

[0035] Among them, the mesa trench 4 undertakes the core and fundamental functions of physical isolation and termination formation in traditional mesa technology: through deep etching, deep trenches are formed in the silicon wafer, physically isolating the active area of ​​the device from adjacent devices, thereby establishing a high-voltage termination structure on the trench sidewalls. However, due to the small radius of curvature at the intersection of its sidewalls and the PN junction in the bulk plane, the electric field lines at this intersection point are extremely dense, generating local peak electric fields, which become a bottleneck restricting the breakdown voltage of the device. The auxiliary trench 5 is a structure specifically introduced to solve the above bottleneck: the auxiliary trench 5 creates a new semiconductor interface with a different radius of curvature on the side of the mesa trench 4. During withstand voltage testing, this new curved surface structure can actively attract and redistribute the electric field lines that were originally dense on the sidewalls of the mesa trench 4, making their distribution in the horizontal direction smoother and more linear. Therefore, the auxiliary trench 5 itself does not undertake the main isolation task; its main function is to optimize the electric field. The combination of the two forms a new composite trench termination structure, which has the new function of optimizing electric field distribution and suppressing peak electric field. Ultimately, it achieves a significant improvement in the breakdown voltage and electrical performance reliability of the device without significantly increasing the area and process complexity.

[0036] It should be added that the auxiliary groove 5 is located on the side of the deep groove 4 on the countertop, such as... Figure 1 As shown, the two are arranged adjacent to each other in the terminal isolation area of ​​the chip; the depth of the mesa deep trench 4 is 84-90 μm, and the depth of the auxiliary trench is 31-33 μm. The depth of the auxiliary trench is significantly shallower than that of the mesa deep trench, and the simulation optimization results indicate that its optimal depth is about 32 μm, which is between 1 / 3 and 2 / 5 of the depth of the mesa deep trench; since both the mesa deep trench and the auxiliary trench are formed by wet chemical etching, both have a certain tilt angle on the sidewalls and have a radius of curvature at the bottom; the interior of both trenches is filled with SIPOS film, and the surface is successively covered with glass film and LTO film, forming a complete surface passivation and protection system; In this invention, the mesa deep trench 4 performs the core and fundamental functions of physical isolation and termination formation in traditional mesa processes: through deep etching, deep trenches are formed in the silicon wafer, physically isolating the active region of the device from adjacent devices, thereby establishing a high-voltage termination structure on the trench sidewalls. However, due to the small radius of curvature at the intersection of its sidewalls and the PN junction in the bulk plane, the electric field lines at this point are extremely dense, generating local peak electric fields, which become a bottleneck restricting the breakdown voltage of the device. The auxiliary trench is a structure specifically introduced to solve the above bottleneck: the auxiliary trench creates a new semiconductor interface with a different radius of curvature on the side of the mesa deep trench. During withstand voltage testing, this new curved surface structure can actively attract and redistribute the electric field lines that were originally dense at the corners of the mesa deep trench, making their distribution in the horizontal direction smoother and more linear. In summary, the auxiliary trench itself does not undertake the main isolation task; its sole purpose is to optimize the electric field. The combination of the two forms a new composite trench terminal structure, which has the new function of optimizing electric field distribution and suppressing peak electric field. Ultimately, it achieves a significant improvement in breakdown voltage and electrical performance reliability without significantly increasing area and process complexity.

[0037] Among them, the oxide film 6 serves as an electrical insulating and passivation layer, reducing surface state density and stabilizing the electrical characteristics of the device. It also prevents metal or ion contamination during the manufacturing process. The SIPOS film 7 acts as an electric field conditioning layer, optimizing the surface electric field distribution. The glass film 8, distributed within the mesa trenches as an insulating dielectric layer, primarily acts to block ion migration. Additionally, at high temperatures, the molten glass smooths the device surface, facilitating step coverage. The LTO film 9, as the outermost protective film, primarily serves to cover and isolate the device. The cathode electrode 10 and gate electrode 11 are located on the front side of the device, while the anode electrode 12 is located on the back side; their positions are not random.

[0038] like Figure 8As shown, according to another embodiment of the present invention, a method for fabricating a bidirectional thyristor with a composite trench termination structure is also provided. The method includes: providing an N-type silicon substrate 1; implanting and diffusing P-type impurity ions on the front and back sides of the N-type silicon substrate 1, and during the diffusion process, forming P-type base regions 2 on the front and back sides and an oxide film 6 on the surface; creating a first window on the front and back sides of the N-type silicon substrate 1 by photolithography, removing the oxide film 6 within the first window using an etching solution, and then cleaning the substrate; implanting N-type impurity ions into the first window, and diffusing and diffusing to form an N+ type emitter region 3 and an oxide film 6 on the surface; creating a second window in the termination isolation region by photolithography, removing the oxide film 6 within the second window, and then performing wet etching using an etching solution to form an auxiliary trench 5; and creating a third window in the termination isolation region by photolithography. After removing the oxide film 6 in the third window, wet etching is performed using an etchant to form a mesa deep trench 4, thereby obtaining a composite trench terminal structure including the mesa deep trench 4 and auxiliary trench 5; SIPOS films 7 are deposited on the front and back sides of the N-type silicon substrate 1, so that the SIPOS films 7 enter and cover the mesa deep trench 4 and auxiliary trench 5; glass paste is prepared and filled into the mesa deep trench 4 and auxiliary trench 5, and then sintered to form a glass film 8; LTO films 9 are deposited on the front and back sides of the N-type silicon substrate 1 to form an outer protective film; lead windows for the cathode electrode 10 and gate electrode 11 are formed on the front side of the N-type silicon substrate 1, and lead windows for the anode electrode 12 are formed on the back side, and then the corresponding films in the lead windows are removed; a metal layer is deposited and the cathode electrode 10, gate electrode 11 and anode electrode 12 are formed by metal reverse etching.

[0039] Specifically, the etching solution consists of ammonium fluoride and hydrofluoric acid; the etching solution is formed by mixing nitric acid, glacial acetic acid and hydrofluoric acid.

[0040] In one embodiment, aluminum ions are used as implanted ions for P-type impurity ion implantation, and the aluminum ions are implanted at an implantation angle perpendicular to the silicon wafer surface within a predetermined implantation energy range and a predetermined implantation dose range. Subsequently, a P-type base region 2 is formed by diffusion and push-junction, so that the junction depth of the P-type base region 2 is in the range of 54-58 μm and an oxide film 6 is generated at the same time.

[0041] In one embodiment, phosphorus ions are used as implanted ions for N-type impurity ion implantation. The phosphorus ions are implanted within a predetermined implantation energy range and a predetermined implantation dose range and diffused to form an N+ type emitter region 3, so that the junction depth of the N+ type emitter region 3 is in the range of 10-15 μm and an oxide film 6 is generated at the same time.

[0042] In one embodiment, the preparation order of forming the auxiliary trench 5 and the mesa deep trench 4 is as follows: the auxiliary trench 5 is formed first, followed by the mesa deep trench 4. The trench depth of the auxiliary trench 5 is in the range of 31-33 μm, and the trench depth of the mesa deep trench 4 is in the range of 84-90 μm, so that the two form a deep and shallow trench structure. This preparation order is used to reduce the impact of photoresist accumulation in the deep trench during photolithography after the mesa deep trench 4 has been formed on development and resist removal, and to avoid the two trenches from being etched at the same time, resulting in the trench depths becoming similar and thus failing to form a deep and shallow trench structure.

[0043] It should be noted that the specific manufacturing process of the bidirectional thyristor with a composite trench terminal structure provided by the present invention is as follows: 1. Preparation of the silicon substrate, i.e., selecting a substrate with a resistivity of 40-50 Ω·cm and a thickness of 260±5 μm. <111> N-type silicon substrate with crystal orientation 1; 2. Ion implantation of P-type impurities: Aluminum ions are implanted onto the front and back sides of the silicon wafer using an ion implanter. The implantation energy is 120-150 keV, and the implantation dose is 1.8E14~2.2E14 / cm². 2 The injection angle is 0°; 3. P-type base region 2 diffusion: The silicon wafer is placed in a diffusion furnace, a protective gas is introduced, and diffusion and bonding are carried out at high temperature to form P-type base regions 2 on the front and back sides of the silicon wafer, and an oxide film 6 is generated on the surface. The final junction depth of P-type base region 2 is 54-58μm. 4. Photolithography of N+ type emitter region 3: Photoresist is uniformly coated on the front and back sides of the silicon wafer using a spin coater. After pre-baking, exposure, development, and hardening processes, the N+ type emitter region 3 window is opened. The oxide layer film 6 inside the window is etched away using an etching solution of ammonium fluoride (NH4F): hydrofluoric acid (HF) = 5:1. The photoresist is removed, the wafer is cleaned, and then dried. 5. Ion implantation of N-type impurities: Phosphorus ions are implanted into the window opened in step 4 using an ion implanter. The implantation energy is 50-80 keV, and the implantation dose is 1.5E15~3E15 / cm³. 2 The injection angle is 0°; 6. N+ type emitter region 3 diffusion: The silicon wafer is placed in a diffusion furnace, a protective gas is introduced, and diffusion and bonding are carried out at high temperature to form N+ type emitter region 3, and an oxide thin film 6 is generated on the surface. The final junction depth of N+ type emitter region 3 is 10-15μm. 7. Photolithography auxiliary trench 5 area, that is, the photoresist is evenly coated on the front and back of the silicon wafer by a spin coater. After the pre-baking, exposure, development and hardening processes, the auxiliary trench 5 window is opened. The oxide layer film 6 inside the window is etched away by an etching solution of ammonium fluoride (NH4F): hydrofluoric acid (HF) = 5:1. Then, it is cleaned and dried. 8. Table surface etching I, i.e., etching the silicon in the window opened in step 7 with an etching solution of nitric acid (HNO3): glacial acetic acid (HAC): hydrofluoric acid (HF) = 5:4:4, forming auxiliary trenches 5 with a depth of 31-33μm, removing adhesive, cleaning, and spin drying; 9. Photolithography deep trench 4 area: Photoresist is evenly coated on the front and back of the silicon wafer using a spin coater. After pre-baking, exposure, development and hardening processes, the deep trench 4 window is opened on the surface. The oxide layer film 6 inside the window is etched away using an etching solution of ammonium fluoride (NH4F): hydrofluoric acid (HF) = 5:1. The wafer is then cleaned and dried. 10. Mesa etching II, which involves etching the silicon inside the window opened in step 9 with an etching solution of nitric acid (HNO3): glacial acetic acid (HAC): hydrofluoric acid (HF) = 5:4:4, forming a mesa deep trench 4 with a depth of 84-90μm. Then, remove the adhesive, clean, and spin dry. It should also be noted that the reason for adopting the sequence of making shallow trenches (steps 7-8) followed by deep trenches (steps 9-10) in this invention is as follows: if the mesa deep trenches are made first and then the auxiliary trenches are made, the photoresist is prone to accumulate in the mesa deep trenches when making the auxiliary trenches, which will affect the subsequent development and photoresist removal; if the mesa deep trenches and auxiliary trenches are made together, the etching solution of nitric acid (HNO3): glacial acetic acid (HAC): hydrofluoric acid (HF) = 5:4:4 can only form two trenches of the same depth, which cannot form the structure of this invention; therefore, this invention adopts the process sequence of making auxiliary trenches first and then mesa deep trenches.

[0044] 11. Deposit SIPOS film 7, i.e., deposit SIPOS film 7 on the front and back sides of the silicon wafer using an LPCVD device, with a thickness of 1.6-2um; 12. Prepare glass membrane 8 by mixing an adhesive with ethyl cellulose and butyl carbitol in a ratio of (1.6-2.0) g to 100 ml, and mixing it with glass powder to form a glass paste. Fill the deep groove 4 and auxiliary groove 5 of the table surface with the glass paste by scraping, and form glass membrane 8 by low-temperature sintering at a temperature of 450-470℃ for 25-35 min. The final thickness of glass membrane 8 is 15-20 μm. 13. Deposit LTO thin film 9, that is, deposit LTO thin film 9 on the front and back sides of the silicon wafer using LPCVD equipment, with a thickness of 0.3-0.5um; 14. Photolithography leads: Photoresist is uniformly coated onto the front and back sides of the silicon wafer using a spin coater. After pre-baking, exposure, development, and hardening processes, windows for the cathode electrode 10 and gate electrode 11 are opened on the front side of the silicon wafer, and windows for the anode electrode 12 are opened on the back side of the silicon wafer. The oxide film 6 and LTO film 9 inside the windows are etched away using an etching solution of ammonium fluoride (NH4F): hydrofluoric acid (HF) = 5:1. The SIPOS film 7 inside the windows is etched away using an etching solution of nitric acid (HNO3): glacial acetic acid (HAC): hydrofluoric acid (HF) = 20:1:1. The photoresist is removed, the wafer is cleaned, and then dried. 15. Deposit a metal layer, that is, deposit a thin metal film on the front and back sides of the silicon wafer using a high-vacuum electron beam evaporation device, with a thickness of 3~15μm; 16. Metal reverse etching: Photoresist is evenly coated on the front and back sides of a silicon wafer using a spin coater. After pre-baking, exposure, development, and hardening processes, reverse etching windows are opened. The metal film inside the window is removed using a metal etching solution. The photoresist is removed, the wafer is cleaned, and dried. The remaining metals are the cathode electrode 10, the gate electrode 11, and the anode electrode 12.

[0045] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A bidirectional thyristor having a composite trench termination structure, characterized by, include: N-type silicon substrate (1); terminal isolation areas are provided on both sides of the front and both sides of the back of the N-type silicon substrate (1); Two P-type base regions (2) are respectively disposed on the front and back sides of the N-type silicon substrate (1); the P-type base regions (2) are used together with the N-type silicon substrate (1) to form a planar PN junction in the device; The N+ type emitter region (3) is located on the side of the P type base region (2) away from the N- type silicon substrate (1); Several composite trench termination structures are disposed in the termination isolation region of the N-type silicon substrate (1); the composite trench termination structure includes a mesa deep trench (4) and an auxiliary trench (5) located on the side of the mesa deep trench (4); wherein, the mesa deep trench (4) is used to achieve physical isolation between the active region and adjacent devices through the trench structure, and the auxiliary trench (5) is used to attract and redistribute electric field lines during withstand voltage to reduce the peak electric field at the sidewall of the mesa deep trench (4); An oxide film (6) covers the side of the P-type base region (2) away from the N-type silicon substrate (1); The auxiliary groove (5) and the deep groove on the tabletop (4) are arranged adjacent to each other in the terminal isolation area, and the deep groove on the tabletop (4) has a first groove depth, and the auxiliary groove (5) has a second groove depth; the second groove depth is less than the first groove depth, and the second groove depth is in the range of one-third to two-fifths of the first groove depth. The mesa deep trench (4) and the auxiliary trench (5) are both trench structures formed by wet chemical etching. The trench structure includes sidewalls with an inclined angle and bottom trenches with a radius of curvature. The auxiliary trench (5) forms a semiconductor interface through the bottom trench with a radius of curvature, so that the electric field lines that were originally concentrated at the intersection of the sidewall of the mesa deep trench (4) and the planar PN junction in the device during withstand voltage are shifted to the auxiliary trench (5) to suppress the local peak electric field at the intersection.

2. A triac having a composite trench termination structure according to claim 1, wherein, Also includes: SIPOS film (7) is disposed inside the deep groove (4) and the auxiliary groove (5) of the tabletop, and on one side of the oxide film (6); wherein, the surface of the SIPOS film (7) located inside the deep groove (4) and the auxiliary groove (5) is sequentially covered with a glass film (8) and an LTO film (9), and the surface of the SIPOS film (7) located on one side of the oxide film (6) is covered with an LTO film (9); A cathode electrode (10) and a gate electrode (11) are located on the front side of the N-type silicon substrate (1), and an anode electrode (12) is located on the back side of the N-type silicon substrate (1); wherein the cathode electrode (10) and the gate electrode (11) are used to lead out the cathode and realize gate control respectively, and the anode electrode (12) is used to lead out the anode.

3. A triac having a composite trench termination structure as defined in claim 1, wherein, The groove depth of the deep groove (4) on the platform is 84-90μm, and the groove depth of the auxiliary groove (5) is 31-33μm, which are used to improve the forward breakdown voltage and reverse breakdown voltage of the device.

4. A triac having a composite trench termination structure according to claim 2, wherein, The oxide film (6) serves as an electrical insulating layer and a passivation layer, used to reduce the surface state density to stabilize the electrical properties of the device and to suppress metal or ion contamination during the fabrication process; The SIPOS thin film (7) serves as an electric field conditioning layer to optimize the electric field distribution on the terminal surface; The glass film (8) is distributed in the deep trench (4) and the auxiliary trench (5) as an insulating medium layer to block the migration of insulators and to make the device surface smooth after high temperature treatment so as to facilitate step coverage. The LTO film (9) serves as the outermost protective film, used to cover and isolate the surface to form a complete passivation and protective layer.

5. A method for producing a bidirectional thyristor with a composite trench termination structure, for producing a bidirectional thyristor with a composite trench termination structure according to any one of claims 1 to 4, characterized in that The preparation method includes: Provide an N-type silicon substrate (1); P-type impurity ions are implanted and diffused on the front and back sides of the N-type silicon substrate (1), and during the diffusion process, P-type base regions (2) and oxide film (6) are formed on the front and back sides. The first window is made on the front and back sides of the N-type silicon substrate (1) by photolithography, and the oxide film (6) in the first window is removed by etching solution and then the resist is removed and cleaned. N-type impurity ions are implanted into the first window and N+ type emitter region (3) and oxide film (6) on the surface are formed by diffusion and bonding. A second window is created in the terminal isolation area by photolithography. After removing the oxide film (6) in the second window, wet etching is performed using an etchant to form an auxiliary trench (5). In the terminal isolation area, a third window is opened by photolithography. After removing the oxide film (6) in the third window, wet etching is performed using an etching solution to form a mesa deep trench (4), thereby obtaining a composite trench terminal structure including mesa deep trench (4) and auxiliary trench (5). SIPOS films (7) are deposited on the front and back sides of the N-type silicon substrate (1) so that the SIPOS films (7) enter and cover the mesa deep trench (4) and the auxiliary trench (5). Prepare glass paste and fill the deep groove (4) of the table and the auxiliary groove (5) with glass paste, and sinter to form a glass film (8). An outer protective film is formed by depositing LTO thin films (9) on the front and back sides of the N-type silicon substrate (1); Lead windows for a cathode electrode (10) and a gate electrode (11) are formed on the front side of the N-type silicon substrate (1), and lead windows for an anode electrode (12) are formed on the back side. The corresponding thin films inside the lead windows are then removed. A metal layer is deposited and a cathode electrode (10), a gate electrode (11), and an anode electrode (12) are formed by metal reverse etching.

6. The method for fabricating a bidirectional thyristor with a composite trench terminal structure according to claim 5, characterized in that, The P-type impurity ion implantation uses aluminum ions as implantation ions, and the aluminum ions are implanted at an implantation angle perpendicular to the silicon wafer surface within a predetermined implantation energy range and a predetermined implantation dose range. Subsequently, a P-type base region (2) is formed through diffusion and push-junction, so that the junction depth of the P-type base region (2) is in the range of 54-58 μm and the oxide layer film (6) is generated at the same time.

7. The method for fabricating a bidirectional thyristor with a composite trench terminal structure according to claim 5, characterized in that, The N-type impurity ion implantation uses phosphorus ions as implantation ions, and the phosphorus ions are implanted within a predetermined implantation energy range and a predetermined implantation dose range and diffused to form an N+ type emission region (3), so that the junction depth of the N+ type emission region (3) is in the range of 10-15 μm and the oxide layer film (6) is generated at the same time.

8. The preparation method according to claim 5, characterized in that, The preparation order of forming the auxiliary groove (5) and forming the mesa deep groove (4) is as follows: first form the auxiliary groove (5), then form the mesa deep groove (4), and the groove depth of the auxiliary groove (5) is in the range of 31-33μm, and the groove depth of the mesa deep groove (4) is in the range of 84-90μm, so that the two form a deep and shallow groove structure. The preparation sequence is used to reduce the impact of photoresist buildup in the deep trenches during photolithography after the formation of the mesa deep trenches (4), on development and removal, and to avoid the two trenches being etched at the same time, resulting in the trenches having similar depths and thus failing to form the deep and shallow trench structure.

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