LSTM neural network-based constant temperature crystal oscillator time-keeping method and system

Abstract

The application discloses a constant temperature crystal oscillator time keeping method and system based on an LSTM neural network, and the method comprises the following steps: collecting clock difference, environmental temperature, time sequence and frequency control quantity data in real time to construct a training sample set; taking historical temperature and time sequence as input and filtered frequency control quantity as output, training an LSTM neural network to obtain a frequency drift prediction model; when satellite signals are available, updating the model online with new data; when the signals are interrupted, switching to a time keeping prediction mode, inputting real-time temperature and time sequence into the model to predict frequency control quantity; generating a voltage control voltage according to the predicted value to compensate for the frequency of the constant temperature crystal oscillator, and maintaining the accuracy of the local time reference. The application captures the nonlinear time-varying characteristics of temperature-aging coupling through the LSTM, realizes model calculation and real-time control decoupling in combination with a dual-core architecture, realizes nanosecond-level long-term time keeping accuracy in a satellite denial environment, and has online self-learning ability and mode switching smoothness.

Description

Technical Field

[0001] This invention relates to the field of precision time and frequency technology, and in particular to a method and system for keeping time at a temperature-controlled crystal oscillator based on an LSTM neural network. Background Technology

[0002] In modern communications, power, finance, and defense, high-precision time synchronization is a crucial foundation for ensuring the coordinated operation of systems. Oven-controlled crystal oscillators (OCXOs), as the core component for timekeeping, rely on frequency compensation techniques to maintain long-term stability in satellite-denied environments. Traditional timekeeping methods primarily employ models such as least-squares fitting, lookup tables, or Kalman filtering, achieving frequency prediction and compensation by establishing linear or low-dimensional mappings between temperature and frequency or time and frequency.

[0003] However, cryogenic crystal oscillators exhibit significant nonlinear and time-varying characteristics in practical operation. Their frequency drift is caused by the combined effects of multiple physical field coupling factors, such as temperature fluctuations, long-term aging, and internal stress release, resulting in complex dynamic patterns. Existing technical solutions, based on fixed-parameter models, struggle to accurately characterize the high-dimensional nonlinear time-varying characteristics of aging-temperature coupling and lack adaptability to individual crystal oscillator differences. Once the operating environment shifts or the crystal enters different aging stages, the preset model fails to track the drift trend, leading to rapid degradation in timing accuracy. Especially in deny-of-sight environments with long-term satellite signal interruptions, traditional methods can achieve timing errors on the order of microseconds or even milliseconds within 30 days, failing to meet the stringent nanosecond-level accuracy requirements of modern systems. Therefore, there is an urgent need for a frequency prediction method capable of deeply exploring multi-dimensional temporal coupling relationships and possessing online self-learning capabilities to overcome the bottlenecks in accuracy and adaptability of traditional models. Summary of the Invention

[0004] Therefore, the present invention provides a timekeeping method and system for isothermal crystal oscillators based on LSTM neural networks to solve the aforementioned problems existing in the prior art.

[0005] To achieve the above objectives, this invention provides a time-keeping method for a temperature-controlled crystal oscillator based on an LSTM neural network, comprising:

[0006] Step S1: Real-time acquisition of clock difference data, ambient temperature data, timing information and frequency control data of the isothermal crystal oscillator, and preprocessing to obtain a training sample set;

[0007] Step S2: Using the ambient temperature data and time series information collected at historical moments as input features, and the filtered frequency control data as the prediction target, a long short-term memory neural network model is constructed, and the frequency drift prediction model is obtained by training according to the training sample set.

[0008] Step S3: When satellite signals are available, continuously update the frequency drift prediction model online using newly acquired data;

[0009] Step S4: When the satellite signal is interrupted, switch to the time-keeping prediction mode, and input the real-time collected temperature data and time sequence information into the frequency drift prediction model for prediction to obtain the frequency control quantity;

[0010] Step S5: Generate a voltage-controlled voltage according to the frequency control quantity, perform frequency compensation on the temperature-controlled crystal oscillator, and maintain the timekeeping accuracy of the local time reference.

[0011] Furthermore, the process of step S2 includes:

[0012] Once the accumulated data reaches the preset window length, the model training process is automatically triggered to construct a single-layer long short-term memory network structure and configure a preset number of hidden layer neurons.

[0013] The ambient temperature data and time series information collected at historical moments are used as multi-dimensional input feature vectors, and the frequency control data after filtering and smoothing are used as the target output of supervised learning.

[0014] An adaptive moment estimation optimizer is used with an adjustable initial learning rate, and the learning rate is dynamically and exponentially decayed during training based on the performance on the validation set.

[0015] The model parameters are optimized by a preset number of training iterations, and the mean square error function is used to measure the deviation between the predicted value and the true value to obtain the frequency drift prediction model.

[0016] Furthermore, the process of dynamically and exponentially decaying the learning rate based on the validation set performance during training includes:

[0017] After each training iteration, the current batch of data is divided into a training subset and a validation subset.

[0018] The model parameters are updated using the training subset, and the prediction error index is calculated synchronously on the validation subset.

[0019] At the end of each epoch, exponential decay is automatically performed, and the current learning rate is exponentially reduced according to the preset decay coefficient. After the reduction, the learning rate is reconfigured into the optimizer.

[0020] Continue the iterative training process until all training cycles are completed or the learning rate decays to the preset minimum threshold.

[0021] Furthermore, the process of step S3 includes:

[0022] While satellite signals are available, the proportional-integral control discipline mode is maintained, and the online update process for the frequency drift prediction model is initiated.

[0023] The sample training set is continuously accumulated in the local cache unit;

[0024] When the accumulated data reaches the preset update window length, the model update mechanism is automatically triggered, and the frequency drift prediction model is fine-tuned or locally updated using the newly added data.

[0025] After the model update is completed, the local cache unit is cleared, and the data collection and accumulation process is repeated to achieve periodic online adaptive learning.

[0026] Furthermore, the process of fine-tuning or locally updating the parameters of the frequency drift prediction model using the new data includes:

[0027] After gradient calculation and parameter optimization are completed on the second processing core, pruning and quantization operations are performed on the updated frequency drift prediction model, and it is converted into a lightweight inference format.

[0028] The optimized and compressed frequency drift prediction results are synchronously transmitted to the first processing core via shared memory.

[0029] At the start of the next control cycle, the first processing core reads the new frequency drift prediction results from the shared memory and performs frequency control, achieving seamless integration between the model update process and the real-time control task.

[0030] Furthermore, the process of step S4 includes:

[0031] After the first processing core detects the satellite signal interruption trigger condition, it immediately disconnects the proportional-integral control discipline mode and starts the timekeeping forecast mode.

[0032] The first processing core stops outputting real-time calculated control quantities to the digital-to-analog converter, and simultaneously writes the real-time collected temperature data and timing information asynchronously into the shared memory.

[0033] The second processing core continuously monitors the shared memory status. When new data is detected being written, it reads it and inputs it into the frequency drift prediction model to perform forward inference calculations and generate the predicted value of the frequency control quantity at the current moment.

[0034] The second processing core writes the predicted value back to the shared memory. The first processing core reads the predicted value and assigns it to the digital-to-analog converter module through a programmable logic device to generate a corresponding voltage-controlled voltage to compensate the frequency of the temperature-controlled crystal oscillator.

[0035] Furthermore, the process of the second processing core performing forward inference computation includes:

[0036] After reading the temperature data and time-series information from shared memory, they are format-converted and dimension-reconstructed to obtain a tensor structure.

[0037] The tensor structure is used as input to the frequency drift prediction model for inference calculation to generate initial prediction results;

[0038] Boundary value verification is performed on the initial prediction result. If the predicted value is detected to exceed the preset DAC control word range, an exception handling mechanism is triggered to perform forced truncation and record the exception event.

[0039] The calibrated frequency control quantity prediction value is converted into a new format and then written back to shared memory.

[0040] Furthermore, the triggering conditions for entering the timekeeping forecast mode include:

[0041] Satellite signal strength is detected to be below a preset threshold or completely interrupted;

[0042] The frequency drift prediction model has completed its initial training and reached convergence.

[0043] Furthermore, the process of step S5 includes:

[0044] The first processing core reads the predicted value of the frequency control quantity from the shared memory, converts the predicted value into a digital control signal through a programmable logic device, and assigns it to the digital-to-analog converter.

[0045] The digital-to-analog converter converts the digital control signal into an analog voltage-controlled voltage, which is then applied to the voltage-controlled input terminal of the temperature-controlled crystal oscillator.

[0046] The temperature-controlled crystal oscillator adjusts its internal oscillation frequency according to the voltage-controlled voltage to obtain a frequency output signal;

[0047] The programmable logic device generates a local second pulse signal based on the frequency output signal and maintains phase continuity through a phase-locked loop mechanism;

[0048] The first processing core continuously monitors the stability of the frequency output signal and the local second pulse signal to ensure long-term timekeeping accuracy of the time reference during satellite signal interruptions.

[0049] On the other hand, the present invention also provides a time-keeping system for a temperature-controlled crystal oscillator based on an LSTM neural network, comprising:

[0050] The data acquisition module is used to collect clock difference data, ambient temperature data, timing information and frequency control data of the isothermal crystal oscillator in real time and preprocess them to obtain a training sample set.

[0051] The model training module, connected to the data acquisition module, is used to construct a long short-term memory neural network model by using the environmental temperature data and time series information collected at historical moments as input features and the filtered frequency control data as the prediction target, and to train the model based on the training sample set to obtain a frequency drift prediction model.

[0052] An online update module, connected to the model training module, is used to continuously update the frequency drift prediction model online using newly acquired data when satellite signals are available.

[0053] The time-keeping forecast module, connected to the online update module, is used to switch to the time-keeping forecast mode when the satellite signal is interrupted, and input the real-time collected temperature data and time sequence information into the frequency drift prediction model for prediction to obtain the frequency control quantity;

[0054] The frequency compensation module, connected to the timekeeping prediction module, is used to generate a voltage-controlled voltage based on the frequency control quantity to perform frequency compensation on the temperature-controlled crystal oscillator and maintain the timekeeping accuracy of the local time reference.

[0055] Compared with existing technologies, the advantages of this invention are as follows: This invention deeply mines the nonlinear time-varying coupling relationship between temperature and crystal oscillator aging through an LSTM neural network, and utilizes its gating mechanism to adaptively learn the multi-dimensional time-series mapping law of historical clock bias, ambient temperature, and frequency control quantities. The constructed frequency drift prediction model can detect the OCXO frequency shift trend in advance under satellite-denied environments. The dual-core collaborative architecture decouples model training and inference from real-time docile control, enabling the embedded system to efficiently execute complex deep learning algorithms under resource-constrained conditions, while ensuring the determinism and real-time performance of the control loop. The online update mechanism continuously accumulates newly acquired data... The model undergoes incremental fine-tuning to dynamically track the long-term evolution of crystal oscillator aging characteristics, avoiding the problem of fixed-parameter models failing over time. During timekeeping prediction mode switching, the digital phase-locked loop captures phase errors and smoothly corrects them cycle by cycle, effectively suppressing phase jumps caused by mode switching. Combined with the voltage-controlled voltage generated by the frequency control quantity predicted by the model, it accurately compensates the OCXO, ensuring that the local second pulse signal remains continuous and stable during satellite outages. This invention utilizes the inherent correlation between LSTM prediction, voltage compensation, and phase locking to achieve nanosecond-level long-term timekeeping accuracy under satellite rejection conditions, which is significantly better than traditional polynomial fitting or Kalman filtering methods. Attached Figure Description

[0056] Figure 1 A flowchart illustrating the timekeeping method for isothermal crystal oscillators based on LSTM neural networks provided by this invention;

[0057] Figure 2This is a flowchart illustrating step S2 in the LSTM neural network-based timekeeping method for isothermal crystal oscillators provided by the present invention.

[0058] Figure 3 A schematic diagram of the structure of the isothermal crystal oscillator timekeeping system based on LSTM neural network provided by the present invention. Detailed Implementation

[0059] To make the objectives and advantages of the present invention clearer, the present invention will be further described below with reference to embodiments; it should be understood that the specific embodiments described herein are merely for explaining the present invention and are not intended to limit the present invention.

[0060] Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are merely illustrative of the technical principles of the present invention and are not intended to limit the scope of protection of the present invention.

[0061] It should be noted that in the description of this invention, the terms "upper", "lower", "left", "right", "inner", "outer", etc., which indicate the direction or positional relationship, are based on the direction or positional relationship shown in the drawings. This is only for the convenience of description and is not intended to indicate or imply that the device or element must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this invention.

[0062] Furthermore, it should be noted that, in the description of this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0063] Please see Figure 1 As shown, this invention provides a time-keeping method for isothermal crystal oscillators based on LSTM neural networks, comprising:

[0064] Step S1: Real-time acquisition of clock difference data, ambient temperature data, timing information and frequency control data of the isothermal crystal oscillator, and preprocessing to obtain a training sample set;

[0065] Specifically, the system utilizes a heterogeneous dual-core architecture. Data acquisition is performed by the first processing core (CPU0), while data reading and preprocessing are performed by the second processing core (CPU1). The two cores interact asynchronously via shared physical memory. Within each control cycle, the first processing core analyzes satellite navigation messages and dual-frequency carrier phase observations using a connected GNSS receiver, calculating the clock difference between the local isothermal crystal oscillator and standard time in real time. Simultaneously, it reads the current ambient temperature data from a temperature sensor, records the timing information generated during system operation (including timestamps and cumulative runtime), and acquires the digital control output (i.e., frequency control, represented as DAC control words) from the proportional-integral controller.

[0066] The above four types of data constitute the raw sampled data set. The first processing core writes the raw sampled data set obtained in each control cycle into a circular buffer of shared memory with a fixed data structure. The shared memory is implemented using dual-port RAM or on-chip shared memory, which has concurrent read and write capabilities. The second processing core continuously monitors the accumulated data in the shared memory. When the accumulated data reaches the preset window length (e.g., 720 sampling points, corresponding to 1 hour of continuous sampling data), the data preprocessing process is automatically triggered. The second processing core reads the raw sampled data in batches from the shared memory. First, it performs moving average filtering on the frequency control quantity data sequence, with the filtering window length set to 50 sampling points, to smooth high-frequency noise and short-term disturbances and extract stable control quantities that reflect the long-term dynamic trend of the crystal oscillator. Then, it performs Z-score standardization on the input features (including temperature data and time series information), that is, it calculates the mean and standard deviation of each feature sequence, converting the raw data into standardized data with a mean of 0 and a standard deviation of 1, to accelerate the convergence speed of subsequent model training and improve numerical stability. The filtered and standardized data constitute the training sample set, where each sample contains standardized temperature and time-series features as input vectors, and filtered frequency control parameters as label values. This training sample set is stored in the local memory of the second processing core.

[0067] Step S2: Using the ambient temperature data and time series information collected at historical moments as input features, and the filtered frequency control data as the prediction target, a long short-term memory neural network model is constructed, and the frequency drift prediction model is obtained by training according to the training sample set.

[0068] Specifically, such as Figure 2 As shown, the process of step S2 includes:

[0069] Step S21: After the data accumulation reaches the preset window length, the model training process is automatically triggered to construct a single-layer long short-term memory network structure and configure a preset number of hidden layer neurons.

[0070] Specifically, when the second processing kernel detects that the number of accumulated samples in the local cache has reached the preset window length, it automatically triggers the model training process. This embodiment constructs a single-layer long short-term memory neural network structure with 128 neurons in the hidden layer. Each neuron uses the tanh activation function to achieve a non-linear transformation. The input layer dimension is set to 2, corresponding to two features: environmental temperature data and time-series information; the output layer dimension is set to 1, corresponding to the predicted value of the frequency control variable. To mitigate the risk of overfitting, a dropout layer is added after the LSTM layer, with a dropout rate set to 0.2. The model weights are initialized using the Xavier uniform distribution initialization method to ensure stable gradient propagation in the early stages of training. The entire network structure is constructed using a static graph built through the TensorFlow framework and converted to TensorFlow Lite format to adapt to embedded deployment environments.

[0071] Step S22: Use the ambient temperature data and time series information collected at historical moments as multidimensional input feature vectors, and use the frequency control data that has been filtered and smoothed as the target output of supervised learning.

[0072] Specifically, the second processing core organizes the training sample set obtained in step S1 into a supervised learning dataset according to the time series order. A sliding window method is used to construct input-output pairs: standardized temperature data and time series information from the N consecutive sampling points before the current time are used as multi-dimensional input feature vectors, and the filtered frequency control quantity data corresponding to the Nth sampling point is used as the target output label for supervised learning. In this embodiment, N is set to 10, meaning the frequency control quantity at the current time is predicted using historical data from the previous 10 time points. During training, the entire sample set is randomly divided into an 85% training set and a 15% validation set. The validation set is used to monitor the model's generalization performance and ensure that overfitting does not occur during training. The data batch size is set to 32, and a time series batch sampling strategy is adopted to ensure that the samples within each batch have temporal continuity.

[0073] Step S23: An adaptive moment estimation optimizer is used and an adjustable initial learning rate is set. During training, the learning rate is dynamically and exponentially decayed based on the performance of the validation set.

[0074] Specifically, the second processing core first initializes the Adaptive Moment Estimation (Adam) optimizer, configuring the following core parameters: the first-order moment estimation exponential decay rate (beta1) is set to 0.9 to control the smoothness of the gradient mean estimation; the second-order moment estimation exponential decay rate (beta2) is set to 0.999 to control the smoothness of the uncentered variance estimation of the gradient; and the numerical stability constant is set to 1 × 10⁻⁶. -8 To prevent numerical overflow caused by a denominator of zero; the initial learning rate is set to 0.01 as the step size benchmark at the beginning of training.

[0075] Specifically, the process of dynamically and exponentially decaying the learning rate based on the validation set performance during training includes:

[0076] After each training iteration, the current batch of data is divided into a training subset and a validation subset.

[0077] Specifically, the second processing core shuffles the current batch of data according to time sequence and randomly divides it into a training subset (80%) and a validation subset (20%). A stratified sampling strategy is used to ensure the validation subset is representative of the temporal distribution and avoids outliers from specific time periods dominating the validation results. The training subset is used to calculate gradients and update model parameters, while the validation subset is only used for forward propagation to calculate prediction errors and does not participate in gradient calculation or parameter updates.

[0078] The model parameters are updated using the training subset, and the prediction error index is calculated synchronously on the validation subset.

[0079] Specifically, forward inference is performed using the validation subset data. Input features (temperature data and time-series information) are fed into the current long short-term memory neural network model to obtain a sequence of predicted frequency control values. The root mean square error (RMSE) of the predictions is calculated as a performance metric for the validation set; its mathematical expression is as follows:

[0080]

[0081] Where m is the number of samples in the validation subset. Let j be the true frequency control value of the j-th sample. The second processing kernel calculates the model's predicted values ​​for each epoch. The value is stored in the monitoring array.

[0082] At the end of each epoch, exponential decay is automatically performed, and the current learning rate is exponentially reduced according to the preset decay coefficient. After the reduction, the learning rate is reconfigured into the optimizer.

[0083] Specifically, after the decay is triggered, the second processing core exponentially reduces the current learning rate according to a preset decay coefficient of 0.95, i.e., the new learning rate. ,in, Let k be the initial learning rate and k be the current epoch. After each decay, the new learning rate is reconfigured into the Adam optimizer.

[0084] Continue the iterative training process until all training cycles are completed or the learning rate decays to the preset minimum threshold.

[0085] Specifically, to avoid training stagnation due to an excessively low learning rate, a minimum threshold (i.e., the minimum learning rate threshold) is set to 1×10.-5 Once the learning rate decays to this threshold, it will no longer be adjusted downwards.

[0086] Step S24: Optimize the model parameters by a preset number of training iterations, and use the mean square error function to measure the deviation between the predicted value and the true value to obtain the frequency drift prediction model.

[0087] Specifically, the preset number of training iterations is 150. In each iteration, the Adam optimizer automatically adjusts the model weights and bias parameters based on the calculated gradients to minimize the loss function. The loss function uses the mean squared error (MSE) function, whose mathematical expression is:

[0088]

[0089] Where M is the batch sample size. Let be the true frequency control value of the i-th sample. The first kernel calculates the MSE values ​​on the training and validation sets after each epoch and plots the loss curves to monitor the convergence trend. The model is considered complete when the loss curves on the training and validation sets plateau and the validation set loss no longer decreases. The final model parameter file is stored in non-volatile memory and contains network weights, biases, input / output scaling parameters, and model structure metadata for online updates and inference deployment.

[0090] Step S3: When satellite signals are available, continuously update the frequency drift prediction model online using newly acquired data;

[0091] Specifically, under the condition that satellite signals are continuously available, the second processing core (CPU1) performs periodic online adaptive updates of the model so that the frequency drift prediction model can track the long-term drift trend of the aging characteristics of the isothermal crystal oscillator. At the same time, the first processing core (CPU0) maintains the normal operation of the proportional-integral control discipline mode to ensure that the timekeeping process is not interrupted.

[0092] Specifically, step S3 includes the following process:

[0093] While satellite signals are available, the proportional-integral control discipline mode is maintained, and the online update process for the frequency drift prediction model is initiated.

[0094] Specifically, during periods when satellite signals are available, the first processing core continuously executes proportional-integral control (PIC) discipline mode, generating frequency control values ​​in real time and driving the temperature-controlled crystal oscillator. Simultaneously, the second processing core initiates an online update process, continuously receiving newly acquired data from the first processing core via shared memory. The second processing core allocates a circular buffer unit (e.g., set to 5MB) in its local memory, appending the received temperature data, timing information, and corresponding frequency control value data in timestamp order. The buffer unit employs a dual-pointer management mechanism; the write pointer automatically increments, wrapping back to the beginning when it reaches the end of the buffer, achieving rolling over storage.

[0095] The sample training set is continuously accumulated in the local cache unit;

[0096] Specifically, the second processing step monitors the amount of valid data in the cache unit during verification. When the accumulated data reaches the preset update window length (720 sampling points in this embodiment, corresponding to 1 hour of new data), the model update mechanism is automatically triggered. To avoid frequent updates leading to wasted computing resources, an update interval protection time is set (2 hours in this embodiment), meaning that at least 2 hours must be waited after the last model update before another update can be triggered. The triggering condition is implemented through a combination of hardware timer and data volume counter logic, ensuring precise and controllable update timing.

[0097] When the accumulated data reaches the preset update window length, the model update mechanism is automatically triggered, and the frequency drift prediction model is fine-tuned or locally updated using the newly added data.

[0098] Specifically, the second processing core loads the currently deployed frequency drift prediction model as the initial network and performs incremental training using the newly added data in the cache unit. This embodiment employs a transfer learning fine-tuning strategy: freezing the bottom feature extraction layer (the first 64 neurons) of the LSTM network and fine-tuning only the weight parameters of the top regression layer (the last 64 neurons) and the output layer. The fine-tuning process uses a small learning rate (set to 0.001 in this embodiment), a batch size of 16, and 30 training iterations, with the loss function remaining the mean squared error. This strategy retains the aging trend knowledge already learned by the model while quickly adapting to minor changes in crystal oscillator characteristics.

[0099] Specifically, the process of fine-tuning or locally updating the parameters of the frequency drift prediction model using new data includes:

[0100] After gradient calculation and parameter optimization are completed on the second processing core, pruning and quantization operations are performed on the updated frequency drift prediction model, and it is converted into a lightweight inference format.

[0101] Specifically, the weight matrix of the fully connected layers in the LSTM network is traversed, and weight connections with absolute values ​​less than a preset threshold (set to 0.01 in this embodiment) are marked as items to be pruned, while ensuring that each neuron retains at least 70% of its effective input connections. The pruning ratio is strictly controlled within 15% to avoid over-pruning that could lead to a loss of more than 1% in model accuracy. After pruning, the network connectivity is reconstructed, the marked connections are removed, and the weight storage matrix is ​​compressed.

[0102] The quantization operation randomly selects 100 samples from the local cache unit to form a calibration dataset, runs forward inference, and calculates the dynamic range (maximum and minimum values) of the activation values ​​of each layer. Based on this range, a quantization scaling factor is calculated, quantizing the 32-bit floating-point weight parameters into 8-bit integers, reducing the model size to 25% of the original. The second processing core generates a lightweight inference format file (.tflite) through the TensorFlowLite converter. This format contains the optimized computation graph, quantized weights, and metadata for online inference.

[0103] The optimized and compressed frequency drift prediction results are synchronously transmitted to the first processing core via shared memory.

[0104] Specifically, the second processing core allocates a dedicated model transmission area in shared memory, starting at address 0x4000_0000, with a size of 1MB. The second processing core divides the .tflite model file into 512-byte blocks and writes them to the transmission area using DMA. After each block is written, a "data valid" flag is set (address 0x4000_1000). The first processing core polls and reads the data block after detecting the flag. The first processing core prints the first and last 32-bit words of each received data block via serial port. The second processing core synchronously prints the corresponding values ​​from the sending end, and the two are compared manually or via script. If they do not match, the second processing core retransmits the data block; if they match, the first processing core writes 0x55AA to the "receive confirmation" address (0x4000_1004), and the second processing core confirms and continues sending the next block. The transmission timeout is set to 100ms, with a maximum of 3 retransmissions to ensure correct model data transmission.

[0105] At the start of the next control cycle, the first processing core reads the new frequency drift prediction results from the shared memory and performs frequency control, achieving seamless integration between the model update process and the real-time control task.

[0106] Specifically, at the start of the next control cycle (5 seconds), the first processing core loads the new model from local storage into the inference buffer and performs file integrity checks (version number and tensor dimensions). After successful verification, the current inference task is stopped, and the model pointer is atomically switched to the new model address, with the switching time less than 1ms. Subsequently, the first processing core reads real-time temperature data and timing information from shared memory, inputs it into the new model to perform forward inference, obtains the predicted value of the frequency control quantity, and assigns it to the digital-to-analog converter via a programmable logic device to perform frequency control, achieving seamless integration between model updates and real-time tasks.

[0107] After the model update is completed, the local cache unit is cleared, and the data collection and accumulation process is repeated to achieve periodic online adaptive learning.

[0108] Specifically, the second processing core clears the used data in its local cache unit, resets the write pointer to the beginning position, and resets the data volume counter. It then repeats the data acquisition and accumulation process to achieve a periodic online adaptive learning loop. After each update cycle, the second processing core records the model version number, update timestamp, and validation set error metric to the log storage area.

[0109] Step S4: When the satellite signal is interrupted, switch to the time-keeping prediction mode, and input the real-time collected temperature data and time sequence information into the frequency drift prediction model for prediction to obtain the frequency control quantity;

[0110] Specifically, step S4 includes the following process:

[0111] After the first processing core detects the satellite signal interruption trigger condition, it immediately disconnects the proportional-integral control discipline mode and starts the timekeeping forecast mode.

[0112] Specifically, the triggering conditions for entering the timekeeping forecast mode include:

[0113] Satellite signal strength is detected to be below a preset threshold or completely interrupted;

[0114] The frequency drift prediction model has completed its initial training and reached convergence.

[0115] Specifically, the first processing core monitors satellite signal quality in real time using the carrier-to-noise ratio (C / N0) reported every second by the GNSS receiver module. When the number of visible satellites is less than 3, or the average C / N0 of all satellites is below a preset threshold (35 dB-Hz in this embodiment) for 5 consecutive seconds, a satellite signal interruption is detected. Simultaneously, the first processing core queries the model status register to confirm that the frequency drift prediction model has completed initial training and that the root mean square error of the validation set is less than a preset convergence threshold (0.5 DAC units in this embodiment), ensuring the model has reliable predictive capabilities.

[0116] Once the above two conditions are met, the first processing core immediately executes a mode switching operation: it writes the mode flag 0x02 (time-predicting mode) to the system state machine, and simultaneously sends a mode disconnect command to the proportional-integral controller to stop the PI integral calculation and freeze the current integrator state value. The switching process is completed within one 1PPS cycle (1 second), ensuring a seamless transition of the control logic.

[0117] The first processing core stops outputting real-time calculated control quantities to the digital-to-analog converter, and simultaneously writes the real-time collected temperature data and timing information asynchronously into the shared memory.

[0118] Specifically, after the mode switch is completed, the first processing core stops outputting real-time calculated control quantities (DAC control words) to the digital-to-analog converter and instead starts the data acquisition task. At the beginning of each control cycle (5 seconds in this embodiment), the first processing core uses I... 2 The C bus reads the ambient temperature value from the temperature sensor (resolution 0.01℃, read time less than 10ms) and obtains the current timing information (including the cumulative number of seconds since the start of the timer) from the system clock. Then, the temperature data, timing information, and frequency control values ​​used in the previous cycle (as a historical reference) are packaged into a data frame with the following format: [32-bit timestamp][32-bit temperature value][32-bit DAC control word]. This data frame is asynchronously written to the shared memory inference data area via non-blocking DMA at address 0x3000_0000. The write operation takes less than 1ms and does not affect the real-time task scheduling of the first processing core.

[0119] The second processing core continuously monitors the shared memory status. When new data is detected being written, it reads it and inputs it into the frequency drift prediction model to perform forward inference calculations and generate the predicted value of the frequency control quantity at the current moment.

[0120] Specifically, after the first processing core completes the data writing, it atomically sets the flag to 1. Upon detecting that the flag is 1, the second processing core immediately reads the data frame content and clears the flag to zero after reading, notifying the first processing core that the data area can be written to again. The polling interval is set to 5ms to ensure that the data read latency is less than one control cycle. If no new data is detected after 10 consecutive polls (50ms), the second processing core triggers a watchdog timeout alarm and reports a "data synchronization failed" error to the system log.

[0121] Specifically, the process of the second processing core performing forward inference computation includes:

[0122] After reading the temperature data and time-series information from shared memory, they are format-converted and dimension-reconstructed to obtain a tensor structure.

[0123] Specifically, the 32-bit integer temperature data and time series information are converted to 32-bit floating-point data, and then reconstructed according to the model input requirements. Specifically, a single data point is expanded into a three-dimensional tensor structure of shape [1, 10, 2], where the first dimension is the batch size, the second dimension is the time step, and the third dimension is the feature dimension (temperature and time series). During reconstruction, data from the nine historical moments preceding the current moment are read from the local cache and concatenated with the current data to form a complete time series input. If historical data is insufficient (e.g., in the initial stage of the time-keeping forecast mode), zero-padding is used to supplement the data.

[0124] The tensor structure is used as input to the frequency drift prediction model for inference calculation to generate initial prediction results;

[0125] Specifically, the reconstructed tensor is input into a lightweight transformed TensorFlow Lite frequency drift prediction model, and the neural network acceleration unit (NPU) built into the second processing core or the SIMD instruction set is activated to perform parallel forward inference computation. The inference process includes state propagation of the LSTM layer (hidden state dimension 128), random deactivation of the dropout layer (disabled during inference), and output of the fully connected layer. After computation, the initial prediction result is obtained, which is a single floating-point value representing the predicted value of the DAC control word at the current time step.

[0126] Boundary value verification is performed on the initial prediction result. If the predicted value is detected to exceed the preset DAC control word range, an exception handling mechanism is triggered to perform forced truncation and record the exception event.

[0127] Specifically, the effective range of the DAC control word is set to [0, 1048576] (corresponding to the maximum value of a 32-bit unsigned integer). If the predicted value is less than 0, it is forcibly truncated to 0 and an anomaly is recorded; if the predicted value is greater than 1048576, it is forcibly truncated to 1048576 and an anomaly is recorded. The anomaly record is written to the log area of ​​the memory, containing a timestamp, the value before truncation, the value after truncation, and temperature information, for offline analysis.

[0128] The verified frequency control prediction values ​​are formatted and then written back to shared memory.

[0129] Specifically, the verified frequency control prediction value is quantized and mapped to a 32-bit unsigned integer format (range 0~1048576, corresponding to the DAC full scale), and packaged into an inference result frame: [32-bit timestamp][32-bit valid prediction value]. This result frame is written to the inference result area of ​​shared memory (address 0x3000_2000), and after completion, the "result ready" flag (address 0x3000_3000) is set to notify the first processing core to read it.

[0130] The second processing core writes the predicted value back to the shared memory. The first processing core reads the predicted value and assigns it to the digital-to-analog converter module through a programmable logic device to generate a corresponding voltage-controlled voltage to compensate the frequency of the temperature-controlled crystal oscillator.

[0131] Specifically, after the first processing core detects the "result ready" flag is set, it reads the prediction result frame from shared memory and extracts the 32-bit frequency control prediction value. This value is then written to the input register of the digital-to-analog converter (DAC) module via the FPGA's internal bus (e.g., AXI4-Lite). The write operation is implemented using combinational logic to ensure completion within 1 microsecond. The DAC converts the digital control value into a 0-5V analog voltage-controlled voltage, which is output to the voltage-controlled input of the temperature-controlled crystal oscillator, completing the frequency compensation closed loop. The entire process, from data acquisition to voltage output delay, is controlled within 10ms, meeting real-time requirements.

[0132] Step S5: Generate a voltage-controlled voltage according to the frequency control quantity, perform frequency compensation on the temperature-controlled crystal oscillator, and maintain the timekeeping accuracy of the local time reference.

[0133] Specifically, step S5 includes the following process:

[0134] The first processing core reads the predicted value of the frequency control quantity from the shared memory, converts the predicted value into a digital control signal through a programmable logic device, and assigns it to the digital-to-analog converter.

[0135] Specifically, the first processing core reads the 32-bit frequency control prediction value from the inference result area of ​​shared memory. This prediction value is stored in 32-bit unsigned integer format, with a value range of 0~1048576, corresponding to the full-scale input of the digital-to-analog converter (DAC). The first processing core writes the prediction value to the input register of the DAC module via the FPGA's internal AXI4-Lite bus interface, triggered by the rising edge of a 1PPS pulse signal. The write operation uses combinational logic decoding, with a bus clock frequency of 10MHz, ensuring that the register write delay is less than 10 clock cycles (100ns). To prevent data races, the first processing core checks the "busy" status bit of the DAC module before writing; if the status bit is 1, it waits 50μs and retryes, ensuring that the DAC conversion is complete before updating the new value.

[0136] The digital-to-analog converter converts the digital control signal into an analog voltage-controlled voltage, which is then applied to the voltage-controlled input terminal of the temperature-controlled crystal oscillator.

[0137] Specifically, the digital-to-analog converter (DAC) employs a high-precision 16-bit resolution DAC chip, supporting SPI interface and parallel input mode. The FPGA's built-in DAC controller converts the digital control signals written by the first processing core into analog voltages, with a typical output settling time of 5μs. The DAC reference voltage source uses an external 5V precision reference source (such as DP832).

[0138] The temperature-controlled crystal oscillator adjusts its internal oscillation frequency according to the voltage-controlled voltage to obtain a frequency output signal;

[0139] Specifically, the temperature-controlled crystal oscillator uses a high-precision SC-cut OCXO, with a frequency stability better than ±5×10⁻⁶. -10 / day, voltage-controlled tuning range ±10×10 -6 The voltage-controlled voltage sensitivity is approximately 2×10⁻⁶. -6 / V. When the voltage control voltage When applied to the crystal oscillator tuning terminal, the capacitance value of the varactor diode inside the crystal oscillator changes accordingly, causing the resonant frequency of the oscillation circuit to shift.

[0140] The programmable logic device generates a local second pulse signal based on the frequency output signal and maintains phase continuity through a phase-locked loop mechanism;

[0141] Specifically, the process by which the programmable logic device generates a local second pulse signal based on the frequency output signal and maintains phase continuity through a phase-locked loop mechanism includes:

[0142] The programmable logic device has a built-in digital phase-locked loop module to perform frequency multiplication on the frequency output signal to obtain a high-frequency reference clock;

[0143] Specifically, the programmable logic device (FPGA) incorporates a digital phase-locked loop (DPLL) module to multiply the input 10MHz frequency output signal. The DPLL employs a fully digital architecture, consisting of a phase detector, loop filter, and digitally controlled oscillator. The multiplication factor is set to 500 to generate a 5GHz high-frequency reference clock. The high-frequency clock is divided to generate a 10MHz system operating clock, which also serves as the time base for second pulse generation. The DPLL loop bandwidth is set to 1kHz, the lockout time is less than 1ms, and the phase jitter after locking is less than 10ps RMS.

[0144] Periodic counting is performed based on the high-frequency reference clock, and a second pulse edge signal is generated when the count value reaches a preset threshold.

[0145] Specifically, based on a high-frequency reference clock The FPGA internally implements a 40-bit periodic counter. After the initial value of the counter is cleared to zero, each... The rising edge triggers the counter to increment by 1. The counter increments by 1 when the count reaches a preset threshold. At that time, a second pulse edge signal is generated. The threshold calculation formula is:

[0146]

[0147] in, =1Hz is the target pulse frequency per second. To dynamically adjust the amount, under ideal conditions, =5×10 9 -1. The counter automatically resets after overflowing and begins counting for the next second, thus generating a local 1PPS signal with a period of 1 second.

[0148] At the instant of switching the timekeeping forecast mode, the digital phase-locked loop module captures the current phase error and starts the phase smooth transition mechanism, and suppresses phase jump by finely adjusting the counting threshold value cycle by cycle.

[0149] Specifically, at the instant of switching from PI discipline mode to timekeeping forecast mode, the digital phase-locked loop module captures the current phase error. This refers to the time difference between the local 1PPS rising edge and the previous GNSS reference 1PPS rising edge, with a capture accuracy of 16.67ns. To avoid phase jumps caused by switching, a phase smoothing transition mechanism is activated: the DPLL fine-tunes the counting threshold value cycle by cycle within 10 seconds after the switch. The adjustment amount per cycle is This gradually brings the phase error to zero. The adjustment process uses a PI control algorithm:

[0150]

[0151] in, To ensure the smoothing coefficient and guarantee monotonically convergent transition process, the phase jump is suppressed to within 5ns.

[0152] During satellite signal interruption, the accumulated phase drift is continuously monitored. When the accumulated amount exceeds the compensation limit, the digital phase-locked loop module is triggered to perform a one-time phase correction operation to ensure the long-term phase continuity of the local second pulse signal.

[0153] Specifically, during the satellite signal interruption, the first processing core continuously monitors the cumulative phase drift. Its calculation method is the sum of the differences between the actual counting period and the theoretical period. When When the compensation limit is exceeded (set to ±50ns in this embodiment), the DPLL is triggered to perform a one-time phase correction operation: forcibly compensating the current value of the counter. This ensures that the phase of the local 1PPS signal returns to the center position, guaranteeing long-term phase continuity. The correction operation frequency does not exceed 0.1Hz to avoid introducing additional frequency disturbances.

[0154] The first processing core continuously monitors the stability of the frequency output signal and the local second pulse signal to ensure long-term timekeeping accuracy of the time reference during satellite signal interruptions.

[0155] Specifically, the first processing core continuously monitors the frequency stability of the output signal (calculated using Allan variance, with a sampling interval of 1 second and 100 sampling times) and the period jitter of the local second pulse signal (measured using a time interval counter, with a resolution of 1 ns) through the FPGA's internal monitoring module. The monitoring data is stored in a circular buffer. When the Allan variance is greater than 1 × 10⁻⁶, the buffer will close. -9 If the period jitter exceeds 20ns, a "timekeeping performance degradation" alarm is triggered. In the alarm state, the system automatically shortens the model update cycle (from 2 hours to 30 minutes) and increases the DAC output refresh frequency (from 5 seconds to 2 seconds) to enhance the tracking capability of crystal oscillator drift and ensure that the timekeeping accuracy is better than ±50ns during a 30-day satellite signal interruption.

[0156] Specifically, the present invention also provides a timekeeping system for a temperature-controlled crystal oscillator based on an LSTM neural network, comprising:

[0157] The data acquisition module is used to collect clock difference data, ambient temperature data, timing information and frequency control data of the isothermal crystal oscillator in real time and preprocess them to obtain a training sample set.

[0158] The model training module, connected to the data acquisition module, is used to construct a long short-term memory neural network model by using the environmental temperature data and time series information collected at historical moments as input features and the filtered frequency control data as the prediction target, and to train the model based on the training sample set to obtain a frequency drift prediction model.

[0159] An online update module, connected to the model training module, is used to continuously update the frequency drift prediction model online using newly acquired data when satellite signals are available.

[0160] The time-keeping forecast module, connected to the online update module, is used to switch to the time-keeping forecast mode when the satellite signal is interrupted, and input the real-time collected temperature data and time sequence information into the frequency drift prediction model for prediction to obtain the frequency control quantity;

[0161] The frequency compensation module, connected to the timekeeping prediction module, is used to generate a voltage-controlled voltage based on the frequency control quantity to perform frequency compensation on the temperature-controlled crystal oscillator and maintain the timekeeping accuracy of the local time reference.

[0162] Specifically, the LSTM neural network-based timekeeping method for isothermal crystal oscillators provided by this invention can execute the LSTM neural network-based timekeeping system for isothermal crystal oscillators in the embodiments of this invention and can achieve the same technical effect, which will not be elaborated here.

[0163] Specifically, this invention utilizes an LSTM neural network to deeply mine the nonlinear time-varying coupling relationship between temperature and crystal oscillator aging. Leveraging its gating mechanism, it adaptively learns the multidimensional time-series mapping patterns of historical clock bias, ambient temperature, and frequency control variables. The constructed frequency drift prediction model can detect OCXO frequency shift trends in advance under satellite-denied environments. The dual-core collaborative architecture decouples model training and inference from real-time docile control, enabling the embedded system to efficiently execute complex deep learning algorithms even under resource-constrained conditions, while ensuring the determinism and real-time performance of the control loop. The online update mechanism incrementally updates the model by continuously accumulating newly acquired data. Fine-tuning allows it to dynamically track the long-term evolution of crystal oscillator aging characteristics, avoiding the problem of fixed-parameter models failing over time. When switching timekeeping prediction modes, the digital phase-locked loop captures phase errors and smoothly corrects them cycle by cycle, effectively suppressing phase jumps caused by mode switching. Combined with the voltage-controlled voltage generated by the frequency control quantity predicted by the model, it accurately compensates the OCXO, ensuring that the local second pulse signal remains continuous and stable during satellite outages. This invention utilizes the inherent correlation between LSTM prediction, voltage compensation, and phase locking to achieve nanosecond-level long-term timekeeping accuracy under satellite rejection conditions, which is significantly better than traditional polynomial fitting or Kalman filtering methods.

[0164] The technical solution of the present invention has been described above with reference to the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of the present invention is obviously not limited to these specific embodiments. Without departing from the principles of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of the present invention.

[0165] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A time-keeping method for a isothermal crystal oscillator based on an LSTM neural network, characterized in that, include: Step S1: Real-time acquisition of clock difference data, ambient temperature data, timing information and frequency control data of the isothermal crystal oscillator, and preprocessing to obtain a training sample set; Step S2: Using the ambient temperature data and time series information collected at historical moments as input features, and the filtered frequency control data as the prediction target, a long short-term memory neural network model is constructed, and the frequency drift prediction model is obtained by training the model based on the training sample set. Step S3: When satellite signals are available, continuously update the frequency drift prediction model online using newly acquired data; The process of step S3 includes: While satellite signals are available, the proportional-integral control discipline mode is maintained, and the online update process for the frequency drift prediction model is initiated. The training sample set is continuously accumulated in the local cache unit; When the accumulated data reaches the preset update window length, the model update mechanism is automatically triggered, and the frequency drift prediction model is fine-tuned or locally updated using the newly added data. After the model update is completed, the local cache unit is cleared, and the data collection and accumulation process is repeated to achieve periodic online adaptive learning. The process of fine-tuning or locally updating the parameters of the frequency drift prediction model using new data includes: After gradient calculation and parameter optimization are completed on the second processing core, pruning and quantization operations are performed on the updated frequency drift prediction model, and it is converted into a lightweight inference format. The optimized and compressed frequency drift prediction results are synchronously transmitted to the first processing core via shared memory. At the start of the next control cycle, the first processing core reads the new frequency drift prediction results from the shared memory and executes frequency control, achieving seamless integration between the model update process and the real-time control task. Step S4: When the satellite signal is interrupted, switch to the time-keeping prediction mode, and input the real-time collected temperature data and time sequence information into the frequency drift prediction model for prediction to obtain the frequency control quantity; Step S5: Generate a voltage-controlled voltage according to the frequency control quantity, perform frequency compensation on the temperature-controlled crystal oscillator, and maintain the timekeeping accuracy of the local time reference.

2. The method for maintaining the time of a isothermal crystal oscillator based on an LSTM neural network according to claim 1, characterized in that, The process of step S2 includes: Once the accumulated data reaches the preset window length, the model training process is automatically triggered to construct a single-layer long short-term memory network structure and configure a preset number of hidden layer neurons. The ambient temperature data and time series information collected at historical moments are used as multi-dimensional input feature vectors, and the frequency control data after filtering and smoothing are used as the target output of supervised learning. An adaptive moment estimation optimizer is used with an adjustable initial learning rate, and the learning rate is dynamically and exponentially decayed during training based on the performance on the validation set. The model parameters are optimized by a preset number of training iterations, and the mean square error function is used to measure the deviation between the predicted value and the true value to obtain the frequency drift prediction model.

3. The isothermal crystal oscillator timekeeping method based on LSTM neural network according to claim 2, characterized in that, The process of dynamically and exponentially decaying the learning rate based on the validation set performance during training includes: After each training iteration, the current batch of data is divided into a training subset and a validation subset. The model parameters are updated using the training subset, and the prediction error index is calculated synchronously on the validation subset. At the end of each epoch, exponential decay is automatically performed, and the current learning rate is exponentially reduced according to the preset decay coefficient. After the reduction, the learning rate is reconfigured into the optimizer. Continue the iterative training process until all training cycles are completed or the learning rate decays to the preset minimum threshold.

4. The method for maintaining the time of a isothermal crystal oscillator based on an LSTM neural network according to claim 1, characterized in that, The process of step S4 includes: After the first processing core detects the satellite signal interruption trigger condition, it immediately disconnects the proportional-integral control discipline mode and starts the timekeeping forecast mode. The first processing core stops outputting real-time calculated control quantities to the digital-to-analog converter, and simultaneously writes the real-time collected temperature data and timing information asynchronously into the shared memory. The second processing core continuously monitors the shared memory status. When new data is detected being written, it reads it and inputs it into the frequency drift prediction model to perform forward inference calculations and generate the predicted value of the frequency control quantity at the current moment. The second processing core writes the predicted value back to the shared memory. The first processing core reads the predicted value and assigns it to the digital-to-analog converter module through a programmable logic device to generate a corresponding voltage-controlled voltage to compensate the frequency of the temperature-controlled crystal oscillator.

5. The isothermal crystal oscillator timekeeping method based on LSTM neural network according to claim 4, characterized in that, The process of the second processing core performing forward inference computation includes: After reading the temperature data and time-series information from shared memory, they are formatted and reconstructed to obtain a tensor structure. The tensor structure is used as input to the frequency drift prediction model for inference calculation to generate initial prediction results; Boundary value verification is performed on the initial prediction result. If the predicted value is detected to exceed the preset DAC control word range, an exception handling mechanism is triggered to perform forced truncation and record the exception event. The calibrated frequency control quantity prediction value is converted into a new format and then written back to shared memory.

6. The method for maintaining the time of a isothermal crystal oscillator based on an LSTM neural network according to claim 5, characterized in that, The triggering conditions for activating the timed forecast mode include: Satellite signal strength is detected to be below a preset threshold or completely interrupted; The frequency drift prediction model has completed its initial training and reached convergence.

7. The method for maintaining the time of a isothermal crystal oscillator based on an LSTM neural network according to claim 6, characterized in that, The process of step S5 includes: The first processing core reads the predicted value of the frequency control quantity from the shared memory, converts the predicted value into a digital control signal through a programmable logic device, and assigns it to the digital-to-analog converter. The digital-to-analog converter converts the digital control signal into an analog voltage-controlled voltage, which is then applied to the voltage-controlled input terminal of the temperature-controlled crystal oscillator. The temperature-controlled crystal oscillator adjusts its internal oscillation frequency according to the voltage-controlled voltage to obtain a frequency output signal; The programmable logic device generates a local second pulse signal based on the frequency output signal and maintains phase continuity through a phase-locked loop mechanism; The first processing core continuously monitors the stability of the frequency output signal and the local second pulse signal to ensure long-term timekeeping accuracy of the time reference during satellite signal interruptions.

8. A isothermal crystal oscillator timing system based on an LSTM neural network, according to any one of claims 1-7, characterized in that, include: The data acquisition module is used to collect clock difference data, ambient temperature data, timing information and frequency control data of the isothermal crystal oscillator in real time and preprocess them to obtain a training sample set. The model training module, connected to the data acquisition module, is used to construct a long short-term memory neural network model by using the environmental temperature data and time series information collected at historical moments as input features and the filtered frequency control data as the prediction target, and to train the model based on the training sample set to obtain a frequency drift prediction model. An online update module, connected to the model training module, is used to continuously update the frequency drift prediction model online using newly acquired data when satellite signals are available. The time-keeping forecast module, connected to the online update module, is used to switch to the time-keeping forecast mode when the satellite signal is interrupted, and input the real-time collected temperature data and time sequence information into the frequency drift prediction model for prediction to obtain the frequency control quantity; The frequency compensation module, connected to the timekeeping prediction module, is used to generate a voltage-controlled voltage based on the frequency control quantity to perform frequency compensation on the temperature-controlled crystal oscillator and maintain the timekeeping accuracy of the local time reference.

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