A multi-time scale parallel interactive simulation method and system suitable for adaptive commutation converter

Abstract

This invention proposes a multi-timescale parallel interactive simulation method and system suitable for adaptive commutator converters. Addressing the problem that traditional single-simulation-step-size simulations struggle to balance real-time performance and accuracy due to the dynamic multi-timescale operation of adaptive commutator converters, this invention constructs a CPU-FPGA heterogeneous simulation architecture: the rectifier-side model, DC-side model, inverter-side model, LCC model, and control system model are deployed on the CPU side, while the SVG model is deployed on the FPGA side. To solve the strong coupling problem caused by the interaction of different timescales, a multi-rate decoupling algorithm is adopted. Based on the inductor discretization model, the strongly coupled branch is decomposed into two Thevenin equivalent sub-circuits at the interface, which can be independently calculated using historical electrical quantity data. This effectively realizes the parallel interactive calculation of fast and slow timescale models, overcomes the accuracy bottleneck caused by the difference in simulation step size, and achieves efficient and high-precision real-time simulation of the adaptive commutator converter system under all operating conditions.

Description

Technical Field

[0001] This invention belongs to the field of electromagnetic transient simulation technology of high voltage direct current transmission systems, and relates to a multi-timescale parallel interactive simulation method and system suitable for adaptive commutation converters. Specifically, it relates to a simulation model, simulation method and system suitable for adaptive commutation converters. Background Technology

[0002] With the rapid development of high-proportion grid integration of new energy power generation and AC / DC hybrid power grids, the dynamic characteristics of power systems are becoming increasingly complex, placing higher demands on the accuracy and efficiency of simulation technology. Against this backdrop, novel converter technologies, such as self-commutated converters (SLCCs) employing fully controlled power electronic devices, have become an important direction for upgrading high-voltage direct current (HVDC) transmission technology. Self-commutated converters include line-commutated converters (LCCs) and static var generators (SVGs). The SVG, as a reactive power and harmonic compensation component, is coupled with the LCC, leading to engineering challenges such as reactive power compensation, harmonic suppression, and transient fault response.

[0003] Currently, electromagnetic transient simulation of power systems is mainly based on a pure central processing unit (CPU) architecture. However, when facing the simulation requirements of high-frequency dynamic processes of SVG in SLCC systems (such as microsecond-level control cycles), existing technologies have significant shortcomings: First, the serial computing mode of the CPU cannot meet the real-time requirements, resulting in the simulation speed being unable to keep up with the dynamic response of the actual system; second, the simulation accuracy is difficult to match the stringent requirements of engineering applications for harmonic analysis and transient characteristic research; third, dedicated simulation models for new topologies such as SLCC are not yet mature and cannot accurately support the optimization of their control and protection strategies and the in-depth analysis of fault characteristics.

[0004] Therefore, there is an urgent need in this field to develop an innovative simulation solution that can effectively adapt to new switching technologies such as SLCC, significantly improving simulation efficiency while ensuring simulation accuracy. This invention introduces a field-programmable gate array (FPGA) as the hardware acceleration core, constructing a CPU+FPGA heterogeneous computing architecture and combining it with a multi-rate decoupling algorithm. Leveraging its hardware parallel computing capabilities and programmability, the FPGA can provide real-time simulation with microsecond-level accuracy for the high-frequency dynamic processes of SVG, effectively compensating for the shortcomings of pure CPU architectures in terms of real-time performance and accuracy. Summary of the Invention

[0005] In view of this, in order to solve the problems of insufficient real-time performance of existing pure CPU simulation in SVG high-frequency control, poor adaptability to new SLCC topologies, and difficulty in matching the accuracy of fault transient simulation to engineering requirements, this invention provides a multi-timescale parallel interactive simulation method and system suitable for adaptive commutation converters. It aims to achieve efficient and high-precision simulation of SLCC system under all operating conditions, and provide accurate and efficient simulation support for SLCC system control and protection strategy optimization and fault characteristic analysis.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] Adaptive commutation converters include grid commutation converters (LCCs) and static var generators (SVGs).

[0008] A multi-timescale parallel interactive simulation method for adaptive commutation converters includes:

[0009] A CPU+FPGA heterogeneous computing architecture is constructed, in which the adaptive commutator simulation model is divided into a CPU-side simulator and an FPGA-side simulator according to the dynamic response characteristics of the components; the simulation step size of the CPU-side simulator is larger than that of the FPGA-side simulator; the components deployed in the CPU-side simulator include the rectifier side model, DC side model, inverter side model, LCC model, LCC rectifier side control system, LCC inverter side control system, and SVG control system; the components deployed in the FPGA-side simulator include the SVG model.

[0010] A multi-rate decoupling algorithm is used to decouple the connection branches between the components deployed on the CPU side and the components deployed on the FPGA side. The multi-rate decoupling algorithm is based on the inductor discretization model and decomposes the connection branch into two Thevenin equivalent sub-circuits that are independently calculated through historical terms. This allows the CPU-side and FPGA-side simulators to perform independent calculations based on their respective optimal simulation step sizes. Boundary data is exchanged through a communication interface, and the models and control systems deployed on the CPU side and FPGA side are updated in parallel based on the calculation results of the Thevenin equivalent sub-circuits.

[0011] Furthermore, the multi-rate decoupling algorithm based on the inductor discretization model specifically includes:

[0012] The inductance continuous model shown in equation (1) is discretized using the trapezoidal integral rule:

[0013]

[0014] Among them, u k (t) and u m (t) represents the instantaneous voltage at the node, i L(t) represents the branch current; to ensure high numerical fidelity of the linear passive network, the trapezoidal integration rule is adopted; for equation (1) at the time step Integrating within the inner quadrat, we get:

[0015]

[0016] Let the equivalent characteristic resistance be defined as To simplify the symbols, use the superscript "; " indicates the previous time step ( The value of ) is given by substituting the above definition into equation (3) and rearranging the terms to express the inductor voltage. Furthermore, the Thevenin equivalent model is obtained:

[0017]

[0018] Equation (3) shows that the voltage drop depends on the instantaneous current and the historical state; to achieve a decoupling interface, equation (4) is further expanded into a symmetrical form:

[0019]

[0020] Equation (4) clarifies the core principle of the inductor discretization method; by using delay elements and controlled voltage sources, the inductor model can be conveniently divided into two symmetrical sub-circuits; this mathematical structure enables the global system matrix to be decoupled at the inductor port.

[0021] Furthermore, the maximum relative amplitude error of the multi-rate decoupling algorithm does not exceed 3.3% in the frequency range of 0~5000Hz, and the CPU-side time step used for discretization is 20μs.

[0022] A simulation system for implementing the above-mentioned multi-timescale parallel interactive simulation method includes:

[0023] The CPU-side simulator is configured to perform simulation calculations for the CPU-side components.

[0024] An FPGA-side simulator is configured to perform simulation calculations for the components on the FPGA side.

[0025] A high-speed communication module connects the emulator on the FPGA side and the emulator on the CPU side, and is configured to enable data interaction between the two sides.

[0026] Furthermore, the CPU-side simulator deploys rectifier-side models, DC-side models, inverter-side models, LCC models, LCC rectifier-side control systems, LCC inverter-side control systems, and SVG control systems; the FPGA-side simulator deploys SVG models.

[0027] Furthermore, the high-speed communication module uses an optical fiber communication interface to transmit critical electrical quantities such as commutation voltage and DC current, thereby reducing communication delay and electromagnetic interference.

[0028] A simulation model for implementing the above-mentioned multi-timescale parallel interactive simulation method is based on the coordinated operation of an LCC model and an SVG model. It includes a simulator deployed on the CPU side, a simulator deployed on the FPGA side, and a communication interface connecting the CPU-side and FPGA-side simulators. The CPU-side simulator includes a rectifier-side model, a DC-side model, an inverter-side model, an LCC model, an LCC rectifier-side control system, an LCC inverter-side control system, and an SVG control system. The FPGA-side simulator includes an SVG model. The simulation step size of the CPU-side simulator is larger than that of the FPGA-side simulator.

[0029] The rectifier-side model, DC-side model, and inverter-side model are connected sequentially. The LCC model is connected to the rectifier-side model and the inverter-side model, and the SVG model is connected to the rectifier-side model. The rectifier-side model is used to convert AC to DC and provide electrical quantities. The DC-side model is used to transmit DC electrical quantities. The inverter-side model is used to convert DC to AC and provide electrical quantities. The LCC model and SVG model are used to output electrical quantities and update them according to the corresponding control commands. Electrical quantities are interacted at the connection branches to complete one simulation cycle of the simulation system. Among them, the LCC rectifier-side control system is connected to the rectifier-side model, the LCC inverter-side control system is connected to the inverter-side model, the LCC rectifier-side control system and the LCC inverter-side control system are connected to the LCC model, and the SVG control system is connected to the SVG model.

[0030] A computer device includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the above-mentioned multi-timescale parallel interactive simulation method.

[0031] A computer-readable storage medium storing a computer program, which, when executed by a processor, implements the aforementioned multi-timescale parallel interactive simulation method.

[0032] A multi-timescale parallel interactive simulation method suitable for adaptive commutation converters is applied to the simulation verification of new power electronic topologies and is applicable to various laboratory environments.

[0033] The beneficial effects of this invention are as follows:

[0034] 1. The CPU+FPGA heterogeneous computing architecture and multi-rate decoupling algorithm used in the multi-timescale parallel interactive simulation method for adaptive commutated converters disclosed in this invention are closely linked through functional partitioning and data interaction timing. Specifically, this architecture decouples the simulation tasks based on the differences in the dynamic response characteristics of each component in the SLCC system: the rectifier-side model, DC-side model, inverter-side model, LCC model, LCC rectifier-side control system, LCC inverter-side control system, and SVG control system are deployed on the CPU side; the SVG model is deployed on the FPGA side. The multi-rate decoupling algorithm (based on the inductor discretization model) provides the mathematical basis for asynchronous parallel computing on both sides. By introducing equivalent resistance and historical terms, it decouples strongly coupled physical branches (such as the SVG output inductor) at the interface, allowing independent calculations based on their respective optimal simulation step sizes. Boundary data (such as voltage and current) are exchanged according to a specific timing sequence through high-speed communication (such as optical fiber), thereby significantly improving the overall simulation efficiency while ensuring simulation accuracy and solving the bottleneck problem of insufficient real-time performance in traditional pure CPU simulation during SVG high-frequency control.

[0035] 2. The multi-timescale parallel interactive simulation method for adaptive commutated converters disclosed in this invention utilizes a core multi-rate decoupling algorithm based on an inductor discretization model. This algorithm decomposes strongly coupled physical branches (such as the SVG outlet inductor) at the interface into two Thevenin equivalent sub-circuits that can be independently calculated using historical terms through the trapezoidal integral method. This mathematical innovation achieves effective decoupling of the system at the interface, laying a theoretical foundation for asynchronous parallel computing between the CPU and FPGA. Frequency response analysis demonstrates that the algorithm's maximum relative amplitude error does not exceed 3.3% in the 0–5000Hz range, ensuring high fidelity of the simulation results and accurately matching the stringent requirements of engineering applications for harmonic analysis and transient characteristic research.

[0036] 3. The multi-timescale parallel interactive simulation method for adaptive commutated converters disclosed in this invention demonstrates significant engineering practical value. Hardware-in-the-loop platform verification shows that the SLCC system model built based on this simulation method can accurately capture its advantages over traditional LCC systems in dynamic response and fault ride-through capabilities, such as faster DC voltage and current recovery speeds and the dynamic process of rapid reactive power support from SVG. This proves that this simulation platform is not only an effective tool for studying the novel SLCC topology, but also provides accurate and efficient simulation support for the optimization of control and protection strategies and fault characteristic analysis in practical power engineering, showing significant potential for widespread application.

[0037] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0038] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0039] Figure 1 This is a diagram illustrating the overall architecture of the multi-timescale parallel interactive real-time simulation system applicable to adaptive commutation converters according to the present invention.

[0040] Figure 2 This is a multi-rate real-time simulation structure diagram of the present invention based on CPU+FPGA heterogeneous control architecture and hierarchical collaborative control strategy.

[0041] Figure 3 This is a schematic diagram illustrating the principle of inductor discretization analysis in this invention.

[0042] Figure 4 This is a schematic diagram of the multi-rate decoupling algorithm of the present invention;

[0043] Figure 5 This is a comparison diagram of the frequency characteristics between the discretized inductance model of this invention and the continuous domain theoretical benchmark model; wherein... Figure 5 (a) is the amplitude-frequency response diagram. Figure 5 (b) is the phase frequency response diagram. Figure 5 (c) is the relative error plot;

[0044] Figure 6 This is a schematic diagram of the real-time simulation process of the present invention;

[0045] Figure 7 This is a comparison diagram of DC fault waveforms under the SLCC and LCC models of this invention; wherein, Figure 7 (a) is a comparison of DC voltage during faults for the SLCC and LCC models. Figure 7 (b) Comparison of AC reactive power during faults for SLCC and LCC models;

[0046] Figure 8 shows the engineering implementation architecture of a multi-timescale parallel interactive simulation system based on the RT-LAB simulation platform; where... Figure 8 (a) is a flowchart illustrating the deployment logic and real-time operation of the decoupling algorithm on the CPU model. Figure 8 (b) Data interaction diagram between CPU and FPGA Figure 8 (c) is a flowchart of the decoupling algorithm deployment logic and real-time operation on the FPGA model. Detailed Implementation

[0047] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0048] SLCC stands for Adaptive Commutation Converter. It is an advanced converter that uses fully controllable devices such as Insulated Gate Bipolar Transistors (IGBTs). Unlike traditional converters that rely on grid voltage for commutation, SLCCs can control the current turn-off independently and have the ability to independently adjust active and reactive power, making them a core component in building flexible DC transmission systems.

[0049] SVG stands for Static Var Generator. It is a power electronic device used for dynamic reactive power compensation. "Direct connection" means that the SVG device is directly connected to the high-voltage bus of the power grid without going through a transformer. This method reduces losses and delays in intermediate links, enabling faster response to system demands and maintaining voltage stability, but it places higher demands on the insulation and performance of the device itself. In a SLCC system, the direct-connected SVG is responsible for rapidly providing or absorbing reactive power.

[0050] FPGA stands for Field Programmable Gate Array. It is a semi-custom integrated circuit chip whose key feature is that its logic functions can be defined and reconfigured by the user through programming after manufacturing. In the field of simulation, FPGAs are well-suited for real-time simulation of power electronic systems and other applications requiring extremely high computational speed and determinism due to their high parallel processing capabilities.

[0051] like Figure 1 The diagram shown illustrates the overall architecture of a multi-timescale parallel interactive real-time simulation system for adaptive commutation converters, including:

[0052] S1. Functional partitioning based on CPU+FPGA heterogeneous computing architecture; accurate and efficient co-simulation is achieved by modeling the CPU and FPGA heterogeneous architectures separately, as detailed below:

[0053] S11. FPGA-side modeling focuses on high-precision, high-frequency components, with a key emphasis on constructing the SVG topology and its DC-side circuitry. Given that the SVG is the core of the SLCC system's reactive power and harmonic self-compensation, processes such as decoupling control and harmonic compensation require high-frequency dynamic response. The FPGA's parallel computing capabilities can meet the microsecond-level data processing requirements, ensuring the simulation accuracy of key aspects such as harmonic extraction and reactive power regulation.

[0054] S12. Deploy the rectifier-side model, DC-side model, inverter-side model, LCC model, LCC rectifier-side control system, LCC inverter-side control system, and SVG control system on the CPU side; the simulation step size on the CPU side is larger than the simulation step size on the FPGA side. Integrate and deploy the control system on the CPU side (e.g., Figure 2 As shown in the figure, to execute the corresponding control logic and optimize the allocation of simulation resources;

[0055] S13. To address the simulation accuracy issue in asynchronous communication scenarios, this architecture employs fiber optic communication to achieve data interaction between the CPU and the FPGA. This method minimizes communication latency, resists electromagnetic interference, ensures the timeliness of data synchronization for key electrical quantities such as commutation voltage and DC current, and avoids simulation distortion caused by communication bottlenecks.

[0056] Through the collaborative design of component decomposition, heterogeneous modeling, and high-speed communication, a heterogeneous multi-rate real-time simulation platform was constructed, providing stable and reliable infrastructure support for subsequent SLCC system control strategy verification and fault transient characteristic analysis.

[0057] S2. Data timing interaction based on multi-rate decoupling algorithm; Decoupling of strongly coupled physical branches in SLCC system through multi-rate decoupling algorithm;

[0058] With the rapid development of DC power grids and the widespread application of large-scale power systems, network decoupling has gradually become one of the important means to improve the efficiency of real-time simulation of DC power grids. Its basic principle is to select transmission lines and inductors as network decoupling nodes to realize the division of the system and calculate the amount of interactive information. However, since the characteristic frequencies of the circuits on both sides of the network in the system to be decoupled are not necessarily the same, the appropriate simulation step size is not equal.

[0059] Furthermore, LCCs and AC power grids do not exhibit rapid switching state transitions, classifying them as slow-dynamic systems suitable for CPU logic scheduling and low-to-medium frequency computing capabilities; therefore, they are modeled within the CPU. In contrast, the direct-connected SVG controller, as a core component of the SLCC system's reactive power self-compensation and harmonic self-compensation, exhibits high dynamic response frequencies in its dq decoupling control and PR harmonic compensation processes, requiring high-frequency parallel computing support; therefore, it is modeled within the FPGA. Simultaneously, the SVG output inductor (e.g., Figure 2 L a,b,c It can serve as a key processing object for the network decoupling algorithm, providing hardware-level adaptation support for the decoupling operation of strongly coupled branches in the SLCC system.

[0060] like Figure 2As shown, from an architectural perspective, the emulator on the CPU side runs the CPU model; the emulator on the FPGA side runs the FPGA model; the CPU model and the FPGA model are connected via fiber optic communication and interact with each other.

[0061] The CPU model includes the rectifier-side model, DC-side model, inverter-side model, LCC model, LCC rectifier-side control system, LCC inverter-side control system, and SVG control system; the FPGA model includes the SVG model.

[0062] The rectifier-side model, DC-side model, and inverter-side model are connected sequentially. The LCC model is connected to the rectifier-side model and the inverter-side model, and the SVG model is connected to the rectifier-side model. The rectifier-side model is used to convert AC to DC and provide electrical quantities. The DC-side model is used to transmit DC electrical quantities. The inverter-side model is used to convert DC to AC and provide electrical quantities. The LCC model and SVG model are used to output electrical quantities and update them according to the corresponding control commands. Electrical quantities are interacted at the connection branches to complete one simulation cycle of the simulation system. Among them, the LCC rectifier-side control system is connected to the rectifier-side model, the LCC inverter-side control system is connected to the inverter-side model, the LCC rectifier-side control system and the LCC inverter-side control system are connected to the LCC model, and the SVG control system is connected to the SVG model.

[0063] From a system perspective, the LCC model and the SVG model operate collaboratively to jointly realize the operation of the adaptive commutation converter simulation model. The LCC rectifier-side control system and the LCC inverter-side control system acquire electrical quantities such as DC voltage for calculation, generating control commands to control the DC current of the LCC model. The SVG control system acquires electrical quantities to perform reactive power control calculation, capacitor voltage equalization control calculation, and harmonic compensation control calculation, and inputs the calculation results to the active and reactive power decoupling control for calculation, so as to output control commands to the SVG model. The LCC model and the SVG model are updated according to the corresponding control commands, and electrical quantities are exchanged at the connection branches. In this embodiment, the LCC model is an LCC converter composed of six thyristors.

[0064] The multi-rate decoupling algorithm based on the inductor discretization model specifically includes:

[0065] The inductor continuous model shown in equation (1) is discretized using the trapezoidal integral rule. Its schematic diagram is shown below. Figure 3 :

[0066]

[0067] Among them, u k (t) and u m (t) represents the instantaneous voltage at the node, i L(t) represents the branch current; to ensure high numerical fidelity of the linear passive network, the trapezoidal integration rule is adopted; for equation (1) at the time step Integrating within the inner quadrat, we get:

[0068]

[0069] Let the equivalent characteristic resistance be defined as To simplify the symbols, use the superscript "; " indicates the previous time step ( The value of ) is given by substituting the above definition into equation (3) and rearranging the terms to express the inductor voltage. The Thevenin equivalent model is obtained:

[0070]

[0071] Equation (3) shows that the voltage drop depends on the instantaneous current and the historical state; to achieve a decoupling interface, equation (4) is further expanded into a symmetrical form:

[0072]

[0073] Equation (4) elucidates the core principle of the inductor discretization method; by utilizing delay elements and controlled voltage sources, the inductor model can be conveniently divided into two symmetrical sub-circuits. For example... Figure 4 As shown, this mathematical structure enables the global system matrix to be decoupled at the inductor port.

[0074] Figure 4 This diagram illustrates the core mathematical model and engineering implementation principle of the multi-rate decoupling algorithm. Using an equivalent circuit model, it intuitively demonstrates how the CPU and FPGA can achieve stable and accurate joint simulation despite computational latency. This diagram forms the mathematical foundation for the successful integration and operation of the "CPU+FPGA heterogeneous computing architecture" and the "multi-rate decoupling algorithm." It proves that through this equivalent transformation, a physically strongly coupled SLCC system can be mathematically and safely decomposed into two weakly coupled, independently asynchronous subsystems, deployed on the CPU-side simulator and the FPGA-side simulator respectively. Ultimately, by exchanging "historical data," they collaboratively complete the high-precision real-time simulation of the entire system.

[0075] Since the interface algorithm is derived based on the trapezoidal integral transform, its spectral fidelity must be verified. The verification method is to compare the frequency response of the discretized inductor model with the frequency response of the continuous domain theoretical benchmark model. Figure 5The comparison and relative error between the two are shown. The simulation step size is set to 20 μs, and the inductance L is 0.5 mH. Within the frequency range of 0~5000 Hz, the maximum relative amplitude error does not exceed 3.3%, ensuring that the accuracy meets the error requirements of real-time simulation.

[0076] Figure 5 This is a comparison of the frequency characteristics of the discretized inductor model and the continuous-domain theoretical benchmark model. It is the core performance verification diagram of the multi-rate decoupling algorithm, and the figures from top to bottom are: Figure 5 (a) shows the amplitude-frequency response diagram. Figure 5 (b) shows the phase frequency response diagram and Figure 5 (c) shows the relative error plot. The amplitude-frequency response plot illustrates the change of system gain (output / input amplitude ratio) with frequency, and the phase-frequency response plot illustrates the change of phase delay of the system output relative to the input with frequency. The relative error plot quantifies the difference in frequency domain response between the discrete and continuous models. In FPGA and CPU co-simulation, the FPGA uses a smaller simulation step size (2μs), which means its sampling frequency is higher (500 kHz). Therefore, it can more accurately simulate high-frequency dynamic characteristics (such as the fast switching process of the SVG in the figure) and avoid falling into the high error region. For components that mainly involve low-frequency dynamics (such as power grids and slow control loops), the discretization model with a larger step size (20μs) on the CPU side is accurate and efficient enough because it operates in the low-frequency, low-error region of the error curve.

[0077] Rigorous frequency response analysis demonstrates that the inductor-based decoupling method can accurately represent the original continuous system within a 0-5kHz wideband with extremely high precision (error <3.3%), thus ensuring the reliability of the simulation results after decoupling between the CPU and FPGA. This is one of the key technical bases for the validity of this method and its superiority over traditional methods.

[0078] Figure 6 The simulation model is configured using a host computer. First, the FPGA+CPU simulation model runs according to the initial values ​​set by the host computer. Then, simulation timing begins. The CPU's rectifier-side grid model sends the calculated LCC AC-side electrical quantities to the FPGA via optical fiber, while the LCC AC-side and DC-side electrical quantities are sent to the CPU's LCC control system model. Next, the FPGA receives the LCC AC-side and SLCC AC-side electrical quantities and performs high-speed calculations, sending the results to the CPU's SLCC control model and inverter-side grid model. Afterward, each control model of the CPU judges the system's operating status and generates corresponding trigger signals, which are then sent back to the CPU's LCC model and the FPGA's SLCC model. Finally, the CPU and FPGA models are updated, and the next simulation cycle begins.

[0079] based on Figure 2 The architecture shown constructs a hardware-in-the-loop simulation platform to perform DC-side fault simulations on both the grid-commutated converter and the adaptive commutated converter, thereby obtaining transient response data of the system. In the attached figures, solid lines correspond to the operating data of the grid-commutated converter, and dashed lines correspond to the operating data of the adaptive commutated converter.

[0080] like Figure 7 As shown in (a), after a disturbance is applied, the DC voltage of the adaptive commutator recovers to a steady state in a shorter time than that of the grid commutator.

[0081] like Figure 7 (b) shows the AC-side reactive power waveform. During the disturbance period, the peak and fluctuation amplitude of the reactive power of the adaptive commutation converter are both smaller than those of the grid commutation converter. This waveform reflects the dynamic adjustment process of the static var generator on the AC-side reactive power in the adaptive commutation converter.

[0082] The simulation results show that the multi-timescale parallel interactive simulation method can output interactive operation data of the SVG model deployed on the FPGA side and the components deployed on the CPU side under fault transients, realizing the simulation of the fault characteristics of the adaptive commutator converter system.

[0083] Figure 7 The time-domain simulation results intuitively and powerfully demonstrate that the SLCC system model based on the CPU+FPGA heterogeneous simulation platform proposed in this invention has significant advantages in dynamic response and fault ride-through capability compared to the traditional LCC system.

[0084] Figure 8 illustrates the engineering implementation architecture of a multi-timescale parallel interactive simulation system based on the RT-LAB simulation platform, in which... Figure 8 (a) is a flowchart illustrating the deployment logic and real-time operation of the decoupling algorithm on the CPU model. Figure 8 (b) Data interaction diagram between CPU and FPGA Figure 8(c) is a flowchart illustrating the deployment logic and real-time operation of the decoupling algorithm on the FPGA model. This diagram intuitively and completely presents the deployment logic and real-time operation of the decoupling algorithm of this invention on CPU+FPGA heterogeneous hardware. Compared with traditional single-platform simulation solutions, this architecture can rely on the hardware resource scheduling capabilities of the RT-LAB platform to deploy the SVG model on the FPGA side to meet the high-frequency, high-precision simulation requirements, while deploying the rectifier side, inverter side, LCC-HVDC, and control system models on the CPU side to achieve efficient computation of large-scale systems. Simultaneously, real-time data exchange of the decoupled Thevenin equivalent sub-circuits is achieved through a cross-platform interaction interface. This implementation not only verifies the feasibility of the multi-rate decoupling algorithm on the RT-LAB platform but also further demonstrates the technical advantages of this invention in terms of decoupling efficiency of strongly coupled branches and simulation accuracy across multiple time scales through the real-time simulation results.

[0085] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A multi-timescale parallel interactive simulation method suitable for adaptive commutated converters, characterized in that, include: A CPU+FPGA heterogeneous computing architecture is constructed, which divides the adaptive commutator simulation model into a CPU-side simulator and an FPGA-side simulator according to the dynamic response characteristics of the components. The simulation step size of the CPU-side simulator is larger than that of the FPGA-side simulator; the components deployed in the CPU-side simulator include the rectifier-side model, DC-side model, inverter-side model, LCC model, LCC rectifier-side control system, LCC inverter-side control system, and SVG control system; the components deployed in the FPGA-side simulator include the SVG model. A multi-rate decoupling algorithm is used to decouple the connection branches between the components deployed on the CPU side and the components deployed on the FPGA side. The multi-rate decoupling algorithm is based on the inductor discretization model and decomposes the connection branch into two Thevenin equivalent sub-circuits that are independently calculated through historical terms. This allows the CPU-side and FPGA-side simulators to perform independent calculations based on their respective optimal simulation step sizes. Boundary data is exchanged through a communication interface, and the models and control systems deployed on the CPU side and FPGA side are updated in parallel based on the calculation results of the Thevenin equivalent sub-circuits. The multi-rate decoupling algorithm based on the inductor discretization model specifically includes: The inductance continuous model shown in equation (1) is discretized using the trapezoidal integral rule: Among them, u k (t) and u m (t) represents the instantaneous voltage at the node, i L (t) represents the branch current; to ensure high numerical fidelity of the linear passive network, the trapezoidal integration rule is adopted; for equation (1) at the time step Integrating within the inner quadrat, we get: Let the equivalent characteristic resistance be defined as To simplify the symbols, use the superscript "; " indicates the previous time step ( The value of ) is given by substituting the above definition into equation (3) and rearranging the terms to express the inductor voltage. Furthermore, the Thevenin equivalent model is obtained: Equation (3) shows that the voltage drop depends on the instantaneous current and the historical state; to achieve a decoupling interface, equation (4) is further expanded into a symmetrical form: Equation (4) clarifies the core principle of the inductor discretization segmentation method; by using delay elements and controlled voltage sources, the inductor model is conveniently segmented into two symmetrical sub-circuits; this mathematical structure enables the global system matrix to be decoupled at the inductor port.

2. The multi-timescale parallel interactive simulation method as described in claim 1, characterized in that, The multi-rate decoupling algorithm has a maximum relative amplitude error of no more than 3.3% in the frequency range of 0~5000Hz, and the CPU-side time step used for discretization is 20μs.

3. A simulation system for implementing the multi-timescale parallel interactive simulation method according to any one of claims 1 to 2, characterized in that, include: CPU-side simulator, configured to perform simulation calculations for CPU-side components; FPGA-side emulator, configured to perform simulation calculations for FPGA-side components; A high-speed communication module connects the emulator on the FPGA side and the emulator on the CPU side, and is configured to enable data interaction between the two sides.

4. The simulation system as described in claim 3, characterized in that, The CPU-side simulator deploys a rectifier-side model, a DC-side model, an inverter-side model, an LCC model, an LCC rectifier-side control system, an LCC inverter-side control system, and an SVG control system; the FPGA-side simulator deploys an SVG model.

5. The simulation system as described in claim 4, characterized in that, The high-speed communication module uses an optical fiber communication interface to transmit key electrical quantities such as commutation voltage and DC current, thereby reducing communication delay and electromagnetic interference.

6. A simulation model for implementing the multi-timescale parallel interactive simulation method according to any one of claims 1 to 2, characterized in that, This includes a simulator deployed on the CPU side, a simulator deployed on the FPGA side, and a communication interface connecting the CPU-side and FPGA-side simulators. The CPU-side simulator includes a rectifier-side model, a DC-side model, an inverter-side model, an LCC model, an LCC rectifier-side control system, an LCC inverter-side control system, and an SVG control system. The FPGA-side simulator includes an SVG model. The simulation step size of the CPU-side simulator is larger than that of the FPGA-side simulator. The rectifier-side model, DC-side model, and inverter-side model are connected sequentially. The LCC model is connected to the rectifier-side model and the inverter-side model, and the SVG model is connected to the rectifier-side model. The rectifier-side model is used to convert AC to DC and provide electrical quantities. The DC-side model is used to transmit DC electrical quantities. The inverter-side model is used to convert DC to AC and provide electrical quantities. The LCC model and SVG model are used to output electrical quantities and update them according to the corresponding control commands. Electrical quantities are interacted at the connection branches to complete one simulation cycle of the simulation system. Among them, the LCC rectifier-side control system is connected to the rectifier-side model, the LCC inverter-side control system is connected to the inverter-side model, the LCC rectifier-side control system and the LCC inverter-side control system are connected to the LCC model, and the SVG control system is connected to the SVG model.

7. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the multi-timescale parallel interactive simulation method according to any one of claims 1 to 2.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the multi-timescale parallel interactive simulation method according to any one of claims 1 to 2.

9. A multi-timescale parallel interactive simulation method suitable for adaptive commutated converters, characterized in that, It is applied to the simulation and verification of new power electronics topologies and is suitable for various laboratory environments.

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